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Mon, 10 Jun 2024 08:06:31 +0000 (GMT) Received: from li-ecc9ffcc-3485-11b2-a85c-e633c5126265.fritz.box (unknown [9.171.57.70]) by smtpav03.fra02v.mail.ibm.com (Postfix) with ESMTP for ; Mon, 10 Jun 2024 08:06:31 +0000 (GMT) From: Andreas Krebbel To: gcc-patches@gcc.gnu.org Subject: [Committed] IBM Z: Fix ICE in expand_perm_as_replicate Date: Mon, 10 Jun 2024 10:06:31 +0200 Message-ID: <20240610080631.189196-1-krebbel@linux.ibm.com> X-Mailer: git-send-email 2.45.1 MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: H3-Z8LUhLPu_JCxDIsnpg18onqTRcH3U X-Proofpoint-GUID: H3-Z8LUhLPu_JCxDIsnpg18onqTRcH3U X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-10_02,2024-06-06_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 clxscore=1015 adultscore=0 priorityscore=1501 impostorscore=0 mlxlogscore=842 suspectscore=0 malwarescore=0 spamscore=0 phishscore=0 bulkscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2405170001 definitions=main-2406100059 X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org The current implementation assumes to always be invoked with register operands. For memory operands we even have an instruction though (vlrep). With the patch we try this first and only if it fails force the input into a register and continue. vec_splats generation fails for single element 128bit types which are allowed for vec_splat. This is something to sort out with another patch I guess. Bootstrapped and regtested on IBM Z. Committed to mainline. Needs to be committed to GCC 14 branch as well. gcc/ChangeLog: * config/s390/s390.cc (expand_perm_as_replicate): Handle memory operands. * config/s390/vx-builtins.md (vec_splats): Turn into parameterized expander. (@vec_splats): New expander. gcc/testsuite/ChangeLog: * g++.dg/torture/vshuf-mem.C: New test. --- gcc/config/s390/s390.cc | 17 +++++++++++++-- gcc/config/s390/vx-builtins.md | 2 +- gcc/testsuite/g++.dg/torture/vshuf-mem.C | 27 ++++++++++++++++++++++++ 3 files changed, 43 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/g++.dg/torture/vshuf-mem.C diff --git a/gcc/config/s390/s390.cc b/gcc/config/s390/s390.cc index fa517bd3e77..ec836ec3cd4 100644 --- a/gcc/config/s390/s390.cc +++ b/gcc/config/s390/s390.cc @@ -17940,7 +17940,8 @@ expand_perm_as_replicate (const struct expand_vec_perm_d &d) unsigned char i; unsigned char elem; rtx base = d.op0; - rtx insn; + rtx insn = NULL_RTX; + /* Needed to silence maybe-uninitialized warning. */ gcc_assert (d.nelt > 0); elem = d.perm[0]; @@ -17954,7 +17955,19 @@ expand_perm_as_replicate (const struct expand_vec_perm_d &d) base = d.op1; elem -= d.nelt; } - insn = maybe_gen_vec_splat (d.vmode, d.target, base, GEN_INT (elem)); + if (memory_operand (base, d.vmode)) + { + /* Try to use vector load and replicate. */ + rtx new_base = adjust_address (base, GET_MODE_INNER (d.vmode), + elem * GET_MODE_UNIT_SIZE (d.vmode)); + insn = maybe_gen_vec_splats (d.vmode, d.target, new_base); + } + if (insn == NULL_RTX) + { + base = force_reg (d.vmode, base); + insn = maybe_gen_vec_splat (d.vmode, d.target, base, GEN_INT (elem)); + } + if (insn == NULL_RTX) return false; emit_insn (insn); diff --git a/gcc/config/s390/vx-builtins.md b/gcc/config/s390/vx-builtins.md index 93c0d408a43..bb271c09a7d 100644 --- a/gcc/config/s390/vx-builtins.md +++ b/gcc/config/s390/vx-builtins.md @@ -145,7 +145,7 @@ DONE; }) -(define_expand "vec_splats" +(define_expand "@vec_splats" [(set (match_operand:VEC_HW 0 "register_operand" "") (vec_duplicate:VEC_HW (match_operand: 1 "general_operand" "")))] "TARGET_VX") diff --git a/gcc/testsuite/g++.dg/torture/vshuf-mem.C b/gcc/testsuite/g++.dg/torture/vshuf-mem.C new file mode 100644 index 00000000000..5f1ebf65665 --- /dev/null +++ b/gcc/testsuite/g++.dg/torture/vshuf-mem.C @@ -0,0 +1,27 @@ +// { dg-options "-std=c++11" } +// { dg-do run } +// { dg-additional-options "-march=z14" { target s390*-*-* } } + +/* This used to trigger (2024-05-28) the vectorize_vec_perm_const + backend hook to be invoked with a MEM source operand. Extracted + from onnxruntime's mlas library. */ + +typedef float V4SF __attribute__((vector_size (16))); +typedef int V4SI __attribute__((vector_size (16))); + +template < unsigned I0, unsigned I1, unsigned I2, unsigned I3 > V4SF +MlasShuffleFloat32x4 (V4SF Vector) +{ + return __builtin_shuffle (Vector, Vector, V4SI{I0, I1, I2, I3}); +} + +int +main () +{ + V4SF f = { 1.0f, 2.0f, 3.0f, 4.0f }; + if (MlasShuffleFloat32x4 < 1, 1, 1, 1 > (f)[3] != 2.0f) + __builtin_abort (); + if (MlasShuffleFloat32x4 < 3, 3, 3, 3 > (f)[1] != 4.0f) + __builtin_abort (); + return 0; +}