From patchwork Fri Jun 7 13:51:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 1945098 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=dWU9oFZa; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4VwjLd1mg3z20PW for ; Fri, 7 Jun 2024 23:52:23 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 1382E398FBB9 for ; Fri, 7 Jun 2024 13:51:46 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) by sourceware.org (Postfix) with ESMTPS id 9D63A38EC7CB for ; Fri, 7 Jun 2024 13:51:12 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 9D63A38EC7CB Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 9D63A38EC7CB Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=198.175.65.12 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1717768284; cv=none; b=pHpgDR8YVuLyvX1sfzXmXiIr2DKtk3W7nQyT7xY/yrX9xp0Z7WkDJlqw+/bRgbsIf7j8GF5v30iZEw0M0SvnIbGVn2QVs0uAccJk/7G05rw+H/egaUJn9Mn9eeiZJel72CkwEjUMZYpcqx/eYsG7g3pmh0gGrpTyi43qxp5YrTk= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1717768284; c=relaxed/simple; bh=Cxdm+MNFNNYdugc/j8dyeXnCbNXw5w2MxSl6EQ/nyH8=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=I7H4CL+wZC4zJgzx4Infi1V88iav6aH7HY/lFXLdkZ8TvVF5rU9EJahG5YXgRf0qSmmZROUTGNY3QsIti3AY7AmL5/o+MrKncN16MrU0CyN4Vvu8ZfjszgEFNxd2gwbsnSBW3eIvXgLzWly/+BbxrzvZHKi6YiZXAj37qKopIs0= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1717768273; x=1749304273; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=Cxdm+MNFNNYdugc/j8dyeXnCbNXw5w2MxSl6EQ/nyH8=; b=dWU9oFZahh1+Ti7Nvy3XAZPgePXAMTCnjHN3vT1gWev9pRCCuZ93Os6p kc6WqcILdcLPG+sfqrl8m93YTlppiUVa1Ox3Dw9FOlBal47t1hRYlXbr9 F4cfV6YYETKJ51Yal9fYSQ2xuN7VnRH8p7qaXINuNSB4krDx8uQTPHBJR jRi1HQ2AVQodxXAuJrKMpoarhQjYCHWmL1KtCCMQwr6vq1NKkF2VTiNtX JNppMM2htUdK/xErcr9nO/g899BBXGBsdQH2snUActXwdq5t7edpyyHVM neySiQyvbF6l+kErz+13GwLE8IRuqizQSUWpOk5/GBDieSKwHCciMKgFS Q==; X-CSE-ConnectionGUID: K9czjTzVTpugBlbMr9iDSw== X-CSE-MsgGUID: skojiIENTVyeGelXjPPSCg== X-IronPort-AV: E=McAfee;i="6600,9927,11096"; a="25896641" X-IronPort-AV: E=Sophos;i="6.08,221,1712646000"; d="scan'208";a="25896641" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jun 2024 06:51:11 -0700 X-CSE-ConnectionGUID: EOlQjaGxSU2V3PiF4whWnw== X-CSE-MsgGUID: DFkenZGwRAi4ob0qI2CWqw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,221,1712646000"; d="scan'208";a="38450127" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmviesa009.fm.intel.com with ESMTP; 07 Jun 2024 06:51:05 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 1F3511007367; Fri, 7 Jun 2024 21:51:01 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, rdapp.gcc@gmail.com, Pan Li Subject: [PATCH v3] RISC-V: Implement .SAT_SUB for unsigned scalar int Date: Fri, 7 Jun 2024 21:51:00 +0800 Message-Id: <20240607135100.4135976-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_LOTSOFHASH, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li As the middle support of .SAT_SUB committed, implement the unsigned scalar int of .SAT_SUB for the riscv backend. Consider below example code: T __attribute__((noinline)) \ sat_u_sub_##T##_fmt_1 (T x, T y) \ { \ return (x - y) & (-(T)(x >= y)); \ } T __attribute__((noinline)) \ sat_u_sub_##T##_fmt_2 (T x, T y) \ { \ return (x - y) & (-(T)(x > y)); \ } DEF_SAT_U_SUB_FMT_1(uint64_t); DEF_SAT_U_SUB_FMT_2(uint64_t); Before this patch: sat_u_sub_uint64_t_fmt_1: bltu a0,a1,.L2 sub a0,a0,a1 ret .L2: li a0,0 ret After this patch: sat_u_sub_uint64_t_fmt_1: sltu a5,a0,a1 addi a5,a5,-1 sub a0,a0,a1 and a0,a5,a0 ret ToDo: Only above 2 forms of .SAT_SUB are support for now, we will support more forms of .SAT_SUB in the middle-end in short future. The below test suites are passed for this patch. * The rv64gcv fully regression test. gcc/ChangeLog: * config/riscv/riscv-protos.h (riscv_expand_ussub): Add new func decl for ussub expanding. * config/riscv/riscv.cc (riscv_expand_ussub): Ditto but for impl. * config/riscv/riscv.md (ussub3): Add new pattern ussub for scalar modes. gcc/testsuite/ChangeLog: * gcc.target/riscv/sat_arith.h: Add test macros and comments. * gcc.target/riscv/sat_u_sub-1.c: New test. * gcc.target/riscv/sat_u_sub-2.c: New test. * gcc.target/riscv/sat_u_sub-3.c: New test. * gcc.target/riscv/sat_u_sub-4.c: New test. * gcc.target/riscv/sat_u_sub-5.c: New test. * gcc.target/riscv/sat_u_sub-6.c: New test. * gcc.target/riscv/sat_u_sub-7.c: New test. * gcc.target/riscv/sat_u_sub-8.c: New test. * gcc.target/riscv/sat_u_sub-run-1.c: New test. * gcc.target/riscv/sat_u_sub-run-2.c: New test. * gcc.target/riscv/sat_u_sub-run-3.c: New test. * gcc.target/riscv/sat_u_sub-run-4.c: New test. * gcc.target/riscv/sat_u_sub-run-5.c: New test. * gcc.target/riscv/sat_u_sub-run-6.c: New test. * gcc.target/riscv/sat_u_sub-run-7.c: New test. * gcc.target/riscv/sat_u_sub-run-8.c: New test. Signed-off-by: Pan Li --- gcc/config/riscv/riscv-protos.h | 1 + gcc/config/riscv/riscv.cc | 35 +++++++++++++++++++ gcc/config/riscv/riscv.md | 11 ++++++ gcc/testsuite/gcc.target/riscv/sat_arith.h | 23 ++++++++++++ gcc/testsuite/gcc.target/riscv/sat_u_sub-1.c | 18 ++++++++++ gcc/testsuite/gcc.target/riscv/sat_u_sub-2.c | 19 ++++++++++ gcc/testsuite/gcc.target/riscv/sat_u_sub-3.c | 18 ++++++++++ gcc/testsuite/gcc.target/riscv/sat_u_sub-4.c | 17 +++++++++ gcc/testsuite/gcc.target/riscv/sat_u_sub-5.c | 18 ++++++++++ gcc/testsuite/gcc.target/riscv/sat_u_sub-6.c | 19 ++++++++++ gcc/testsuite/gcc.target/riscv/sat_u_sub-7.c | 18 ++++++++++ gcc/testsuite/gcc.target/riscv/sat_u_sub-8.c | 17 +++++++++ .../gcc.target/riscv/sat_u_sub-run-1.c | 25 +++++++++++++ .../gcc.target/riscv/sat_u_sub-run-2.c | 25 +++++++++++++ .../gcc.target/riscv/sat_u_sub-run-3.c | 25 +++++++++++++ .../gcc.target/riscv/sat_u_sub-run-4.c | 25 +++++++++++++ .../gcc.target/riscv/sat_u_sub-run-5.c | 25 +++++++++++++ .../gcc.target/riscv/sat_u_sub-run-6.c | 25 +++++++++++++ .../gcc.target/riscv/sat_u_sub-run-7.c | 25 +++++++++++++ .../gcc.target/riscv/sat_u_sub-run-8.c | 25 +++++++++++++ 20 files changed, 414 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-7.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-8.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-7.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-8.c diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 0704968561b..09eb3a574e3 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -134,6 +134,7 @@ extern bool riscv_zcmp_valid_stack_adj_bytes_p (HOST_WIDE_INT, int); extern void riscv_legitimize_poly_move (machine_mode, rtx, rtx, rtx); extern void riscv_expand_usadd (rtx, rtx, rtx); +extern void riscv_expand_ussub (rtx, rtx, rtx); #ifdef RTX_CODE extern void riscv_expand_int_scc (rtx, enum rtx_code, rtx, rtx, bool *invert_ptr = 0); diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 9704ff9c6a0..95f3636f8e4 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -11612,6 +11612,41 @@ riscv_expand_usadd (rtx dest, rtx x, rtx y) emit_move_insn (dest, gen_lowpart (mode, xmode_dest)); } +/* Implements the unsigned saturation sub standard name usadd for int mode. + + z = SAT_SUB(x, y). + => + 1. minus = x - y. + 2. lt = x < y. + 3. lt = lt - 1. + 4. z = minus & lt. */ + +void +riscv_expand_ussub (rtx dest, rtx x, rtx y) +{ + machine_mode mode = GET_MODE (dest); + rtx pmode_x = gen_lowpart (Pmode, x); + rtx pmode_y = gen_lowpart (Pmode, y); + rtx pmode_lt = gen_reg_rtx (Pmode); + rtx pmode_minus = gen_reg_rtx (Pmode); + rtx pmode_dest = gen_reg_rtx (Pmode); + + /* Step-1: minus = x - y */ + riscv_emit_binary (MINUS, pmode_minus, pmode_x, pmode_y); + + /* Step-2: lt = x < y */ + riscv_emit_binary (LTU, pmode_lt, pmode_x, pmode_y); + + /* Step-3: lt = lt - 1 (lt + (-1)) */ + riscv_emit_binary (PLUS, pmode_lt, pmode_lt, CONSTM1_RTX (Pmode)); + + /* Step-4: pmode_dest = minus & lt */ + riscv_emit_binary (AND, pmode_dest, pmode_lt, pmode_minus); + + /* Step-5: dest = pmode_dest */ + emit_move_insn (dest, gen_lowpart (mode, pmode_dest)); +} + /* Initialize the GCC target structure. */ #undef TARGET_ASM_ALIGNED_HI_OP #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t" diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index e57bfcf616a..7a9454de430 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -4228,6 +4228,17 @@ (define_expand "usadd3" } ) +(define_expand "ussub3" + [(match_operand:ANYI 0 "register_operand") + (match_operand:ANYI 1 "register_operand") + (match_operand:ANYI 2 "register_operand")] + "" + { + riscv_expand_ussub (operands[0], operands[1], operands[2]); + DONE; + } +) + ;; These are forms of (x << C1) + C2, potentially canonicalized from ;; ((x + C2') << C1. Depending on the cost to load C2 vs C2' we may ;; want to go ahead and recognize this form as C2 may be cheaper to diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat_arith.h index 976ef1c44c1..9c60ac09f41 100644 --- a/gcc/testsuite/gcc.target/riscv/sat_arith.h +++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h @@ -3,6 +3,9 @@ #include +/******************************************************************************/ +/* Saturation Add (unsigned and signed) */ +/******************************************************************************/ #define DEF_SAT_U_ADD_FMT_1(T) \ T __attribute__((noinline)) \ sat_u_add_##T##_fmt_1 (T x, T y) \ @@ -72,4 +75,24 @@ vec_sat_u_add_##T##_fmt_1 (T *out, T *op_1, T *op_2, unsigned limit) \ #define RUN_VEC_SAT_U_ADD_FMT_1(T, out, op_1, op_2, N) \ vec_sat_u_add_##T##_fmt_1(out, op_1, op_2, N) +/******************************************************************************/ +/* Saturation Sub (Unsigned and Signed) */ +/******************************************************************************/ +#define DEF_SAT_U_SUB_FMT_1(T) \ +T __attribute__((noinline)) \ +sat_u_sub_##T##_fmt_1 (T x, T y) \ +{ \ + return (x - y) & (-(T)(x >= y)); \ +} + +#define DEF_SAT_U_SUB_FMT_2(T) \ +T __attribute__((noinline)) \ +sat_u_sub_##T##_fmt_2 (T x, T y) \ +{ \ + return (x - y) & (-(T)(x > y)); \ +} + +#define RUN_SAT_U_SUB_FMT_1(T, x, y) sat_u_sub_##T##_fmt_1(x, y) +#define RUN_SAT_U_SUB_FMT_2(T, x, y) sat_u_sub_##T##_fmt_2(x, y) + #endif diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-1.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-1.c new file mode 100644 index 00000000000..73be7d59422 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-1.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_sub_uint8_t_fmt_1: +** sub\s+[atx][0-9]+,\s*a0,\s*a1 +** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 +** and\s+a0,\s*a0,\s*[atx][0-9]+ +** andi\s+a0,\s*a0,\s*0xff +** ret +*/ +DEF_SAT_U_SUB_FMT_1(uint8_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-2.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-2.c new file mode 100644 index 00000000000..7bd5efcd9d9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-2.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_sub_uint16_t_fmt_1: +** sub\s+[atx][0-9]+,\s*a0,\s*a1 +** sltu\s+[atx][0-9]+,\s*a0,\s*a1 +** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 +** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ +** slli\s+a0,\s*a0,\s*48 +** srli\s+a0,\s*a0,\s*48 +** ret +*/ +DEF_SAT_U_SUB_FMT_1(uint16_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-3.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-3.c new file mode 100644 index 00000000000..a60fc9ba71e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-3.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_sub_uint32_t_fmt_1: +** sub\s+[atx][0-9]+,\s*a0,\s*a1 +** sltu\s+[atx][0-9]+,\s*a0,\s*a1 +** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 +** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ +** sext.w\s+a0,\s*a0 +** ret +*/ +DEF_SAT_U_SUB_FMT_1(uint32_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-4.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-4.c new file mode 100644 index 00000000000..bae46a0bd83 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-4.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_sub_uint64_t_fmt_1: +** sub\s+[atx][0-9]+,\s*a0,\s*a1 +** sltu\s+[atx][0-9]+,\s*a0,\s*a1 +** addi\s+a0,\s*[atx][0-9]+,\s*-1 +** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ +** ret +*/ +DEF_SAT_U_SUB_FMT_1(uint64_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-5.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-5.c new file mode 100644 index 00000000000..e917487a640 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-5.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_sub_uint8_t_fmt_2: +** sub\s+[atx][0-9]+,\s*a0,\s*a1 +** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 +** and\s+a0,\s*a0,\s*[atx][0-9]+ +** andi\s+a0,\s*a0,\s*0xff +** ret +*/ +DEF_SAT_U_SUB_FMT_2(uint8_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-6.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-6.c new file mode 100644 index 00000000000..4e3c91d205d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-6.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_sub_uint16_t_fmt_2: +** sub\s+[atx][0-9]+,\s*a0,\s*a1 +** sltu\s+[atx][0-9]+,\s*a0,\s*a1 +** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 +** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ +** slli\s+a0,\s*a0,\s*48 +** srli\s+a0,\s*a0,\s*48 +** ret +*/ +DEF_SAT_U_SUB_FMT_2(uint16_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-7.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-7.c new file mode 100644 index 00000000000..e1b0eaccf95 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-7.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_sub_uint32_t_fmt_2: +** sub\s+[atx][0-9]+,\s*a0,\s*a1 +** sltu\s+[atx][0-9]+,\s*a0,\s*a1 +** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 +** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ +** sext.w\s+a0,\s*a0 +** ret +*/ +DEF_SAT_U_SUB_FMT_2(uint32_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-8.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-8.c new file mode 100644 index 00000000000..d73f00fcf02 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-8.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_sub_uint64_t_fmt_2: +** sub\s+[atx][0-9]+,\s*a0,\s*a1 +** sltu\s+[atx][0-9]+,\s*a0,\s*a1 +** addi\s+a0,\s*[atx][0-9]+,\s*-1 +** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ +** ret +*/ +DEF_SAT_U_SUB_FMT_2(uint64_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-1.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-1.c new file mode 100644 index 00000000000..931420a3098 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-1.c @@ -0,0 +1,25 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" + +#define T uint8_t +#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_1 + +DEF_SAT_U_SUB_FMT_1(T) + +T test_data[][3] = { + /* arg_0, arg_1, expect */ + { 0, 0, 0, }, + { 0, 1, 0, }, + { 1, 1, 0, }, + { 255, 254, 1, }, + { 255, 255, 0, }, + { 254, 255, 0, }, + { 253, 254, 0, }, + { 0, 255, 0, }, + { 1, 255, 0, }, + { 32, 5, 27, }, +}; + +#include "scalar_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-2.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-2.c new file mode 100644 index 00000000000..1534cf99827 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-2.c @@ -0,0 +1,25 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" + +#define T uint16_t +#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_1 + +DEF_SAT_U_SUB_FMT_1(T) + +T test_data[][3] = { + /* arg_0, arg_1, expect */ + { 0, 0, 0, }, + { 0, 1, 0, }, + { 1, 1, 0, }, + { 65535, 65534, 1, }, + { 65535, 65535, 0, }, + { 65534, 65535, 0, }, + { 65533, 65534, 0, }, + { 0, 65535, 0, }, + { 1, 65535, 0, }, + { 35, 5, 30, }, +}; + +#include "scalar_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-3.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-3.c new file mode 100644 index 00000000000..5c60d28997f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-3.c @@ -0,0 +1,25 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" + +#define T uint32_t +#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_1 + +DEF_SAT_U_SUB_FMT_1(T) + +T test_data[][3] = { + /* arg_0, arg_1, expect */ + { 0, 0, 0, }, + { 0, 1, 0, }, + { 1, 1, 0, }, + { 4294967295, 4294967294, 1, }, + { 4294967295, 4294967295, 0, }, + { 4294967294, 4294967295, 0, }, + { 4294967293, 4294967294, 0, }, + { 1, 4294967295, 0, }, + { 2, 4294967295, 0, }, + { 5, 1, 4, }, +}; + +#include "scalar_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-4.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-4.c new file mode 100644 index 00000000000..403764c8568 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-4.c @@ -0,0 +1,25 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" + +#define T uint64_t +#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_1 + +DEF_SAT_U_SUB_FMT_1(T) + +T test_data[][3] = { + /* arg_0, arg_1, expect */ + { 0, 0, 0, }, + { 0, 1, 0, }, + { 1, 1, 0, }, + { 18446744073709551615u, 18446744073709551614u, 1, }, + { 18446744073709551615u, 18446744073709551615u, 0, }, + { 18446744073709551614u, 18446744073709551615u, 0, }, + { 18446744073709551613u, 18446744073709551614u, 0, }, + { 0, 18446744073709551615u, 0, }, + { 1, 18446744073709551615u, 0, }, + { 43, 11, 32, }, +}; + +#include "scalar_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-5.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-5.c new file mode 100644 index 00000000000..6fa44ca323b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-5.c @@ -0,0 +1,25 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" + +#define T uint8_t +#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_2 + +DEF_SAT_U_SUB_FMT_2(T) + +T test_data[][3] = { + /* arg_0, arg_1, expect */ + { 0, 0, 0, }, + { 0, 1, 0, }, + { 1, 1, 0, }, + { 255, 254, 1, }, + { 255, 255, 0, }, + { 254, 255, 0, }, + { 253, 254, 0, }, + { 0, 255, 0, }, + { 1, 255, 0, }, + { 32, 5, 27, }, +}; + +#include "scalar_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-6.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-6.c new file mode 100644 index 00000000000..7deaae9a5fd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-6.c @@ -0,0 +1,25 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" + +#define T uint16_t +#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_2 + +DEF_SAT_U_SUB_FMT_2(T) + +T test_data[][3] = { + /* arg_0, arg_1, expect */ + { 0, 0, 0, }, + { 0, 1, 0, }, + { 1, 1, 0, }, + { 65535, 65534, 1, }, + { 65535, 65535, 0, }, + { 65534, 65535, 0, }, + { 65533, 65534, 0, }, + { 0, 65535, 0, }, + { 1, 65535, 0, }, + { 35, 5, 30, }, +}; + +#include "scalar_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-7.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-7.c new file mode 100644 index 00000000000..d9b1d5cbfe2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-7.c @@ -0,0 +1,25 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" + +#define T uint32_t +#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_2 + +DEF_SAT_U_SUB_FMT_2(T) + +T test_data[][3] = { + /* arg_0, arg_1, expect */ + { 0, 0, 0, }, + { 0, 1, 0, }, + { 1, 1, 0, }, + { 4294967295, 4294967294, 1, }, + { 4294967295, 4294967295, 0, }, + { 4294967294, 4294967295, 0, }, + { 4294967293, 4294967294, 0, }, + { 1, 4294967295, 0, }, + { 2, 4294967295, 0, }, + { 5, 1, 4, }, +}; + +#include "scalar_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-8.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-8.c new file mode 100644 index 00000000000..2774c235cc3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-8.c @@ -0,0 +1,25 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" + +#define T uint64_t +#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_2 + +DEF_SAT_U_SUB_FMT_2(T) + +T test_data[][3] = { + /* arg_0, arg_1, expect */ + { 0, 0, 0, }, + { 0, 1, 0, }, + { 1, 1, 0, }, + { 18446744073709551615u, 18446744073709551614u, 1, }, + { 18446744073709551615u, 18446744073709551615u, 0, }, + { 18446744073709551614u, 18446744073709551615u, 0, }, + { 18446744073709551613u, 18446744073709551614u, 0, }, + { 0, 18446744073709551615u, 0, }, + { 1, 18446744073709551615u, 0, }, + { 43, 11, 32, }, +}; + +#include "scalar_sat_binary.h"