From patchwork Fri Jun 7 11:14:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 1945038 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20201202 header.b=a9XYIGkt; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2604:1380:45d1:ec00::1; helo=ny.mirrors.kernel.org; envelope-from=devicetree+bounces-73619-incoming-dt=patchwork.ozlabs.org@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org [IPv6:2604:1380:45d1:ec00::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Vwdrg1vpFz20Q5 for ; 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arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717758875; cv=none; b=co/UlpIpNc4qgA3CXQGOLmJzeKK05FIm422p/YHtquV78+hKto8RM1PN+pu0t/i3mbQPjHeiu7itVPIflkmxKDRSdYBsd/7fEPZowK3OdQJP7ASh2UHc6wJB5aT8H+F9jp4SE8Ec5vV0OmyIu/0ox8xkr8yIBgsaSy/+Sri2Wlg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717758875; c=relaxed/simple; bh=snAgm64ySynk6RAed5xxHOvVSYB2c27PvNSsTeM0Z7Q=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=fMVbC5qSRQRpIKaLa+NZrlXmUz0rrk9vTSPjiq05ays8eklJhL+69AovsYa0kLebacBkVk8SWgy0gDKxFvJoF3/UqTemHDmvFIDvDylaDmuqROfQQ7DFh0F6ptS89ZuND+BoXpjjz1n5UsdsFOLwFsSejU1TPznFJUDCGFmX12Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=a9XYIGkt; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 08D49C4AF0D; Fri, 7 Jun 2024 11:14:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1717758874; bh=snAgm64ySynk6RAed5xxHOvVSYB2c27PvNSsTeM0Z7Q=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=a9XYIGktTUGug61XAYzRh8Ay83II2dU+xipqLEOCFFvrz55aibPhQavDEM3AMjYwr eBQRY55jn/G/drIK8M+zFbOmbx4Dr8QxaY5st79okeNbQcLFkhp9Z8Mu0ODF3lRQoT 9cY8ckfLnukfK+GYiOYe4uYYSk/WmX95OC8AncTNjkl4qligMHYRSJRF+3OjqUXP2b kHMbrByEkqlHSVSVlq9Td1MA9vzzCC3So7ADx9A71Q6uWIttRee22LlOthuuvt+o60 Q2/dYnsNO+YWJaBJngmxdYVDjqJEv5FjxxbMf/4KuO7aiGwwkTWgQS56bXtD69xpuq lgBjHahUP8Djw== From: Niklas Cassel Date: Fri, 07 Jun 2024 13:14:21 +0200 Subject: [PATCH v5 01/13] dt-bindings: PCI: snps,dw-pcie-ep: Add vendor specific reg-name Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240607-rockchip-pcie-ep-v1-v5-1-0a042d6b0049@kernel.org> References: <20240607-rockchip-pcie-ep-v1-v5-0-0a042d6b0049@kernel.org> In-Reply-To: <20240607-rockchip-pcie-ep-v1-v5-0-0a042d6b0049@kernel.org> To: Jingoo Han , Manivannan Sadhasivam , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Niklas Cassel , Kishon Vijay Abraham I , Arnd Bergmann , Damien Le Moal , Jon Lin , Shawn Lin , Simon Xue Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1367; i=cassel@kernel.org; h=from:subject:message-id; bh=snAgm64ySynk6RAed5xxHOvVSYB2c27PvNSsTeM0Z7Q=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNKSXk+c/04r1bFHskjqgogyS+iD27oBB4+K9v1bdPtdV d/9TGfRjlIWBjEuBlkxRRbfHy77i7vdpxxXvGMDM4eVCWQIAxenAEzkmR/D/xh213PMKq95Tpf/ /ak5/6M2axIL9/8ZLi8eBZXt/Dlfs4vhf4V5euQGd++ZyX2sByREl0ddWtN9WPKWbsadeFFn56X rGAA= X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA Considering that some drivers (e.g. pcie-dw-rockchip.c) already use the reg-name "apb" for the device tree binding in Root Complex mode (snps,dw-pcie.yaml), it doesn't make sense that those drivers should use a different reg-name when running in Endpoint mode (snps,dw-pcie-ep.yaml). Therefore, since "apb" is already defined in snps,dw-pcie.yaml, add it also for snps,dw-pcie-ep.yaml. Signed-off-by: Niklas Cassel Reviewed-by: Rob Herring (Arm) Reviewed-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml index bbdb01d22848..00dec01f1f73 100644 --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml @@ -100,7 +100,7 @@ properties: for new bindings. oneOf: - description: See native 'elbi/app' CSR region for details. - enum: [ link, appl ] + enum: [ apb, link, appl ] - description: See native 'atu' CSR region for details. enum: [ atu_dma ] allOf: From patchwork Fri Jun 7 11:14:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 1945041 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717758879; c=relaxed/simple; bh=G70B+FIi6b2LUEcgijriiOGQyyBBVbl1An3dk3fUHTg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=uRViSuFJt1+aFATOdVlx3xFFFmIENzliqi9kbP7Xn3Mf/D4WOgvi23r78/EpLSxSC++aBNswiUt7QjhggFDLiaHukpN8IjTaNo9lBJ1e5Z/J34hzfZr15Xz6KgfqDCs1bQc2ePnreq1MCBH9XV+P2LmGYbrvucHqBGhe+iw/HZU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=u887h5Ua; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 58150C2BBFC; Fri, 7 Jun 2024 11:14:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1717758879; bh=G70B+FIi6b2LUEcgijriiOGQyyBBVbl1An3dk3fUHTg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=u887h5UaoyOONY4FiqX78ZwqWPOytYssT381fEaC9y3OHHSvIR/st7unQpeD4uj+F gHK/ArrZKVvFsg2B9Aw7oVi6B290u90mk+L1oFQZXpeyc0Kv+qRfxU7iJnW3fyC8L9 kL2H6X4FJ70acEqkNLIyW6PzGT2RDm3wecaQnhUMMdvY0U0RMzDC8dXuqcX0CX0KLC 2CNvAGbSK0WtZq+lJnuQo3QXSVzIonBdGpAIfsUWMLe4YztsOU2p8x+9pL+1Pb/fG2 ZRu3PGRbJ/WONnvFr1eRH6coYjc21DJ/GibKKpHprszPh0SLUHl5axFasG7qH0lhkv JsRjq8jFnmRcw== From: Niklas Cassel Date: Fri, 07 Jun 2024 13:14:22 +0200 Subject: [PATCH v5 02/13] dt-bindings: PCI: snps,dw-pcie-ep: Add vendor specific interrupt-names Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240607-rockchip-pcie-ep-v1-v5-2-0a042d6b0049@kernel.org> References: <20240607-rockchip-pcie-ep-v1-v5-0-0a042d6b0049@kernel.org> In-Reply-To: <20240607-rockchip-pcie-ep-v1-v5-0-0a042d6b0049@kernel.org> To: Jingoo Han , Manivannan Sadhasivam , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Niklas Cassel , Kishon Vijay Abraham I , Arnd Bergmann , Damien Le Moal , Jon Lin , Shawn Lin , Simon Xue Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1338; i=cassel@kernel.org; h=from:subject:message-id; bh=G70B+FIi6b2LUEcgijriiOGQyyBBVbl1An3dk3fUHTg=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNKSXk+897DtZpMw76qmgC3Hpu3ev2L7qifJ7L9+vQ/X2 MqhoX9tVkcpC4MYF4OsmCKL7w+X/cXd7lOOK96xgZnDygQyhIGLUwAmYrSHkWGPxJXoqQxB4rcX 6u94f7Y9JuTLij1Hfpz3y/68eOuR/9uNGP4p/Tf7KnLTXbz70414oZuPrjrrp7tMidpx6MzGV/v MvLZyAwA= X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA Considering that some drivers (e.g. pcie-dw-rockchip.c) already use the interrupt-names "sys", "pmc", "msg", "err" for the device tree binding in Root Complex mode (snps,dw-pcie.yaml), it doesn't make sense that those drivers should use different interrupt-names when running in Endpoint mode (snps,dw-pcie-ep.yaml). Therefore, since "sys", "pmc", "msg", "err" are already defined in snps,dw-pcie.yaml, add them also for snps,dw-pcie-ep.yaml. Signed-off-by: Niklas Cassel Reviewed-by: Rob Herring (Arm) Reviewed-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml index 00dec01f1f73..f5f12cbc2cb3 100644 --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml @@ -156,7 +156,7 @@ properties: for new bindings. oneOf: - description: See native "app" IRQ for details - enum: [ intr ] + enum: [ intr, sys, pmc, msg, err ] max-functions: maximum: 32 From patchwork Fri Jun 7 11:14:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 1945043 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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Fri, 7 Jun 2024 11:14:47 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 49C2B18733D; Fri, 7 Jun 2024 11:14:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="EjWK+86C" X-Original-To: devicetree@vger.kernel.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 088EE14F11B; Fri, 7 Jun 2024 11:14:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717758884; cv=none; b=kNEpGEbEHNUJeO2Qwpud8M87mATkiU8FT05iaOLf/qLr7jZ3bw6agmxynmZhtZUejR76wgo/yUclwtS3ka6zpdrSC/1okMzzXObjn+90jNBmkeYkpNIbVRVij0s3HAHY1PasGCFFyiXxjMNb+J/N7bRROP4juYq3blOEwG0Zdlc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717758884; c=relaxed/simple; bh=0ArQlCvHIIXLagRFXrfsGxVZ7s8NLv5FvY16U5TNFcc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=peHC22Zx+2Oeb0kYarO2HmnAgEXneFDokrGq0ltWlQGDJDHmLhltyZbResFgrQ0BGv/RkQHPTFQD0fOnZxQGQlhw1x3ZKHAd9TXml/rfIo2tRYOT2gfVBnGP4hCybZJn/TXD83YrDLCDwUh4Eanl2CJkioUdc6x6dWKeR1vfz2E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=EjWK+86C; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id A76AEC4AF07; Fri, 7 Jun 2024 11:14:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1717758883; bh=0ArQlCvHIIXLagRFXrfsGxVZ7s8NLv5FvY16U5TNFcc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=EjWK+86C+IwPuNGJ7G+aL7euUVjHMwR59DX3jnJpNUG1O/hTyiGLWMU+MeC8Hpwil AM0JYpXAqtXeEGrmvwnWfDzAiSwoUgnQg1UgyVGpMOKbSCN0V0FDzew4SugzySNxdl sUaEXbg0zmZBQb2Z6Gxf4lHu2ovz2lQRSHjEBYVeqKPbkS1/lt7nY3VK8KQT1eEKSy n71rCrI6fc36H47rYeot953Yjhg9Prx8KsBgXw+c+oei1oTd3VD9QegrVHNONiVofD oSTcgspYBGNBpE6sjv3tp+5W9LtGfoAhwbNcdknj8vYhyo2mtz/tatQGkVCJv1t5DN QIBjfcwC/hA3A== From: Niklas Cassel Date: Fri, 07 Jun 2024 13:14:23 +0200 Subject: [PATCH v5 03/13] dt-bindings: PCI: snps,dw-pcie-ep: Add tx_int{a,b,c,d} legacy irqs Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240607-rockchip-pcie-ep-v1-v5-3-0a042d6b0049@kernel.org> References: <20240607-rockchip-pcie-ep-v1-v5-0-0a042d6b0049@kernel.org> In-Reply-To: <20240607-rockchip-pcie-ep-v1-v5-0-0a042d6b0049@kernel.org> To: Jingoo Han , Manivannan Sadhasivam , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Niklas Cassel , Kishon Vijay Abraham I , Arnd Bergmann , Damien Le Moal , Jon Lin , Shawn Lin , Simon Xue Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1743; i=cassel@kernel.org; h=from:subject:message-id; bh=0ArQlCvHIIXLagRFXrfsGxVZ7s8NLv5FvY16U5TNFcc=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNKSXk+sbPnG7ZJUeUrxxCWWArn4Vy5lczRk5j3WfJKyY 01Of8jPjlIWBjEuBlkxRRbfHy77i7vdpxxXvGMDM4eVCWQIAxenAEzk3WJGhmkBL7V+iqUvfhIv KPmm88ZKz68t5ev+Zm2c/MEn+lu84gqGf+p8/1MnyVxW7mzhOJLU67/mmeXr78ZXX8g8FA5f8sw 8hBcA X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA The DWC core has four interrupt signals: tx_inta, tx_intb, tx_intc, tx_intd that are triggered when the PCIe controller (when running in Endpoint mode) has sent an Assert_INTA Message to the upstream device. Some DWC controllers have these interrupt in a combined interrupt signal. Add the description of these interrupts to the device tree binding. Signed-off-by: Niklas Cassel Reviewed-by: Rob Herring (Arm) Reviewed-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml index f5f12cbc2cb3..f474b9e3fc7e 100644 --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml @@ -151,6 +151,15 @@ properties: Application-specific IRQ raised depending on the vendor-specific events basis. const: app + - description: + Interrupts triggered when the controller itself (in Endpoint mode) + has sent an Assert_INT{A,B,C,D}/Desassert_INT{A,B,C,D} message to + the upstream device. + pattern: "^tx_int(a|b|c|d)$" + - description: + Combined interrupt signal raised when the controller has sent an + Assert_INT{A,B,C,D} message. See "^tx_int(a|b|c|d)$" for details. + const: legacy - description: Vendor-specific IRQ names. Consider using the generic names above for new bindings. From patchwork Fri Jun 7 11:14:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 1945044 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20201202 header.b=lDqy/3U7; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2604:1380:40f1:3f00::1; helo=sy.mirrors.kernel.org; envelope-from=devicetree+bounces-73622-incoming-dt=patchwork.ozlabs.org@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org [IPv6:2604:1380:40f1:3f00::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Vwdrq1Cg0z20QJ for ; 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a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1717758887; bh=LMjwYuvyKA1YAKV2HODt4aKJwV3L3lQE3Wy4MEim00w=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=lDqy/3U7vkwac/SZKhxKkAqeXDUvwUy/sSJIB/4NFMwUUeMzp81eegzB7Xin1d0Iy GNSrfwnxetujeFn+LXwnDvDftwLglMJOHxTCyFxD00Gif8Kx6KEnOrdlCgbKHK7of3 3jjas16G4ZnFYMduTgNqjckwrPaJFOwESuEwBXxbPpNgd4KaXiZP1WCCHjhMBD78tq L43CEglDvu/CPSyAr64kKg7LeWfAPhnc46JyuYiTuo8Su37cGzu/Uzyrxl6Pf5645V xwXKIEWb0lDbxLaGBnfqPi9F+uQ/OBB3AWHw3W7Cp8vfUaHdQeX1I2QoY8XnmTZMPS 0w+AMjV5qmyEQ== From: Niklas Cassel Date: Fri, 07 Jun 2024 13:14:24 +0200 Subject: [PATCH v5 04/13] dt-bindings: PCI: rockchip-dw-pcie: Prepare for Endpoint mode support Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240607-rockchip-pcie-ep-v1-v5-4-0a042d6b0049@kernel.org> References: <20240607-rockchip-pcie-ep-v1-v5-0-0a042d6b0049@kernel.org> In-Reply-To: <20240607-rockchip-pcie-ep-v1-v5-0-0a042d6b0049@kernel.org> To: Jingoo Han , Manivannan Sadhasivam , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Niklas Cassel , Kishon Vijay Abraham I , Arnd Bergmann , Damien Le Moal , Jon Lin , Shawn Lin , Simon Xue Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=8140; i=cassel@kernel.org; h=from:subject:message-id; bh=LMjwYuvyKA1YAKV2HODt4aKJwV3L3lQE3Wy4MEim00w=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNKSXk/01LIJa3sT6JKTt3ha0ZW0Z4E63x5z9QqsOrqh5 fTX4wkPOkpZGMS4GGTFFFl8f7jsL+52n3Jc8Y4NzBxWJpAhDFycAjCR7BKG/4Exq/ZN5Dj3TOtu 9eWIBTs6w1zePf247lFfKv/LcJ+ig90M/8uV0k91G735sdhL4ZD1Vk3XkxztX7KE649Hq5UrRcz VYQYA X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA Refactor the rockchip-dw-pcie binding to move generic properties to a new rockchip-dw-pcie-common binding that can be shared by both RC and EP mode. No functional change intended. Signed-off-by: Niklas Cassel Reviewed-by: Rob Herring (Arm) Reviewed-by: Manivannan Sadhasivam --- .../bindings/pci/rockchip-dw-pcie-common.yaml | 111 +++++++++++++++++++++ .../devicetree/bindings/pci/rockchip-dw-pcie.yaml | 93 +---------------- 2 files changed, 114 insertions(+), 90 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml new file mode 100644 index 000000000000..60d190a77580 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml @@ -0,0 +1,111 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: DesignWare based PCIe RC/EP controller on Rockchip SoCs + +maintainers: + - Shawn Lin + - Simon Xue + - Heiko Stuebner + +description: |+ + Generic properties for the DesignWare based PCIe RC/EP controller on Rockchip + SoCs. + +properties: + clocks: + minItems: 5 + items: + - description: AHB clock for PCIe master + - description: AHB clock for PCIe slave + - description: AHB clock for PCIe dbi + - description: APB clock for PCIe + - description: Auxiliary clock for PCIe + - description: PIPE clock + - description: Reference clock for PCIe + + clock-names: + minItems: 5 + items: + - const: aclk_mst + - const: aclk_slv + - const: aclk_dbi + - const: pclk + - const: aux + - const: pipe + - const: ref + + interrupts: + items: + - description: + Combined system interrupt, which is used to signal the following + interrupts - phy_link_up, dll_link_up, link_req_rst_not, hp_pme, + hp, hp_msi, link_auto_bw, link_auto_bw_msi, bw_mgt, bw_mgt_msi, + edma_wr, edma_rd, dpa_sub_upd, rbar_update, link_eq_req, ep_elbi_app + - description: + Combined PM interrupt, which is used to signal the following + interrupts - linkst_in_l1sub, linkst_in_l1, linkst_in_l2, + linkst_in_l0s, linkst_out_l1sub, linkst_out_l1, linkst_out_l2, + linkst_out_l0s, pm_dstate_update + - description: + Combined message interrupt, which is used to signal the following + interrupts - ven_msg, unlock_msg, ltr_msg, cfg_pme, cfg_pme_msi, + pm_pme, pm_to_ack, pm_turnoff, obff_idle, obff_obff, obff_cpu_active + - description: + Combined legacy interrupt, which is used to signal the following + interrupts - inta, intb, intc, intd + - description: + Combined error interrupt, which is used to signal the following + interrupts - aer_rc_err, aer_rc_err_msi, rx_cpl_timeout, + tx_cpl_timeout, cor_err_sent, nf_err_sent, f_err_sent, cor_err_rx, + nf_err_rx, f_err_rx, radm_qoverflow + + interrupt-names: + items: + - const: sys + - const: pmc + - const: msg + - const: legacy + - const: err + + num-lanes: true + + phys: + maxItems: 1 + + phy-names: + const: pcie-phy + + power-domains: + maxItems: 1 + + resets: + minItems: 1 + maxItems: 2 + + reset-names: + oneOf: + - const: pipe + - items: + - const: pwr + - const: pipe + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - num-lanes + - phys + - phy-names + - power-domains + - resets + - reset-names + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml index 5f719218c472..550d8a684af3 100644 --- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: DesignWare based PCIe controller on Rockchip SoCs +title: DesignWare based PCIe Root Complex controller on Rockchip SoCs maintainers: - Shawn Lin @@ -12,12 +12,13 @@ maintainers: - Heiko Stuebner description: |+ - RK3568 SoC PCIe host controller is based on the Synopsys DesignWare + RK3568 SoC PCIe Root Complex controller is based on the Synopsys DesignWare PCIe IP and thus inherits all the common properties defined in snps,dw-pcie.yaml. allOf: - $ref: /schemas/pci/snps,dw-pcie.yaml# + - $ref: /schemas/pci/rockchip-dw-pcie-common.yaml# properties: compatible: @@ -40,61 +41,6 @@ properties: - const: apb - const: config - clocks: - minItems: 5 - items: - - description: AHB clock for PCIe master - - description: AHB clock for PCIe slave - - description: AHB clock for PCIe dbi - - description: APB clock for PCIe - - description: Auxiliary clock for PCIe - - description: PIPE clock - - description: Reference clock for PCIe - - clock-names: - minItems: 5 - items: - - const: aclk_mst - - const: aclk_slv - - const: aclk_dbi - - const: pclk - - const: aux - - const: pipe - - const: ref - - interrupts: - items: - - description: - Combined system interrupt, which is used to signal the following - interrupts - phy_link_up, dll_link_up, link_req_rst_not, hp_pme, - hp, hp_msi, link_auto_bw, link_auto_bw_msi, bw_mgt, bw_mgt_msi, - edma_wr, edma_rd, dpa_sub_upd, rbar_update, link_eq_req, ep_elbi_app - - description: - Combined PM interrupt, which is used to signal the following - interrupts - linkst_in_l1sub, linkst_in_l1, linkst_in_l2, - linkst_in_l0s, linkst_out_l1sub, linkst_out_l1, linkst_out_l2, - linkst_out_l0s, pm_dstate_update - - description: - Combined message interrupt, which is used to signal the following - interrupts - ven_msg, unlock_msg, ltr_msg, cfg_pme, cfg_pme_msi, - pm_pme, pm_to_ack, pm_turnoff, obff_idle, obff_obff, obff_cpu_active - - description: - Combined legacy interrupt, which is used to signal the following - interrupts - inta, intb, intc, intd - - description: - Combined error interrupt, which is used to signal the following - interrupts - aer_rc_err, aer_rc_err_msi, rx_cpl_timeout, - tx_cpl_timeout, cor_err_sent, nf_err_sent, f_err_sent, cor_err_rx, - nf_err_rx, f_err_rx, radm_qoverflow - - interrupt-names: - items: - - const: sys - - const: pmc - - const: msg - - const: legacy - - const: err - legacy-interrupt-controller: description: Interrupt controller node for handling legacy PCI interrupts. type: object @@ -119,47 +65,14 @@ properties: msi-map: true - num-lanes: true - - phys: - maxItems: 1 - - phy-names: - const: pcie-phy - - power-domains: - maxItems: 1 - ranges: minItems: 2 maxItems: 3 - resets: - minItems: 1 - maxItems: 2 - - reset-names: - oneOf: - - const: pipe - - items: - - const: pwr - - const: pipe - vpcie3v3-supply: true required: - - compatible - - reg - - reg-names - - clocks - - clock-names - msi-map - - num-lanes - - phys - - phy-names - - power-domains - - resets - - reset-names unevaluatedProperties: false From patchwork Fri Jun 7 11:14:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 1945047 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: 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bh=YBd0KTeYI4LPzEdWB+dde91dnzjhiAIa4BUjAunYhAM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=uGEOQcp5y24etqgOhR5hA7h68TvmWcAynZeBOdCiY/lzcm9nk9UPHqp1sByFT9sxn bvzlQxvZIhXKKUUfWhZcatkpDZ74YEe8hF/8kL1new/Fj3ahYl1FUyRNZaknHjK0SM MzyyPd6RFHsU467WLJcsVDIZrvrUjWeFD+KJrAozhK9mbNYM4N1JRcDeGMZcIa9uCi jww/zGRsYrHUlJkLUaXYwCOmdh4VdHARA3csf1t1aheWuah52PQi8FxqeavKnIR/Q2 +joNoIdleKp1JjtkR8yHzQ/I7bDPk4wzi2c9SmceEIk+6zIBF/euxdA6JvcXlqPTHI SNp5gxh3BlMNA== From: Niklas Cassel Date: Fri, 07 Jun 2024 13:14:25 +0200 Subject: [PATCH v5 05/13] dt-bindings: PCI: rockchip-dw-pcie: Fix description of legacy irq Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240607-rockchip-pcie-ep-v1-v5-5-0a042d6b0049@kernel.org> References: <20240607-rockchip-pcie-ep-v1-v5-0-0a042d6b0049@kernel.org> In-Reply-To: <20240607-rockchip-pcie-ep-v1-v5-0-0a042d6b0049@kernel.org> To: Jingoo Han , Manivannan Sadhasivam , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Niklas Cassel , Kishon Vijay Abraham I , Arnd Bergmann , Damien Le Moal , Jon Lin , Shawn Lin , Simon Xue Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2021; i=cassel@kernel.org; h=from:subject:message-id; bh=YBd0KTeYI4LPzEdWB+dde91dnzjhiAIa4BUjAunYhAM=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNKSXk/kaP9wUJ/3zktWh4Zj/eGFBhZ+RldkYzbOuSs9L ffEo5XOHaUsDGJcDLJiiiy+P1z2F3e7TzmueMcGZg4rE8gQBi5OAZiIhDgjw+puyRtbmplmNXEm p/N4Rkh3f/1uuZw98gjr5ljf7UaHbjP8r+A59zlMsXV3vR2PdJOlz8vow3J+1meZknc+n3isO1C ZGwA= X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA The descriptions of the combined interrupt signals (level1) mention all the lower interrupt signals (level2) for each combined interrupt, regardless if the lower (level2) signal is RC or EP specific. E.g. the description of "Combined system interrupt" includes rbar_update, which is EP specific, and the description of "Combined message interrupt" includes obff_idle, obff_obff, obff_cpu_active, which are all EP specific. The only exception is the "Combined legacy interrupt", which for some reason does not provide an exhaustive list of the lower (level2) signals. Add the missing lower interrupt signals: tx_inta, tx_intb, tx_intc, and tx_intd for the "Combined legacy interrupt", as per the rk3568 and rk3588 Technical Reference Manuals, such that the descriptions of the combined interrupt signals are consistent. Signed-off-by: Niklas Cassel Reviewed-by: Rob Herring (Arm) Reviewed-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml index 60d190a77580..ec5e6a3d048e 100644 --- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml @@ -56,7 +56,8 @@ properties: pm_pme, pm_to_ack, pm_turnoff, obff_idle, obff_obff, obff_cpu_active - description: Combined legacy interrupt, which is used to signal the following - interrupts - inta, intb, intc, intd + interrupts - inta, intb, intc, intd, tx_inta, tx_intb, tx_intc, + tx_intd - description: Combined error interrupt, which is used to signal the following interrupts - aer_rc_err, aer_rc_err_msi, rx_cpl_timeout, From patchwork Fri Jun 7 11:14:26 2024 Content-Type: text/plain; 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a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1717758896; bh=GGlA3OAgjgdkRU7hv++14P6DsJjnunw2b/F+pDu45nA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=m5fel8e3Up+j9BenOM/5g8EsKHB0cKykqoR7TtUZr6VU+Up+e7r0MuOYoQn4IZe5o qSLB2SN+48BrGBHma1kZ2cwZ9Jj8iX//UjZkgGGjTq7nWcIAsLIPp0j88alVCC0xsu MgL+5bb+rqM1j5UGYg4eh2Zwh3XHNXBrq389zzefXEMfqcwn/xaQhH0wU4sRO0u5mk nfuQdm5V/oU/K3yn0k2Ub5T6T0gAVoUc/3sRoY3CZjbCeNjMH7oQfJqimuTBG84eHU cZ5HXI9/CPesW7qRhMzn1CDU5vrcFTDpX5rNBoNpkcFEJoXNCm9eNcgkqdc4Xed9BJ 8AvypkQYwsnGw== From: Niklas Cassel Date: Fri, 07 Jun 2024 13:14:26 +0200 Subject: [PATCH v5 06/13] dt-bindings: rockchip: Add DesignWare based PCIe Endpoint controller Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240607-rockchip-pcie-ep-v1-v5-6-0a042d6b0049@kernel.org> References: <20240607-rockchip-pcie-ep-v1-v5-0-0a042d6b0049@kernel.org> In-Reply-To: <20240607-rockchip-pcie-ep-v1-v5-0-0a042d6b0049@kernel.org> To: Jingoo Han , Manivannan Sadhasivam , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Niklas Cassel , Kishon Vijay Abraham I , Arnd Bergmann , Damien Le Moal , Jon Lin , Shawn Lin , Simon Xue Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=5615; i=cassel@kernel.org; h=from:subject:message-id; bh=GGlA3OAgjgdkRU7hv++14P6DsJjnunw2b/F+pDu45nA=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNKSXk/cJpanMfP4wjXq0sY+zO/yt21nSBds+hJspnmqZ /6RW1v2dZSyMIhxMciKKbL4/nDZX9ztPuW44h0bmDmsTCBDGLg4BWAiv2wZGRqK3KoUJ0q9P1sk ELX7QtKK5p2n9ujsXfPukP+k8xITZI4zMrxbovZftXpGT+/nyXbHGVq1d8y1s46+4HD1y+/a2zM kD3ECAA== X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA Document DT bindings for PCIe Endpoint controller found in Rockchip SoCs. Signed-off-by: Niklas Cassel Reviewed-by: Rob Herring (Arm) Reviewed-by: Manivannan Sadhasivam --- .../bindings/pci/rockchip-dw-pcie-common.yaml | 14 ++++ .../bindings/pci/rockchip-dw-pcie-ep.yaml | 95 ++++++++++++++++++++++ 2 files changed, 109 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml index ec5e6a3d048e..cc9adfc7611c 100644 --- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml @@ -39,6 +39,7 @@ properties: - const: ref interrupts: + minItems: 5 items: - description: Combined system interrupt, which is used to signal the following @@ -63,14 +64,27 @@ properties: interrupts - aer_rc_err, aer_rc_err_msi, rx_cpl_timeout, tx_cpl_timeout, cor_err_sent, nf_err_sent, f_err_sent, cor_err_rx, nf_err_rx, f_err_rx, radm_qoverflow + - description: + eDMA write channel 0 interrupt + - description: + eDMA write channel 1 interrupt + - description: + eDMA read channel 0 interrupt + - description: + eDMA read channel 1 interrupt interrupt-names: + minItems: 5 items: - const: sys - const: pmc - const: msg - const: legacy - const: err + - const: dma0 + - const: dma1 + - const: dma2 + - const: dma3 num-lanes: true diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-ep.yaml new file mode 100644 index 000000000000..f2d1137aff50 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-ep.yaml @@ -0,0 +1,95 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie-ep.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: DesignWare based PCIe Endpoint controller on Rockchip SoCs + +maintainers: + - Niklas Cassel + +description: |+ + RK3588 SoC PCIe Endpoint controller is based on the Synopsys DesignWare + PCIe IP and thus inherits all the common properties defined in + snps,dw-pcie-ep.yaml. + +allOf: + - $ref: /schemas/pci/snps,dw-pcie-ep.yaml# + - $ref: /schemas/pci/rockchip-dw-pcie-common.yaml# + +properties: + compatible: + enum: + - rockchip,rk3568-pcie-ep + - rockchip,rk3588-pcie-ep + + reg: + items: + - description: Data Bus Interface (DBI) registers + - description: Data Bus Interface (DBI) shadow registers + - description: Rockchip designed configuration registers + - description: Memory region used to map remote RC address space + - description: Internal Address Translation Unit (iATU) registers + + reg-names: + items: + - const: dbi + - const: dbi2 + - const: apb + - const: addr_space + - const: atu + +required: + - interrupts + - interrupt-names + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie3x4_ep: pcie-ep@fe150000 { + compatible = "rockchip,rk3588-pcie-ep"; + reg = <0xa 0x40000000 0x0 0x00100000>, + <0xa 0x40100000 0x0 0x00100000>, + <0x0 0xfe150000 0x0 0x00010000>, + <0x9 0x00000000 0x0 0x40000000>, + <0xa 0x40300000 0x0 0x00100000>; + reg-names = "dbi", "dbi2", "apb", "addr_space", "atu"; + clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, + <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, + <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "sys", "pmc", "msg", "legacy", "err", + "dma0", "dma1", "dma2", "dma3"; + max-link-speed = <3>; + num-lanes = <4>; + phys = <&pcie30phy>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; + reset-names = "pwr", "pipe"; + }; + }; +...