From patchwork Thu Jun 6 09:22:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Philip Oberfichtner X-Patchwork-Id: 1944522 X-Patchwork-Delegate: rfried.dev@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=denx.de header.i=@denx.de header.a=rsa-sha256 header.s=phobos-20191101 header.b=Lkitb14O; dkim=pass (2048-bit key) header.d=denx.de header.i=@denx.de header.a=rsa-sha256 header.s=phobos-20191101 header.b=xo3jsEOz; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4VvzPh6dD9z20PW for ; Thu, 6 Jun 2024 19:22:32 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 335C0883E3; Thu, 6 Jun 2024 11:22:20 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1717665740; bh=Ez9z+95LH4CLZHB2SgRGvQmtSik9xPXGjZ3/RYbSxNY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=Lkitb14Orz8EEQZg/5ja7oEIlO5jl1VGYHrKWjm7WQeFDjVZ2PUGVE/PZOGWeIWyk 8kAJjp32f68rzpNfQjjHzslK5+Lc+CS1GWW3HqL/KteYlUvmVFCFPJf0rS6nobvvoE NwwYiW0bp6y4dvf4GVnkHRTrkw/yxJEsYbcaV+kU/BOFz6hY8WVoDMMHzXsRKmn7d5 6Ita4+yayRihpTK4g2jp4ARFISZvSBoMsm+quFwznD5JrZwMcbEoq1JugkjWEQ2XYv 3zDwdjZxRJESqQN/ehIhS6kP91NKN6Oyz0sdsmWUxkNt9tI9iXcigqrZovvX6/OQ67 t0ItbZ0WQEgGw== Received: from localhost (unknown [IPv6:2001:861:52:5f60:ff6c:4545:dfcf:4c97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: pro@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id 9639F881B8; Thu, 6 Jun 2024 11:22:18 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1717665738; bh=Ez9z+95LH4CLZHB2SgRGvQmtSik9xPXGjZ3/RYbSxNY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=xo3jsEOzEjMmBm9UG6JgQ18pm2R/+7CDDnltKw2qUGypY3lpat32uMDv7gqGoWv3m 2iquXrt8x8Gtm6F2m9b2P92d/XO2k9mF5YEskWq9oDz04zK/owTSIHq1e20CIuJhbC zr+tXGhIfavR4fzEbmfeYbtriuXxYThQPNVJEczM6X5uqjAid7hRu98KazxK0j/Zku +nTJz7CMOhYS+rM2psXr7xug0kmDx4jjrmUEO7B5WImjup6ca1Cl5+afH8tmgttQfA 0vDWChSPWHzXphVgi9ZVkc+vE50zFHTiwn4/W6tpZ/prmNWIB6WpcnpL6v/WAA1Q2Z ZLa7FAbby73vA== From: Philip Oberfichtner To: u-boot@lists.denx.de Cc: bmeng.cn@gmail.com, caleb.connolly@linaro.org, christophe.roullier@foss.st.com, epsi@gmx.de, eugen.hristev@collabora.com, festevam@gmail.com, forbidden405@outlook.com, ivprusov@salutedevices.com, joe.hershberger@ni.com, jonas@kwiboo.se, kever.yang@rock-chips.com, leyfoon.tan@starfivetech.com, marek.vasut+renesas@mailbox.org, marjolaine.amate@odyssee-systemes.fr, neil.armstrong@linaro.org, n-francis@ti.com, patrice.chotard@foss.st.com, patrick.delaunay@foss.st.com, philipp.tomsich@vrull.eu, rfried.dev@gmail.com, seanga2@gmail.com, sebastian.reichel@collabora.com, sebastien.szymanski@armadeus.com, sjg@chromium.org, sumit.garg@linaro.org, trini@konsulko.com, xypron.glpk@gmx.de, Philip Oberfichtner Subject: [PATCH v2 1/5] x86: provide mb() macro Date: Thu, 6 Jun 2024 11:22:03 +0200 Message-Id: <20240606092207.87816-2-pro@denx.de> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240606092207.87816-1-pro@denx.de> References: <20240606092207.87816-1-pro@denx.de> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Implement memory barrier using mfence. Linux does it equivalently [1]. "The MFENCE instruction establishes a memory fence for both loads and stores" [2]. [1] linux/arch/x86/include/asm/barrier.h [2] Intel® 64 and IA-32 Architectures Software Developer’s Manual Signed-off-by: Philip Oberfichtner --- arch/x86/include/asm/io.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/io.h b/arch/x86/include/asm/io.h index 5efb2e1b21..936ad6f588 100644 --- a/arch/x86/include/asm/io.h +++ b/arch/x86/include/asm/io.h @@ -244,6 +244,7 @@ static inline void sync(void) * have some advantages to use them instead of the simple one here. */ #define dmb() __asm__ __volatile__ ("" : : : "memory") +#define mb() __asm__ __volatile__ ("mfence" : : : "memory") #define __iormb() dmb() #define __iowmb() dmb() From patchwork Thu Jun 6 09:22:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philip Oberfichtner X-Patchwork-Id: 1944523 X-Patchwork-Delegate: rfried.dev@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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Thu, 6 Jun 2024 11:22:19 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1717665739; bh=OGLeWlI8LBF3NCWh7g1w04Ja4u3R9eYEwi2EMfXm0Bo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mmogLlhM36WSLWIt3b7sDAYy4cTk71UYBL1WkVnna8eouvHTzCLjb94t7X66NrlbB mLfQ9S1VCmsITk980oM3d7o6djU3lG7Ej0+0tTA4VIlD8QVL4TkY5drIrMuDnHyuTA rO9/pp94MwKlfJi9NRcqq/eVxGutA/Lr5uFy2RzSzoSePhz+MNvkZhCRuAPqn0cXd8 FUUNu2y/5SAsXhK4Hk75yQjo3VO3mHmVE+E09MD0f54dfbB84JFWaB9QnoSyKfVejQ 7jFsei7Ez45wbVy+mybNOcWaDpHFscpIYLMJy37OFMAOzDKqITzTFTyfv4NtBpS6FO h/6INh96ofpgQ== From: Philip Oberfichtner To: u-boot@lists.denx.de Cc: bmeng.cn@gmail.com, caleb.connolly@linaro.org, christophe.roullier@foss.st.com, epsi@gmx.de, eugen.hristev@collabora.com, festevam@gmail.com, forbidden405@outlook.com, ivprusov@salutedevices.com, joe.hershberger@ni.com, jonas@kwiboo.se, kever.yang@rock-chips.com, leyfoon.tan@starfivetech.com, marek.vasut+renesas@mailbox.org, marjolaine.amate@odyssee-systemes.fr, neil.armstrong@linaro.org, n-francis@ti.com, patrice.chotard@foss.st.com, patrick.delaunay@foss.st.com, philipp.tomsich@vrull.eu, rfried.dev@gmail.com, seanga2@gmail.com, sebastian.reichel@collabora.com, sebastien.szymanski@armadeus.com, sjg@chromium.org, sumit.garg@linaro.org, trini@konsulko.com, xypron.glpk@gmx.de, Philip Oberfichtner Subject: [PATCH v2 2/5] net: dwc_eth_qos: Fix header to be self-contained Date: Thu, 6 Jun 2024 11:22:04 +0200 Message-Id: <20240606092207.87816-3-pro@denx.de> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240606092207.87816-1-pro@denx.de> References: <20240606092207.87816-1-pro@denx.de> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Before this commit, usage of this header relied on a specific include order. Fix it by including all dependencies. Signed-off-by: Philip Oberfichtner --- drivers/net/dwc_eth_qos.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h index a06390a698..c7d3e23ab7 100644 --- a/drivers/net/dwc_eth_qos.h +++ b/drivers/net/dwc_eth_qos.h @@ -3,8 +3,11 @@ * Copyright 2022 NXP */ -#include +#include +#include #include +#include +#include /* Core registers */ From patchwork Thu Jun 6 09:22:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philip Oberfichtner X-Patchwork-Id: 1944524 X-Patchwork-Delegate: rfried.dev@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=denx.de header.i=@denx.de header.a=rsa-sha256 header.s=phobos-20191101 header.b=jtAT9Ywl; dkim=pass (2048-bit key) header.d=denx.de header.i=@denx.de header.a=rsa-sha256 header.s=phobos-20191101 header.b=OD7mm7Rc; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4VvzQ50SMDz20PW for ; Thu, 6 Jun 2024 19:22:52 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 135608842E; Thu, 6 Jun 2024 11:22:22 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1717665742; bh=cCI0yTAqLDshRlf5EZAuZM67j173qGyCFS9nOLhkP8s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=jtAT9Ywl6lOMx1Lm0GziJdD6jlKjz0Pl6BIz1NOKBMcX18P+8TUNFefM/lhbwjeRE 64R2wwVuN6YTYYgT8scelrKtiHsNlXeyPGXJMIl2KF7NV2LJ+fbG/xPSQMbRbQJuXZ KH8k1CGhGSymxF6KKlUr+zt5kA244L1KgPTyKVlfNOIYifG89kjvKde3jf+Hn1VOwN igs2sevB11a/1O6JNHoTZ1OIRzHqMR3ocsvP7cvNp4Zbi0PrRvBQYbnQyL+KzH7lcp 25uy/KWgDi342ksuwdw3qeC+MqOEV0gMyAkxcwOS1zEd9YHRiF1tttdyVdxJkl767p BPf1o8utDTYrA== Received: from localhost (unknown [IPv6:2001:861:52:5f60:ff6c:4545:dfcf:4c97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: pro@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id 9784F8840E; Thu, 6 Jun 2024 11:22:20 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1717665740; bh=cCI0yTAqLDshRlf5EZAuZM67j173qGyCFS9nOLhkP8s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OD7mm7Rc4Fnddo0tL8zePh1Z/lmW/aOOKrD044ha5IfcZ05dCNBbT9Qc7/sG5Q9pX 6si63U3qOYZ0nAZq5rljLV3hpsYyTBACYRGjJeCdn4W8vQV2KYjNiygkmYV2ZE6kmn OLOhweH1JCeFh5sCb+QbMPb+kX7Wfyhbhk8facrZGkZ0oLALnFk6NwQMLrg4HGbAxV b1j+251IsJHvlod3A+laZtiAnfNtPeSN+YTdDMD6YNZ+kNmDbgo6Wp4Nk1w/Nk9X52 u19HYSK4ufsFAtzjrJ6yxF5TQdXD6Alf53Q+1U4o0f5Qr0RAPNcuD7zGr0honuOgqb P+bc5lPhteWug== From: Philip Oberfichtner To: u-boot@lists.denx.de Cc: bmeng.cn@gmail.com, caleb.connolly@linaro.org, christophe.roullier@foss.st.com, epsi@gmx.de, eugen.hristev@collabora.com, festevam@gmail.com, forbidden405@outlook.com, ivprusov@salutedevices.com, joe.hershberger@ni.com, jonas@kwiboo.se, kever.yang@rock-chips.com, leyfoon.tan@starfivetech.com, marek.vasut+renesas@mailbox.org, marjolaine.amate@odyssee-systemes.fr, neil.armstrong@linaro.org, n-francis@ti.com, patrice.chotard@foss.st.com, patrick.delaunay@foss.st.com, philipp.tomsich@vrull.eu, rfried.dev@gmail.com, seanga2@gmail.com, sebastian.reichel@collabora.com, sebastien.szymanski@armadeus.com, sjg@chromium.org, sumit.garg@linaro.org, trini@konsulko.com, xypron.glpk@gmx.de, Philip Oberfichtner Subject: [PATCH v2 3/5] net: dwc_eth_qos: Adapt probe() for PCI devices Date: Thu, 6 Jun 2024 11:22:05 +0200 Message-Id: <20240606092207.87816-4-pro@denx.de> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240606092207.87816-1-pro@denx.de> References: <20240606092207.87816-1-pro@denx.de> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean PCI devices do not necessarily use a device tree. In that case, the driver currently fails to find eqos->config and eqos->regs. This commit factors out the respective functionality. Device tree usage remains default, but board specific implementations will be possible as well. Signed-off-by: Philip Oberfichtner --- drivers/net/dwc_eth_qos.c | 28 +++++++++++++++++++++++++--- drivers/net/dwc_eth_qos.h | 3 +++ drivers/net/dwc_eth_qos_imx.c | 1 + drivers/net/dwc_eth_qos_qcom.c | 1 + drivers/net/dwc_eth_qos_rockchip.c | 1 + drivers/net/dwc_eth_qos_starfive.c | 1 + drivers/net/dwc_eth_qos_stm32.c | 1 + 7 files changed, 33 insertions(+), 3 deletions(-) diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index b87634f1f5..34e29301cc 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -1376,6 +1376,21 @@ static int eqos_remove_resources_tegra186(struct udevice *dev) return 0; } +/* + * Get driver data based on the device tree. Boards not using a device tree can + * overwrite this function. + */ +__weak void *eqos_get_driver_data(struct udevice *dev) +{ + return (void *)dev_get_driver_data(dev); +} + +/* Function to get base address, useable for all boards having a device tree. */ +fdt_addr_t eqos_get_base_addr_dt(struct udevice *dev) +{ + return dev_read_addr(dev); +} + static int eqos_probe(struct udevice *dev) { struct eqos_priv *eqos = dev_get_priv(dev); @@ -1384,13 +1399,19 @@ static int eqos_probe(struct udevice *dev) debug("%s(dev=%p):\n", __func__, dev); eqos->dev = dev; - eqos->config = (void *)dev_get_driver_data(dev); - eqos->regs = dev_read_addr(dev); + eqos->config = eqos_get_driver_data(dev); + if (!eqos->config) { + pr_err("Failed to get driver data.\n"); + return -ENODEV; + } + + eqos->regs = eqos->config->ops->eqos_get_base_addr(dev); if (eqos->regs == FDT_ADDR_T_NONE) { - pr_err("dev_read_addr() failed\n"); + pr_err("Failed to get device address.\n"); return -ENODEV; } + eqos->mac_regs = (void *)(eqos->regs + EQOS_MAC_REGS_BASE); eqos->mtl_regs = (void *)(eqos->regs + EQOS_MTL_REGS_BASE); eqos->dma_regs = (void *)(eqos->regs + EQOS_DMA_REGS_BASE); @@ -1497,6 +1518,7 @@ static struct eqos_ops eqos_tegra186_ops = { .eqos_flush_buffer = eqos_flush_buffer_tegra186, .eqos_probe_resources = eqos_probe_resources_tegra186, .eqos_remove_resources = eqos_remove_resources_tegra186, + .eqos_get_base_addr = eqos_get_base_addr_dt, .eqos_stop_resets = eqos_stop_resets_tegra186, .eqos_start_resets = eqos_start_resets_tegra186, .eqos_stop_clks = eqos_stop_clks_tegra186, diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h index c7d3e23ab7..829eb0a565 100644 --- a/drivers/net/dwc_eth_qos.h +++ b/drivers/net/dwc_eth_qos.h @@ -239,6 +239,7 @@ struct eqos_ops { void (*eqos_flush_buffer)(void *buf, size_t size); int (*eqos_probe_resources)(struct udevice *dev); int (*eqos_remove_resources)(struct udevice *dev); + fdt_addr_t (*eqos_get_base_addr)(struct udevice *dev); int (*eqos_stop_resets)(struct udevice *dev); int (*eqos_start_resets)(struct udevice *dev); int (*eqos_stop_clks)(struct udevice *dev); @@ -290,6 +291,8 @@ void eqos_flush_desc_generic(void *desc); void eqos_inval_buffer_generic(void *buf, size_t size); void eqos_flush_buffer_generic(void *buf, size_t size); int eqos_null_ops(struct udevice *dev); +void *eqos_get_driver_data(struct udevice *dev); +fdt_addr_t eqos_get_base_addr_dt(struct udevice *dev); extern struct eqos_config eqos_imx_config; extern struct eqos_config eqos_rockchip_config; diff --git a/drivers/net/dwc_eth_qos_imx.c b/drivers/net/dwc_eth_qos_imx.c index 9c4e390441..21dbf45a22 100644 --- a/drivers/net/dwc_eth_qos_imx.c +++ b/drivers/net/dwc_eth_qos_imx.c @@ -218,6 +218,7 @@ static struct eqos_ops eqos_imx_ops = { .eqos_flush_buffer = eqos_flush_buffer_generic, .eqos_probe_resources = eqos_probe_resources_imx, .eqos_remove_resources = eqos_remove_resources_imx, + .eqos_get_base_addr = eqos_get_base_addr_dt, .eqos_stop_resets = eqos_null_ops, .eqos_start_resets = eqos_null_ops, .eqos_stop_clks = eqos_stop_clks_imx, diff --git a/drivers/net/dwc_eth_qos_qcom.c b/drivers/net/dwc_eth_qos_qcom.c index 8178138fc6..78213e5ca0 100644 --- a/drivers/net/dwc_eth_qos_qcom.c +++ b/drivers/net/dwc_eth_qos_qcom.c @@ -589,6 +589,7 @@ static struct eqos_ops eqos_qcom_ops = { .eqos_flush_buffer = eqos_flush_buffer_generic, .eqos_probe_resources = eqos_probe_resources_qcom, .eqos_remove_resources = eqos_remove_resources_qcom, + .eqos_get_base_addr = eqos_get_base_addr_dt, .eqos_stop_resets = eqos_null_ops, .eqos_start_resets = eqos_start_resets_qcom, .eqos_stop_clks = eqos_stop_clks_qcom, diff --git a/drivers/net/dwc_eth_qos_rockchip.c b/drivers/net/dwc_eth_qos_rockchip.c index fa9e513fae..2c67753ec9 100644 --- a/drivers/net/dwc_eth_qos_rockchip.c +++ b/drivers/net/dwc_eth_qos_rockchip.c @@ -504,6 +504,7 @@ static struct eqos_ops eqos_rockchip_ops = { .eqos_flush_buffer = eqos_flush_buffer_generic, .eqos_probe_resources = eqos_probe_resources_rk, .eqos_remove_resources = eqos_remove_resources_rk, + .eqos_get_base_addr = eqos_get_base_addr_dt, .eqos_stop_resets = eqos_stop_resets_rk, .eqos_start_resets = eqos_start_resets_rk, .eqos_stop_clks = eqos_stop_clks_rk, diff --git a/drivers/net/dwc_eth_qos_starfive.c b/drivers/net/dwc_eth_qos_starfive.c index 5be8ac0f1a..341fd2b946 100644 --- a/drivers/net/dwc_eth_qos_starfive.c +++ b/drivers/net/dwc_eth_qos_starfive.c @@ -219,6 +219,7 @@ static struct eqos_ops eqos_jh7110_ops = { .eqos_flush_buffer = eqos_flush_buffer_generic, .eqos_probe_resources = eqos_probe_resources_jh7110, .eqos_remove_resources = eqos_remove_resources_jh7110, + .eqos_get_base_addr = eqos_get_base_addr_dt, .eqos_stop_resets = eqos_stop_resets_jh7110, .eqos_start_resets = eqos_start_resets_jh7110, .eqos_stop_clks = eqos_stop_clks_jh7110, diff --git a/drivers/net/dwc_eth_qos_stm32.c b/drivers/net/dwc_eth_qos_stm32.c index fbc08bba1d..2c18896b59 100644 --- a/drivers/net/dwc_eth_qos_stm32.c +++ b/drivers/net/dwc_eth_qos_stm32.c @@ -291,6 +291,7 @@ static struct eqos_ops eqos_stm32_ops = { .eqos_flush_buffer = eqos_flush_buffer_generic, .eqos_probe_resources = eqos_probe_resources_stm32, .eqos_remove_resources = eqos_remove_resources_stm32, + .eqos_get_base_addr = eqos_get_base_addr_dt, .eqos_stop_resets = eqos_null_ops, .eqos_start_resets = eqos_null_ops, .eqos_stop_clks = eqos_stop_clks_stm32, From patchwork Thu Jun 6 09:22:06 2024 Content-Type: text/plain; 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Thu, 6 Jun 2024 11:22:21 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1717665741; bh=ar2QF8MTc+S41k3/9ueKTay82HTTrcYyOGQlg9RPf14=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=P7E8Gbh5hY38tK4r4pOkzYBFwftfFeys9xafz0PGwugzrcXkCs5cQ22AQAt7xsNSH kf7YQNQH7xnCu8zzmGcUUULSdZsKV4v2B71DhXKyo2vNRISvNv0k+RKNmvwPasTZSO bC/eImy1yXzDqpwdyTQFYUOnxeocnjE/vf9LocidjhiAq7oXkSURDTOLV34zvCLOcq H65nBET6eMzFDM8WtMFVEnLDMaHOCEaaNyPtVf2+vx8KI+jOEvoCtysGYFjjZaThYY VaBpJ8vsGwvkrbhIyUX9K1PPo1F9n8V3F430kfhL9gMYvFpxNMhxtT3/ippdt89XiK m7Kfm2uvobANg== From: Philip Oberfichtner To: u-boot@lists.denx.de Cc: bmeng.cn@gmail.com, caleb.connolly@linaro.org, christophe.roullier@foss.st.com, epsi@gmx.de, eugen.hristev@collabora.com, festevam@gmail.com, forbidden405@outlook.com, ivprusov@salutedevices.com, joe.hershberger@ni.com, jonas@kwiboo.se, kever.yang@rock-chips.com, leyfoon.tan@starfivetech.com, marek.vasut+renesas@mailbox.org, marjolaine.amate@odyssee-systemes.fr, neil.armstrong@linaro.org, n-francis@ti.com, patrice.chotard@foss.st.com, patrick.delaunay@foss.st.com, philipp.tomsich@vrull.eu, rfried.dev@gmail.com, seanga2@gmail.com, sebastian.reichel@collabora.com, sebastien.szymanski@armadeus.com, sjg@chromium.org, sumit.garg@linaro.org, trini@konsulko.com, xypron.glpk@gmx.de, Philip Oberfichtner Subject: [PATCH v2 4/5] net: dwc_eth_qos: Implement bind() for PCI devices Date: Thu, 6 Jun 2024 11:22:06 +0200 Message-Id: <20240606092207.87816-5-pro@denx.de> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240606092207.87816-1-pro@denx.de> References: <20240606092207.87816-1-pro@denx.de> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean PCI devices do not necessarily use a device tree. Implement a bind() function to assign unique device names in that case. Signed-off-by: Philip Oberfichtner --- drivers/net/dwc_eth_qos.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index 34e29301cc..2eeaccc800 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -1376,6 +1376,21 @@ static int eqos_remove_resources_tegra186(struct udevice *dev) return 0; } +static int eqos_bind(struct udevice *dev) +{ + static int dev_num; + const size_t name_sz = 16; + char name[name_sz]; + + /* Device name defaults to DT node name. */ + if (ofnode_valid(dev_ofnode(dev))) + return 0; + + /* Assign unique names in case there is no DT node. */ + snprintf(name, name_sz, "eth_eqos#%d", dev_num++); + return device_set_name(dev, name); +} + /* * Get driver data based on the device tree. Boards not using a device tree can * overwrite this function. @@ -1597,6 +1612,7 @@ U_BOOT_DRIVER(eth_eqos) = { .name = "eth_eqos", .id = UCLASS_ETH, .of_match = of_match_ptr(eqos_ids), + .bind = eqos_bind, .probe = eqos_probe, .remove = eqos_remove, .ops = &eqos_ops, From patchwork Thu Jun 6 09:22:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philip Oberfichtner X-Patchwork-Id: 1944526 X-Patchwork-Delegate: rfried.dev@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=denx.de header.i=@denx.de header.a=rsa-sha256 header.s=phobos-20191101 header.b=ikyq5Hb0; dkim=pass (2048-bit key) header.d=denx.de header.i=@denx.de header.a=rsa-sha256 header.s=phobos-20191101 header.b=bCEnLyUM; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4VvzQT3yB3z20Q8 for ; Thu, 6 Jun 2024 19:23:13 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id CE84388485; Thu, 6 Jun 2024 11:22:24 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1717665744; bh=BqYPYsplDlqYMULLNDLqrOP76U1GOq6amOo71IHpjQw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=ikyq5Hb04H0uqN3Yu5HCZVlIAjG4NnBSNFOtES7R1LQfwoWEVwyLZeGOxBVSf7VYR 8yAEal/EjSvn0DvNLh7zEmBYRX51cBplMallvOnzYWLS5wzh+L+SSt19/HjyhB483Y A/HABEbPpnnJVnZZb/qs+iD+L2u7WfBuLwM4xzj2oMfqEsWTb1wHMpk4cEDr1AHRkE TuM1r+jVpONuVykaNBLPoJQZtGrnN8lLtrqiQev3Lq9anrSMEVIhxY0g2DaYYsexeb rC201R5orwan1JjAhewdFWGGfIXgKLhrETpD0BM3YERkAPqQjqaiL0Otl/RpHntOxi vj7zWQawgTAGQ== Received: from localhost (unknown [IPv6:2001:861:52:5f60:ff6c:4545:dfcf:4c97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: pro@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id AE35C883CF; Thu, 6 Jun 2024 11:22:22 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1717665742; bh=BqYPYsplDlqYMULLNDLqrOP76U1GOq6amOo71IHpjQw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bCEnLyUMBQ7LoEwHmKVB1t8B2yTgtY9l9wR+2/8g6qmi3dXlHoivlwgoamYPYHZM5 7AXstUUFq8CRC2tUCz3eRz3eBhxZNC1kDEWiIEVa18SR8E6OLWILUnMn9pDPi/PD7S wBNr/KjIJu9KF35jbdxt/K0igAE9xT06PbahXdyO+IkTF5AkjQ57ryOVWDT9hCRnou T6FMiBLbLtQZSPVyv3wjAK32OGAN5pZmgYViIuS+Zaed8WUd/o+1KY8QcczJrb5acR XsWXwSxGAKy21FgObj9/MVmIVZ1fOmKIv50kVd1nqZixP7+liZA7UJ/XjMTxxFH6pl jrBCtabzPG01Q== From: Philip Oberfichtner To: u-boot@lists.denx.de Cc: bmeng.cn@gmail.com, caleb.connolly@linaro.org, christophe.roullier@foss.st.com, epsi@gmx.de, eugen.hristev@collabora.com, festevam@gmail.com, forbidden405@outlook.com, ivprusov@salutedevices.com, joe.hershberger@ni.com, jonas@kwiboo.se, kever.yang@rock-chips.com, leyfoon.tan@starfivetech.com, marek.vasut+renesas@mailbox.org, marjolaine.amate@odyssee-systemes.fr, neil.armstrong@linaro.org, n-francis@ti.com, patrice.chotard@foss.st.com, patrick.delaunay@foss.st.com, philipp.tomsich@vrull.eu, rfried.dev@gmail.com, seanga2@gmail.com, sebastian.reichel@collabora.com, sebastien.szymanski@armadeus.com, sjg@chromium.org, sumit.garg@linaro.org, trini@konsulko.com, xypron.glpk@gmx.de, Philip Oberfichtner Subject: [PATCH v2 5/5] net: dwc_eth_qos: Add glue driver for Intel MAC Date: Thu, 6 Jun 2024 11:22:07 +0200 Message-Id: <20240606092207.87816-6-pro@denx.de> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240606092207.87816-1-pro@denx.de> References: <20240606092207.87816-1-pro@denx.de> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Add dwc_eth_qos glue driver for the Intel Elkhart-Lake SOC. Signed-off-by: Philip Oberfichtner --- Notes: Changes in V2: - Remove 'struct eqos_intel_config' from dwc_eth_qos.h - Improve some comments - Remove duplicate MAC reset drivers/net/Kconfig | 7 + drivers/net/Makefile | 1 + drivers/net/dwc_eth_qos_intel.c | 446 ++++++++++++++++++++++++++++++++ drivers/net/dwc_eth_qos_intel.h | 58 +++++ include/pci_ids.h | 9 + 5 files changed, 521 insertions(+) create mode 100644 drivers/net/dwc_eth_qos_intel.c create mode 100644 drivers/net/dwc_eth_qos_intel.h diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index b2d7b49976..b23fe55792 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -225,6 +225,13 @@ config DWC_ETH_QOS_IMX The Synopsys Designware Ethernet QOS IP block with the specific configuration used in IMX soc. +config DWC_ETH_QOS_INTEL + bool "Synopsys DWC Ethernet QOS device support for Intel" + depends on DWC_ETH_QOS + help + The Synopsys Designware Ethernet QOS IP block with the specific + configuration used in the Intel Elkhart-Lake soc. + config DWC_ETH_QOS_ROCKCHIP bool "Synopsys DWC Ethernet QOS device support for Rockchip SoCs" depends on DWC_ETH_QOS diff --git a/drivers/net/Makefile b/drivers/net/Makefile index dc3404519d..bd62c65dd5 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_DRIVER_DM9000) += dm9000x.o obj-$(CONFIG_DSA_SANDBOX) += dsa_sandbox.o obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o obj-$(CONFIG_DWC_ETH_QOS_IMX) += dwc_eth_qos_imx.o +obj-$(CONFIG_DWC_ETH_QOS_INTEL) += dwc_eth_qos_intel.o obj-$(CONFIG_DWC_ETH_QOS_ROCKCHIP) += dwc_eth_qos_rockchip.o obj-$(CONFIG_DWC_ETH_QOS_QCOM) += dwc_eth_qos_qcom.o obj-$(CONFIG_DWC_ETH_QOS_STARFIVE) += dwc_eth_qos_starfive.o diff --git a/drivers/net/dwc_eth_qos_intel.c b/drivers/net/dwc_eth_qos_intel.c new file mode 100644 index 0000000000..15680187cc --- /dev/null +++ b/drivers/net/dwc_eth_qos_intel.c @@ -0,0 +1,446 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 DENX Software Engineering GmbH + * Philip Oberfichtner + * + * Based on linux v6.1.38, especially drivers/net/ethernet/stmicro/stmmac + */ + +#include +#include +#include +#include +#include +#include + +#include "dwc_eth_qos.h" +#include "dwc_eth_qos_intel.h" + +static struct pci_device_id intel_pci_ids[] = { + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EHL_RGMII1G) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EHL_SGMII1) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EHL_SGMII2G5) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EHL_PSE0_RGMII1G) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII1G) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII2G5) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EHL_PSE1_RGMII1G) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII1G) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII2G5) }, + {} +}; + +static int __pci_config(struct udevice *dev) +{ + u32 val; + + /* Try to enable I/O accesses and bus-mastering */ + dm_pci_read_config32(dev, PCI_COMMAND, &val); + val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; + dm_pci_write_config32(dev, PCI_COMMAND, val); + + /* Make sure it worked */ + dm_pci_read_config32(dev, PCI_COMMAND, &val); + if (!(val & PCI_COMMAND_MEMORY)) { + pr_err("%s: Can't enable I/O memory\n", __func__); + return -ENOSPC; + } + + if (!(val & PCI_COMMAND_MASTER)) { + pr_err("%s: Can't enable bus-mastering\n", __func__); + return -EPERM; + } + + return 0; +} + +static void __limit_fifo_size(struct udevice *dev) +{ + /* + * As described in Intel Erratum EHL22, Document Number: 636674-2.1, + * the PSE GbE Controllers advertise a wrong RX and TX fifo size. + * Software should limit this value to 64KB. + */ + struct eqos_priv *eqos = dev_get_priv(dev); + + eqos->tx_fifo_sz = 0x8000; + eqos->rx_fifo_sz = 0x8000; +} + +static int __serdes_status_poll(struct udevice *dev, + unsigned char phyaddr, unsigned char phyreg, + unsigned short mask, unsigned short val) +{ + struct eqos_priv *eqos = dev_get_priv(dev); + unsigned int retries = 10; + unsigned short val_rd; + + do { + miiphy_read(eqos->mii->name, phyaddr, phyreg, &val_rd); + if ((val_rd & mask) == (val & mask)) + return 0; + udelay(POLL_DELAY_US); + } while (--retries); + + return -ETIMEDOUT; +} + + /* Returns -ve if MAC is unknown and 0 on success */ +static int __mac_check_pse(const struct udevice *dev, bool *is_pse) +{ + struct pci_child_plat *plat = dev_get_parent_plat(dev); + + if (!plat || plat->vendor != PCI_VENDOR_ID_INTEL) + return -ENXIO; + + switch (plat->device) { + case PCI_DEVICE_ID_INTEL_EHL_PSE0_RGMII1G: + case PCI_DEVICE_ID_INTEL_EHL_PSE1_RGMII1G: + case PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII1G: + case PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII1G: + case PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII2G5: + case PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII2G5: + *is_pse = 1; + return 0; + + case PCI_DEVICE_ID_INTEL_EHL_RGMII1G: + case PCI_DEVICE_ID_INTEL_EHL_SGMII1: + case PCI_DEVICE_ID_INTEL_EHL_SGMII2G5: + *is_pse = 0; + return 0; + }; + + return -ENXIO; +} + +/* Check if we're in 2G5 mode */ +static bool __serdes_link_mode_2500(struct udevice *dev) +{ + const unsigned char phyad = INTEL_MGBE_ADHOC_ADDR; + struct eqos_priv *eqos = dev_get_priv(dev); + unsigned short data; + + miiphy_read(eqos->mii->name, phyad, SERDES_GCR, &data); + if (((data & SERDES_LINK_MODE_MASK) >> SERDES_LINK_MODE_SHIFT) == + SERDES_LINK_MODE_2G5) + return true; + + return false; +} + +static int __serdes_powerup(struct udevice *dev) +{ + /* Based on linux/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c */ + + const unsigned char phyad = INTEL_MGBE_ADHOC_ADDR; + struct eqos_priv *eqos = dev_get_priv(dev); + unsigned short data; + int ret; + bool is_pse; + + /* Set the serdes rate and the PCLK rate */ + miiphy_read(eqos->mii->name, phyad, SERDES_GCR0, &data); + + data &= ~SERDES_RATE_MASK; + data &= ~SERDES_PCLK_MASK; + + if (__serdes_link_mode_2500(dev)) + data |= SERDES_RATE_PCIE_GEN2 << SERDES_RATE_PCIE_SHIFT | + SERDES_PCLK_37p5MHZ << SERDES_PCLK_SHIFT; + else + data |= SERDES_RATE_PCIE_GEN1 << SERDES_RATE_PCIE_SHIFT | + SERDES_PCLK_70MHZ << SERDES_PCLK_SHIFT; + + miiphy_write(eqos->mii->name, phyad, SERDES_GCR0, data); + + /* assert clk_req */ + miiphy_read(eqos->mii->name, phyad, SERDES_GCR0, &data); + data |= SERDES_PLL_CLK; + miiphy_write(eqos->mii->name, phyad, SERDES_GCR0, data); + + /* check for clk_ack assertion */ + ret = __serdes_status_poll(dev, phyad, SERDES_GSR0, + SERDES_PLL_CLK, SERDES_PLL_CLK); + + if (ret) { + pr_err("Serdes PLL clk request timeout\n"); + return ret; + } + + /* assert lane reset*/ + miiphy_read(eqos->mii->name, phyad, SERDES_GCR0, &data); + data |= SERDES_RST; + miiphy_write(eqos->mii->name, phyad, SERDES_GCR0, data); + + /* check for assert lane reset reflection */ + ret = __serdes_status_poll(dev, phyad, SERDES_GSR0, + SERDES_RST, SERDES_RST); + + if (ret) { + pr_err("Serdes assert lane reset timeout\n"); + return ret; + } + + /* move power state to P0 */ + miiphy_read(eqos->mii->name, phyad, SERDES_GCR0, &data); + data &= ~SERDES_PWR_ST_MASK; + data |= SERDES_PWR_ST_P0 << SERDES_PWR_ST_SHIFT; + miiphy_write(eqos->mii->name, phyad, SERDES_GCR0, data); + + /* Check for P0 state */ + ret = __serdes_status_poll(dev, phyad, SERDES_GSR0, + SERDES_PWR_ST_MASK, + SERDES_PWR_ST_P0 << SERDES_PWR_ST_SHIFT); + + if (ret) { + pr_err("Serdes power state P0 timeout.\n"); + return ret; + } + + /* PSE only - ungate SGMII PHY Rx Clock*/ + ret = __mac_check_pse(dev, &is_pse); + if (ret) { + pr_err("Failed to determine MAC type.\n"); + return ret; + } + + if (is_pse) { + miiphy_read(eqos->mii->name, phyad, SERDES_GCR0, &data); + data |= SERDES_PHY_RX_CLK; + miiphy_write(eqos->mii->name, phyad, SERDES_GCR0, data); + } + + return 0; +} + +static int __xpcs_access(struct udevice *dev, int reg, int v) +{ + /* + * Common read/write helper function + * + * It may seem a bit odd at a first glance that we use bus->read() + * directly insetad of one of the wrapper functions. But: + * + * (1) phy_read() can't be used because we do not access an acutal PHY, + * but a MAC-internal submodule. + * + * (2) miiphy_read() can't be used because it assumes MDIO_DEVAD_NONE. + */ + + int port = INTEL_MGBE_XPCS_ADDR; + int devad = 0x1f; + u16 val; + struct eqos_priv *eqos; + struct mii_dev *bus; + + eqos = dev_get_priv(dev); + bus = eqos->mii; + + if (v < 0) + return bus->read(bus, port, devad, reg); + + val = v; + return bus->write(bus, port, devad, reg, val); +} + +static int __xpcs_read(struct udevice *dev, int reg) +{ + return __xpcs_access(dev, reg, -1); +} + +static int __xpcs_write(struct udevice *dev, int reg, u16 val) +{ + return __xpcs_access(dev, reg, val); +} + +static int __xpcs_clr_bits(struct udevice *dev, int reg, u16 bits) +{ + int ret; + + ret = __xpcs_read(dev, reg); + if (ret < 0) + return ret; + + ret &= ~bits; + + return __xpcs_write(dev, reg, ret); +} + +static int __xpcs_set_bits(struct udevice *dev, int reg, u16 bits) +{ + int ret; + + ret = __xpcs_read(dev, reg); + if (ret < 0) + return ret; + + ret |= bits; + + return __xpcs_write(dev, reg, ret); +} + +static int __xpcs_init(struct udevice *dev) +{ + /* Based on linux/drivers/net/pcs/pcs-xpcs.c */ + struct eqos_priv *eqos = dev_get_priv(dev); + phy_interface_t interface = eqos->config->interface(dev); + + if (interface != PHY_INTERFACE_MODE_SGMII) + return 0; + + if (__xpcs_clr_bits(dev, VR_MII_MMD_CTRL, XPCS_AN_CL37_EN) || + __xpcs_set_bits(dev, VR_MII_AN_CTRL, XPCS_MODE_SGMII) || + __xpcs_set_bits(dev, VR_MII_DIG_CTRL1, XPCS_MAC_AUTO_SW) || + __xpcs_set_bits(dev, VR_MII_MMD_CTRL, XPCS_AN_CL37_EN)) + return -EIO; + + return 0; +} + +static int eqos_probe_ressources_intel(struct udevice *dev) +{ + __limit_fifo_size(dev); + + return __pci_config(dev); +} + +struct eqos_config eqos_intel_config; + +/* + * overwrite __weak function from eqos_intel.c + * + * For PCI devices the devcie tree is optional. Choose driver data based on PCI + * IDs instead. + */ +void *eqos_get_driver_data(struct udevice *dev) +{ + const struct pci_device_id *id; + const struct pci_child_plat *plat; + + plat = dev_get_parent_plat(dev); + + if (!plat) + return NULL; + + /* last intel_pci_ids element is zero initialized */ + for (id = intel_pci_ids; id->vendor != 0; id++) { + if (id->vendor == plat->vendor && id->device == plat->device) + return &eqos_intel_config; + } + + return NULL; +} + +static fdt_addr_t eqos_get_base_addr_intel(struct udevice *dev) +{ + void *ptr = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, + PCI_REGION_TYPE, PCI_REGION_MEM); + + if (!ptr) + return FDT_ADDR_T_NONE; + + return (fdt_addr_t)ptr; +} + +static int eqos_start_resets_intel(struct udevice *dev) +{ + int ret; + + ret = __xpcs_init(dev); + if (ret) { + pr_err("xpcs init failed.\n"); + return ret; + } + + ret = __serdes_powerup(dev); + if (ret) { + pr_err("Failed to power up serdes.\n"); + return ret; + } + + return 0; +} + +static ulong eqos_get_tick_clk_rate_intel(struct udevice *dev) +{ + return 0; +} + +static int eqos_get_enetaddr_intel(struct udevice *dev) +{ + /* Assume MAC address is programmed by previous boot stage */ + struct eth_pdata *plat = dev_get_plat(dev); + struct eqos_priv *eqos = dev_get_priv(dev); + u8 *lo = (u8 *)&eqos->mac_regs->address0_low; + u8 *hi = (u8 *)&eqos->mac_regs->address0_high; + + plat->enetaddr[0] = lo[0]; + plat->enetaddr[1] = lo[1]; + plat->enetaddr[2] = lo[2]; + plat->enetaddr[3] = lo[3]; + plat->enetaddr[4] = hi[0]; + plat->enetaddr[5] = hi[1]; + + return 0; +} + +static phy_interface_t eqos_get_interface_intel(const struct udevice *dev) +{ + struct pci_child_plat *plat = dev_get_parent_plat(dev); + + if (!plat || plat->vendor != PCI_VENDOR_ID_INTEL) + return PHY_INTERFACE_MODE_NA; + + switch (plat->device) { + /* The GbE Host Controller has no RGMII interface */ + case PCI_DEVICE_ID_INTEL_EHL_RGMII1G: + return PHY_INTERFACE_MODE_NA; + + case PCI_DEVICE_ID_INTEL_EHL_PSE0_RGMII1G: + case PCI_DEVICE_ID_INTEL_EHL_PSE1_RGMII1G: + return PHY_INTERFACE_MODE_RGMII; + + /* Host SGMII and Host SGMII2G5 share the same device id */ + case PCI_DEVICE_ID_INTEL_EHL_SGMII1: + case PCI_DEVICE_ID_INTEL_EHL_SGMII2G5: + case PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII2G5: + case PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII1G: + case PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII1G: + case PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII2G5: + return PHY_INTERFACE_MODE_SGMII; + }; + + return PHY_INTERFACE_MODE_NA; +} + +static struct eqos_ops eqos_intel_ops = { + .eqos_inval_desc = eqos_inval_desc_generic, + .eqos_flush_desc = eqos_flush_desc_generic, + .eqos_inval_buffer = eqos_inval_buffer_generic, + .eqos_flush_buffer = eqos_flush_buffer_generic, + .eqos_probe_resources = eqos_probe_ressources_intel, + .eqos_remove_resources = eqos_null_ops, + .eqos_get_base_addr = eqos_get_base_addr_intel, + .eqos_stop_resets = eqos_null_ops, + .eqos_start_resets = eqos_start_resets_intel, + .eqos_stop_clks = eqos_null_ops, + .eqos_start_clks = eqos_null_ops, + .eqos_calibrate_pads = eqos_null_ops, + .eqos_disable_calibration = eqos_null_ops, + .eqos_set_tx_clk_speed = eqos_null_ops, + .eqos_get_enetaddr = eqos_get_enetaddr_intel, + .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_intel, +}; + +struct eqos_config eqos_intel_config = { + .reg_access_always_ok = false, + .mdio_wait = 10, + .swr_wait = 50, + .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB, + .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300, + .axi_bus_width = EQOS_AXI_WIDTH_64, + .interface = eqos_get_interface_intel, + .ops = &eqos_intel_ops +}; + +extern U_BOOT_DRIVER(eth_eqos); +U_BOOT_PCI_DEVICE(eth_eqos, intel_pci_ids); diff --git a/drivers/net/dwc_eth_qos_intel.h b/drivers/net/dwc_eth_qos_intel.h new file mode 100644 index 0000000000..a7eede621c --- /dev/null +++ b/drivers/net/dwc_eth_qos_intel.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (c) 2023 DENX Software Engineering GmbH + * Philip Oberfichtner + * + * This header is based on linux v6.1.38, + * + * drivers/net/pcs/pcs-xpcs.h + * drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h, + * + * Copyright (c) 2020 Synopsys, Inc. and/or its affiliates + * Copyright (c) 2020 Intel Corporation + */ + +#ifndef __DWMAC_INTEL_H__ +#define __DWMAC_INTEL_H__ + +#define POLL_DELAY_US 8 + +/* SERDES Register */ +#define SERDES_GCR 0x0 /* Global Conguration */ +#define SERDES_GSR0 0x5 /* Global Status Reg0 */ +#define SERDES_GCR0 0xb /* Global Configuration Reg0 */ + +/* SERDES defines */ +#define SERDES_PLL_CLK BIT(0) /* PLL clk valid signal */ +#define SERDES_PHY_RX_CLK BIT(1) /* PSE SGMII PHY rx clk */ +#define SERDES_RST BIT(2) /* Serdes Reset */ +#define SERDES_PWR_ST_MASK GENMASK(6, 4) /* Serdes Power state*/ +#define SERDES_RATE_MASK GENMASK(9, 8) +#define SERDES_PCLK_MASK GENMASK(14, 12) /* PCLK rate to PHY */ +#define SERDES_LINK_MODE_MASK GENMASK(2, 1) +#define SERDES_LINK_MODE_SHIFT 1 +#define SERDES_PWR_ST_SHIFT 4 +#define SERDES_PWR_ST_P0 0x0 +#define SERDES_PWR_ST_P3 0x3 +#define SERDES_LINK_MODE_2G5 0x3 +#define SERSED_LINK_MODE_1G 0x2 +#define SERDES_PCLK_37p5MHZ 0x0 +#define SERDES_PCLK_70MHZ 0x1 +#define SERDES_RATE_PCIE_GEN1 0x0 +#define SERDES_RATE_PCIE_GEN2 0x1 +#define SERDES_RATE_PCIE_SHIFT 8 +#define SERDES_PCLK_SHIFT 12 + +#define INTEL_MGBE_ADHOC_ADDR 0x15 +#define INTEL_MGBE_XPCS_ADDR 0x16 + +/* XPCS defines */ +#define XPCS_MODE_SGMII BIT(2) +#define XPCS_MAC_AUTO_SW BIT(9) +#define XPCS_AN_CL37_EN BIT(12) + +#define VR_MII_MMD_CTRL 0x0000 +#define VR_MII_DIG_CTRL1 0x8000 +#define VR_MII_AN_CTRL 0x8001 + +#endif /* __DWMAC_INTEL_H__ */ diff --git a/include/pci_ids.h b/include/pci_ids.h index f1886c3a75..14acb77d2d 100644 --- a/include/pci_ids.h +++ b/include/pci_ids.h @@ -2601,6 +2601,15 @@ #define PCI_DEVICE_ID_DCI_PCCOM2 0x0004 #define PCI_VENDOR_ID_INTEL 0x8086 +#define PCI_DEVICE_ID_INTEL_EHL_RGMII1G 0x4b30 +#define PCI_DEVICE_ID_INTEL_EHL_SGMII1 0x4b31 +#define PCI_DEVICE_ID_INTEL_EHL_SGMII2G5 0x4b32 +#define PCI_DEVICE_ID_INTEL_EHL_PSE0_RGMII1G 0x4ba0 +#define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII1G 0x4ba1 +#define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII2G5 0x4ba2 +#define PCI_DEVICE_ID_INTEL_EHL_PSE1_RGMII1G 0x4bb0 +#define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII1G 0x4bb1 +#define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII2G5 0x4bb2 #define PCI_DEVICE_ID_INTEL_EESSC 0x0008 #define PCI_DEVICE_ID_INTEL_SNB_IMC 0x0100 #define PCI_DEVICE_ID_INTEL_IVB_IMC 0x0154