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Fri, 31 May 2024 07:12:28 -0700 (PDT) Received: from noel.flets-west.jp ([2405:6586:4480:a10:167:9818:d778:5c14]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-70242b057besm1418103b3a.162.2024.05.31.07.12.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 May 2024 07:12:28 -0700 (PDT) From: Hironori KIKUCHI To: linux-kernel@vger.kernel.org Cc: Hironori KIKUCHI , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Aleksandr Shubin , Cheo Fusi , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev Subject: [PATCH 3/5] dt-bindings: pwm: sun20i: Add compatible string for Allwinner H616 PWM Date: Fri, 31 May 2024 23:11:35 +0900 Message-ID: <20240531141152.327592-4-kikuchan98@gmail.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240531141152.327592-1-kikuchan98@gmail.com> References: <20240531141152.327592-1-kikuchan98@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Allwinner H616 SoC has a PWM controller similar to the one in the D1, which is supported by the pwm-sun20i driver. The main difference is in the register layout. Specifically, the GATING flag is placed in the PCCR register instead of the individual PCGR register. Add a compatible string to distinguish them. Signed-off-by: Hironori KIKUCHI --- Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml b/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml index 89cebf7841a..b9b6d7e7c87 100644 --- a/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml @@ -17,6 +17,7 @@ properties: - items: - const: allwinner,sun50i-r329-pwm - const: allwinner,sun20i-d1-pwm + - const: allwinner,sun50i-h616-pwm reg: maxItems: 1 From patchwork Fri May 31 14:11:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hironori KIKUCHI X-Patchwork-Id: 1942159 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; 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Signed-off-by: Hironori KIKUCHI --- .../bindings/pwm/allwinner,sun20i-pwm.yaml | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml b/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml index b9b6d7e7c87..436a1d344ab 100644 --- a/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml @@ -45,6 +45,25 @@ properties: description: The number of PWM channels configured for this instance enum: [6, 9] + allwinner,pwm-pair-clock-sources: + description: The clock source names for each PWM pair + items: + enum: [hosc, apb] + minItems: 1 + maxItems: 8 + + allwinner,pwm-pair-clock-prescales: + description: The prescale (DIV_M register) values for each PWM pair + $ref: /schemas/types.yaml#/definitions/uint32-matrix + items: + items: + minimum: 0 + maximum: 8 + minItems: 1 + maxItems: 1 + minItems: 1 + maxItems: 8 + allOf: - $ref: pwm.yaml#