From patchwork Tue May 28 19:15:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabio Estevam X-Patchwork-Id: 1940716 X-Patchwork-Delegate: festevam@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20230601 header.b=UXsTrU//; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Vpj054D4Lz20Q3 for ; Wed, 29 May 2024 05:15:33 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 8B5D788571; Tue, 28 May 2024 21:15:21 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="UXsTrU//"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id B9F7488555; Tue, 28 May 2024 21:15:20 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-pj1-x1036.google.com (mail-pj1-x1036.google.com [IPv6:2607:f8b0:4864:20::1036]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 92A5288555 for ; Tue, 28 May 2024 21:15:18 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=festevam@gmail.com Received: by mail-pj1-x1036.google.com with SMTP id 98e67ed59e1d1-2bf196037a7so232621a91.1 for ; Tue, 28 May 2024 12:15:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1716923717; x=1717528517; darn=lists.denx.de; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=UC7yxqpyjmhSjoo97An3s2I7CS2+n9Ltr90L1w2oRSo=; b=UXsTrU//uWigRdXtLu6eoOPvi3uHq4ufQMIQQ5qI6mP7kd2QUWRHrfNxYz35iPT2DC wQdOldY7Od9A6VNp0NVj65X5g60KUFRTET/RRPAZwuSaZIeVRCbIXrIFgIgfsADFuOHf 796U84eHu01m/10snAwQoI0qfgHeXdcj8bhCPL/ffrs9PSrH6lmYda3m6wflWCd4oS5U IuzzcIyXeecTW2QVGsgazGqI0EKdoeoDPZGQXjYPA7+rJ+p0m3+OeXJ9qP+0nXEIVbD3 PTvv6c82gjazRQv8EylucD6rGrzfCFGkQNqc+w/8bFUoH3Iba5ZOceBW3wHjufvLAywv U4Ww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716923717; x=1717528517; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=UC7yxqpyjmhSjoo97An3s2I7CS2+n9Ltr90L1w2oRSo=; b=BNZoUKCMa//WmjR+ClGHgYX090aoXVyTtdL5F+eMzHQvRNCWnPK3CCvIcd30+D0lCR uawZc/weMIsuwGDnyoE2g2FkFxgtzoc0snVGyCT21712I+Y3cfr/lXQ87jd4vs78shR1 DQEYaORu0iTHdkm8gtn1VCpnU4ViEMQaz8eu++dwuhENpkfMuAFIMVRSMMAYYYeSnDgy jJwp4KIUO0wdnFRz6q3hMLlRK3ZwJcH8St9/bZn/knxJGrxMvfiB/CcPl8Qd5EoVVZRi TxoNSIJ/j2jaR/QuRbgrxQ/wVCVcUMC5CMAdd6qtn0fGyvX/x+7yDdNJDT2AfKk39C24 Xs2Q== X-Gm-Message-State: AOJu0YwS407GNKI5xanwMuy4OICkN/OczdTsWr0Zs2rE4Q4frHrtwcdK +pJu+4u3sgaCnvpjeVnAZTCFuuCSQktGirXl4KZwES4Se1SiOOOY X-Google-Smtp-Source: AGHT+IENcpPkDWGpB65tkHZRnw552zKSc4MgrD5QUASpkPJiFqSAdEsmhjYKudFbfzt97hvX5L7P+Q== X-Received: by 2002:a17:90a:be0b:b0:2af:d64:4887 with SMTP id 98e67ed59e1d1-2bf5f50f7c2mr12233184a91.4.1716923716911; Tue, 28 May 2024 12:15:16 -0700 (PDT) Received: from fabio-Precision-3551.. ([2804:14c:485:4b61:dfd9:2d9b:ff9d:4f57]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2bf92de8b86sm6127952a91.45.2024.05.28.12.15.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 May 2024 12:15:16 -0700 (PDT) From: Fabio Estevam To: paul.liu@linaro.org Cc: u-boot@lists.denx.de, Fabio Estevam Subject: [PATCH 1/2] imx8mm-cl-iot-gate: Add support for Samsung 4GB DDR Date: Tue, 28 May 2024 16:15:09 -0300 Message-Id: <20240528191510.1366328-1-festevam@gmail.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Fabio Estevam Newer versions of the imx8mm-cl-iot-gate boards may come populated with a Samsung 4GB DDR model. Add support for it. Signed-off-by: Fabio Estevam --- board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c b/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c index b230478b611a..f1048a1ab2ab 100644 --- a/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c +++ b/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c @@ -47,7 +47,9 @@ struct lpddr4_desc { static const struct lpddr4_desc lpddr4_array[] = { { .name = "Nanya", .id = 0x05000010, .subind = 0xff, .size = 2048, .count = 1, .timing = &ucm_dram_timing_01061010}, - { .name = "Samsung", .id = 0x01061010, .subind = 0xff, + { .name = "Samsung", .id = 0x01061010, .subind = 0x04, + .size = 4096, .count = 1, .timing = &ucm_dram_timing_ff000110}, + { .name = "Samsung", .id = 0x01061010, .subind = 0x02, .size = 2048, .count = 1, .timing = &ucm_dram_timing_01061010}, { .name = "Kingston", .id = 0xff000010, .subind = 0x04, .size = 4096, .count = 1, .timing = &ucm_dram_timing_ff000110}, From patchwork Tue May 28 19:15:10 2024 Content-Type: text/plain; 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([2804:14c:485:4b61:dfd9:2d9b:ff9d:4f57]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2bf92de8b86sm6127952a91.45.2024.05.28.12.15.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 May 2024 12:15:18 -0700 (PDT) From: Fabio Estevam To: paul.liu@linaro.org Cc: u-boot@lists.denx.de, Fabio Estevam Subject: [PATCH 2/2] imx8mm-cl-iot-gate: Add support for the Realtek RTL8211E PHY Date: Tue, 28 May 2024 16:15:10 -0300 Message-Id: <20240528191510.1366328-2-festevam@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240528191510.1366328-1-festevam@gmail.com> References: <20240528191510.1366328-1-festevam@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Fabio Estevam Newer imx8mm-cl-iot-gate versions are populated with a Realtek RTL8211E PHY instead of the Atheros AR8033. Adapted Compulab's patch from: https://github.com/compulab-yokneam/meta-bsp-imx8mm/blob/iot-gate-imx8_5.10.72/recipes-bsp/u-boot/compulab/imx8mm/0125-imx8mm-net-enable-phy-Realtek-RTL8211E.patch to support both PHYs in U-Boot. Signed-off-by: Fabio Estevam --- .../imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c | 106 +++++++++++++++++- include/configs/imx8mm-cl-iot-gate.h | 2 +- 2 files changed, 104 insertions(+), 4 deletions(-) diff --git a/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c b/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c index af070ec315c4..bf196e062bd0 100644 --- a/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c +++ b/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -31,6 +32,8 @@ DECLARE_GLOBAL_DATA_PTR; +static int fec_phyaddr = -1; + #if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) struct efi_fw_image fw_images[] = { #if defined(CONFIG_TARGET_IMX8MM_CL_IOT_GATE) @@ -110,10 +113,72 @@ static int setup_fec(void) return 0; } +#define FDT_PHYADDR "/soc@0/bus@30800000/ethernet@30be0000/mdio/ethernet-phy@0" +#define FLIP_32B(val) (((val >> 24) & 0xff) | ((val << 8) & 0xff0000) | ((val >> 8) & 0xff00) | ((val << 24) & 0xff000000)) +static int fdt_set_fec_phy_addr(void *blob) +{ + u32 val; + + if (fec_phyaddr < 0) + return -EINVAL; + + val = FLIP_32B(fec_phyaddr); + return fdt_find_and_setprop(blob, FDT_PHYADDR, "reg", (const void *)&val, + sizeof(val), 0); +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + fdt_set_fec_phy_addr(blob); + return 0; +} + +/* + * These are specific ID, purposed to distiguish between PHY vendors. + * These values are not equal to real vendors' OUI (half of MAC address) + */ +#define OUI_PHY_ATHEROS 0x1374 +#define OUI_PHY_REALTEK 0x0732 + int board_phy_config(struct phy_device *phydev) { - if (IS_ENABLED(CONFIG_FEC_MXC)) { + unsigned int model, rev, oui; + int phyid1, phyid2; + unsigned int reg; + + if (!IS_ENABLED(CONFIG_FEC_MXC)) + return 0; + + phyid1 = phy_read(phydev, MDIO_DEVAD_NONE, MII_PHYSID1); + if (phyid1 < 0) { + printf("%s: PHYID1 registry read fail %i\n", __func__, phyid1); + return phyid1; + } + + phyid2 = phy_read(phydev, MDIO_DEVAD_NONE, MII_PHYSID2); + if (phyid2 < 0) { + printf("%s: PHYID2 registry read fail %i\n", __func__, phyid2); + return phyid2; + } + + reg = phyid2 | phyid1 << 16; + if (reg == 0xffff) { + printf("%s: There is no device @%i\n", __func__, phydev->addr); + return -ENODEV; + } + + rev = reg & 0xf; + reg >>= 4; + model = reg & 0x3f; + reg >>= 6; + oui = reg; + debug("%s: PHY @0x%x OUI 0x%06x model 0x%x rev 0x%x\n", + __func__, phydev->addr, oui, model, rev); + + switch (oui) { + case OUI_PHY_ATHEROS: /* enable rgmii rxc skew and phy mode select to RGMII copper */ + printf("phy: AR803x@%x\t", phydev->addr); phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); @@ -121,10 +186,45 @@ int board_phy_config(struct phy_device *phydev) phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee); phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + break; + case OUI_PHY_REALTEK: + printf("phy: RTL8211E@%x\t", phydev->addr); + /* RTL8211E-VB-CG - add TX and RX delay */ + unsigned short val; + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x07); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0xa4); + val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1c); + val |= (0x1 << 13) | (0x1 << 12) | (0x1 << 11); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1c, val); + /* LEDs: set to extension page */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x0007); + /* extension Page44 */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x002c); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1c, 0x0430);//LCR + phy_write(phydev, MDIO_DEVAD_NONE, 0x1a, 0x0010);//LACR + /* + * To disable EEE LED mode (blinking .4s/2s) + * Extension Page5 + */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x0005); + phy_write(phydev, MDIO_DEVAD_NONE, 0x05, 0x8b82);//magic const + phy_write(phydev, MDIO_DEVAD_NONE, 0x06, 0x052b);//magic const + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x00);// Back to Page0 - if (phydev->drv->config) - phydev->drv->config(phydev); + break; + default: + printf("%s: ERROR: unknown PHY @0x%x OUI 0x%06x model 0x%x rev 0x%x\n", + __func__, phydev->addr, oui, model, rev); + return -ENOSYS; } + + fec_phyaddr = phydev->addr; + + if (phydev->drv->config) + phydev->drv->config(phydev); + return 0; } diff --git a/include/configs/imx8mm-cl-iot-gate.h b/include/configs/imx8mm-cl-iot-gate.h index 09d87cf214bf..0c547027ba69 100644 --- a/include/configs/imx8mm-cl-iot-gate.h +++ b/include/configs/imx8mm-cl-iot-gate.h @@ -136,7 +136,7 @@ #define CFG_SYS_FSL_USDHC_NUM 2 #define CFG_SYS_FSL_ESDHC_ADDR 0 -#define CFG_FEC_MXC_PHYADDR 0 +#define CFG_FEC_MXC_PHYADDR -1 /* Auto search of PHY on MII */ /* USB Configs */ #define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)