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Signed-off-by: Teresa Remmet --- board/phytec/phycore_imx8mp/spl.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/phytec/phycore_imx8mp/spl.c b/board/phytec/phycore_imx8mp/spl.c index df158024654e..492ce3b7ca6e 100644 --- a/board/phytec/phycore_imx8mp/spl.c +++ b/board/phytec/phycore_imx8mp/spl.c @@ -25,8 +25,8 @@ DECLARE_GLOBAL_DATA_PTR; -#define EEPROM_ADDR 0x51 -#define EEPROM_ADDR_FALLBACK 0x59 +#define EEPROM_ADDR 0x51 +#define EEPROM_ADDR_FALLBACK 0x59 int spl_board_boot_device(enum boot_device boot_dev_spl) { From patchwork Tue May 28 13:35:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Teresa Remmet X-Patchwork-Id: 1940510 X-Patchwork-Delegate: festevam@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; 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Add support for 1GB 1.5GHz, 1GB 2GHz, 4GB 1.5GHz, 4GB 2GHz and 8GB 2GHz RAM. The RAM size and speed grade is detected by the information stored in the EEPROM on the SoM. Co-developed-by: Benjamin Hahn Signed-off-by: Benjamin Hahn Co-developed-by: Yannic Moog Signed-off-by: Yannic Moog Co-developed-by: Yashwanth Varakala Signed-off-by: Yashwanth Varakala Signed-off-by: Teresa Remmet --- board/phytec/phycore_imx8mp/lpddr4_timing.c | 153 +++++++++++++++++++ board/phytec/phycore_imx8mp/lpddr4_timing.h | 16 ++ board/phytec/phycore_imx8mp/phycore-imx8mp.c | 11 ++ board/phytec/phycore_imx8mp/spl.c | 100 +++++------- include/configs/phycore_imx8mp.h | 4 +- 5 files changed, 224 insertions(+), 60 deletions(-) create mode 100644 board/phytec/phycore_imx8mp/lpddr4_timing.h diff --git a/board/phytec/phycore_imx8mp/lpddr4_timing.c b/board/phytec/phycore_imx8mp/lpddr4_timing.c index f2707b859606..9984b6c26013 100644 --- a/board/phytec/phycore_imx8mp/lpddr4_timing.c +++ b/board/phytec/phycore_imx8mp/lpddr4_timing.c @@ -1839,3 +1839,156 @@ struct dram_timing_info dram_timing = { .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), .fsp_table = { 3000, 400, 100, }, }; + +void set_dram_timings_2ghz_2gb(void) +{ + dram_timing.ddrc_cfg[3].val = 0x1323; + dram_timing.ddrc_cfg[4].val = 0x1e84800; + dram_timing.ddrc_cfg[5].val = 0x7a0118; + dram_timing.ddrc_cfg[8].val = 0xc00307a3; + dram_timing.ddrc_cfg[9].val = 0xc50000; + dram_timing.ddrc_cfg[10].val = 0xf4003f; + dram_timing.ddrc_cfg[11].val = 0xf30000; + dram_timing.ddrc_cfg[14].val = 0x2028222a; + dram_timing.ddrc_cfg[15].val = 0x8083f; + dram_timing.ddrc_cfg[16].val = 0xe0e000; + dram_timing.ddrc_cfg[17].val = 0x12040a12; + dram_timing.ddrc_cfg[18].val = 0x2050f0f; + dram_timing.ddrc_cfg[19].val = 0x1010009; + dram_timing.ddrc_cfg[20].val = 0x502; + dram_timing.ddrc_cfg[21].val = 0x20800; + dram_timing.ddrc_cfg[22].val = 0xe100002; + dram_timing.ddrc_cfg[23].val = 0x120; + dram_timing.ddrc_cfg[24].val = 0xc80064; + dram_timing.ddrc_cfg[25].val = 0x3e8001e; + dram_timing.ddrc_cfg[26].val = 0x3207a12; + dram_timing.ddrc_cfg[28].val = 0x4a3820e; + dram_timing.ddrc_cfg[30].val = 0x230e; + dram_timing.ddrc_cfg[37].val = 0x799; + dram_timing.ddrc_cfg[38].val = 0x9141d1c; + dram_timing.ddrc_cfg[74].val = 0x302; + dram_timing.ddrc_cfg[83].val = 0x599; + dram_timing.ddrc_cfg[99].val = 0x302; + dram_timing.ddrc_cfg[108].val = 0x599; + dram_timing.ddrphy_cfg[66].val = 0x18; + dram_timing.ddrphy_cfg[75].val = 0x1e3; + dram_timing.ddrphy_cfg[77].val = 0x1e3; + dram_timing.ddrphy_cfg[79].val = 0x1e3; + dram_timing.ddrphy_cfg[145].val = 0x3e8; + dram_timing.fsp_msg[0].drate = 4000; + dram_timing.fsp_msg[0].fsp_cfg[1].val = 0xfa0; + dram_timing.fsp_msg[0].fsp_cfg[10].val = 0x3ff4; + dram_timing.fsp_msg[0].fsp_cfg[11].val = 0xf3; + dram_timing.fsp_msg[0].fsp_cfg[15].val = 0x3ff4; + dram_timing.fsp_msg[0].fsp_cfg[16].val = 0xf3; + dram_timing.fsp_msg[0].fsp_cfg[22].val = 0xf400; + dram_timing.fsp_msg[0].fsp_cfg[23].val = 0xf33f; + dram_timing.fsp_msg[0].fsp_cfg[28].val = 0xf400; + dram_timing.fsp_msg[0].fsp_cfg[29].val = 0xf33f; + dram_timing.fsp_msg[3].drate = 4000; + dram_timing.fsp_msg[3].fsp_cfg[1].val = 0xfa0; + dram_timing.fsp_msg[3].fsp_cfg[11].val = 0x3ff4; + dram_timing.fsp_msg[3].fsp_cfg[12].val = 0xf3; + dram_timing.fsp_msg[3].fsp_cfg[16].val = 0x3ff4; + dram_timing.fsp_msg[3].fsp_cfg[17].val = 0xf3; + dram_timing.fsp_msg[3].fsp_cfg[23].val = 0xf400; + dram_timing.fsp_msg[3].fsp_cfg[24].val = 0xf33f; + dram_timing.fsp_msg[3].fsp_cfg[29].val = 0xf400; + dram_timing.fsp_msg[3].fsp_cfg[30].val = 0xf33f; + dram_timing.ddrphy_pie[480].val = 0x465; + dram_timing.ddrphy_pie[481].val = 0xfa; + dram_timing.ddrphy_pie[482].val = 0x9c4; + dram_timing.fsp_table[0] = 4000; +} + +void set_dram_timings_1_5ghz_1gb(void) +{ + dram_timing.ddrc_cfg[3].val = 0x1233; + dram_timing.ddrc_cfg[5].val = 0x5b0087; + dram_timing.ddrc_cfg[6].val = 0x61027f10; + dram_timing.ddrc_cfg[7].val = 0x7b0; + dram_timing.ddrc_cfg[11].val = 0xf30000; + dram_timing.ddrc_cfg[23].val = 0x8d; + dram_timing.ddrc_cfg[45].val = 0xf070707; + dram_timing.ddrc_cfg[59].val = 0x1031; + dram_timing.ddrc_cfg[62].val = 0xc0012; + dram_timing.ddrc_cfg[77].val = 0x13; + dram_timing.ddrc_cfg[84].val = 0x1031; + dram_timing.ddrc_cfg[87].val = 0x30005; + dram_timing.ddrc_cfg[102].val = 0x5; + dram_timing.ddrphy_cfg[75].val = 0x1e3; + dram_timing.ddrphy_cfg[77].val = 0x1e3; + dram_timing.ddrphy_cfg[79].val = 0x1e3; + dram_timing.fsp_msg[0].fsp_cfg[11].val = 0xf3; + dram_timing.fsp_msg[0].fsp_cfg[16].val = 0xf3; + dram_timing.fsp_msg[0].fsp_cfg[23].val = 0xf32d; + dram_timing.fsp_msg[0].fsp_cfg[29].val = 0xf32d; + dram_timing.fsp_msg[3].fsp_cfg[12].val = 0xf3; + dram_timing.fsp_msg[3].fsp_cfg[17].val = 0xf3; + dram_timing.fsp_msg[3].fsp_cfg[24].val = 0xf32d; + dram_timing.fsp_msg[3].fsp_cfg[30].val = 0xf32d; +} + +void set_dram_timings_2ghz_1gb(void) +{ + set_dram_timings_2ghz_2gb(); + dram_timing.ddrc_cfg[5].val = 0x7a00b4; + dram_timing.ddrc_cfg[23].val = 0xbc; + dram_timing.ddrc_cfg[45].val = 0xf070707; + dram_timing.ddrc_cfg[62].val = 0xc0012; + dram_timing.ddrc_cfg[77].val = 0x13; + dram_timing.ddrc_cfg[87].val = 0x30005; + dram_timing.ddrc_cfg[102].val = 0x5; +} + +void set_dram_timings_1_5ghz_4gb(void) +{ + dram_timing.ddrc_cfg[2].val = 0xa3080020; + dram_timing.ddrc_cfg[39].val = 0x17; + dram_timing.fsp_msg[0].fsp_cfg[9].val = 0x310; + dram_timing.fsp_msg[0].fsp_cfg[21].val = 0x3; + dram_timing.fsp_msg[1].fsp_cfg[10].val = 0x310; + dram_timing.fsp_msg[1].fsp_cfg[22].val = 0x3; + dram_timing.fsp_msg[2].fsp_cfg[10].val = 0x310; + dram_timing.fsp_msg[2].fsp_cfg[22].val = 0x3; + dram_timing.fsp_msg[3].fsp_cfg[10].val = 0x310; + dram_timing.fsp_msg[3].fsp_cfg[22].val = 0x3; +} + +void set_dram_timings_2ghz_4gb(void) +{ + set_dram_timings_2ghz_2gb(); + dram_timing.ddrc_cfg[2].val = 0xa3080020; + dram_timing.ddrc_cfg[39].val = 0x17; + dram_timing.fsp_msg[0].fsp_cfg[9].val = 0x310; + dram_timing.fsp_msg[0].fsp_cfg[21].val = 0x3; + dram_timing.fsp_msg[1].fsp_cfg[10].val = 0x310; + dram_timing.fsp_msg[1].fsp_cfg[22].val = 0x3; + dram_timing.fsp_msg[2].fsp_cfg[10].val = 0x310; + dram_timing.fsp_msg[2].fsp_cfg[22].val = 0x3; + dram_timing.fsp_msg[3].fsp_cfg[10].val = 0x310; + dram_timing.fsp_msg[3].fsp_cfg[22].val = 0x3; +} + +void set_dram_timings_2ghz_8gb(void) +{ + set_dram_timings_2ghz_2gb(); + dram_timing.ddrc_cfg[2].val = 0xa3080020; + dram_timing.ddrc_cfg[5].val = 0x7a017c; + dram_timing.ddrc_cfg[23].val = 0x184; + dram_timing.ddrc_cfg[39].val = 0x18; + dram_timing.ddrc_cfg[46].val = 0xf07; + dram_timing.ddrc_cfg[62].val = 0xc0026; + dram_timing.ddrc_cfg[77].val = 0x27; + dram_timing.ddrc_cfg[87].val = 0x3000a; + dram_timing.ddrc_cfg[102].val = 0xa; + + dram_timing.fsp_msg[0].fsp_cfg[9].val = 0x310; + dram_timing.fsp_msg[0].fsp_cfg[21].val = 0x3; + dram_timing.fsp_msg[1].fsp_cfg[10].val = 0x310; + dram_timing.fsp_msg[1].fsp_cfg[22].val = 0x3; + dram_timing.fsp_msg[2].fsp_cfg[10].val = 0x310; + dram_timing.fsp_msg[2].fsp_cfg[22].val = 0x3; + dram_timing.fsp_msg[3].fsp_cfg[10].val = 0x310; + dram_timing.fsp_msg[3].fsp_cfg[22].val = 0x3; +} diff --git a/board/phytec/phycore_imx8mp/lpddr4_timing.h b/board/phytec/phycore_imx8mp/lpddr4_timing.h new file mode 100644 index 000000000000..1c10e085a92a --- /dev/null +++ b/board/phytec/phycore_imx8mp/lpddr4_timing.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2024 PHYTEC Messtechnik GmbH + */ + +#ifndef __LPDDR4_TIMING_H__ +#define __LPDDR4_TIMING_H__ + +void set_dram_timings_2ghz_2gb(void); +void set_dram_timings_2ghz_1gb(void); +void set_dram_timings_2ghz_4gb(void); +void set_dram_timings_1_5ghz_1gb(void); +void set_dram_timings_1_5ghz_4gb(void); +void set_dram_timings_2ghz_8gb(void); + +#endif /* __LPDDR4_TIMING_H__ */ diff --git a/board/phytec/phycore_imx8mp/phycore-imx8mp.c b/board/phytec/phycore_imx8mp/phycore-imx8mp.c index dbdd6bb79373..af54fbd8f559 100644 --- a/board/phytec/phycore_imx8mp/phycore-imx8mp.c +++ b/board/phytec/phycore_imx8mp/phycore-imx8mp.c @@ -10,6 +10,7 @@ #include #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -56,3 +57,13 @@ int board_late_init(void) return 0; } + +int board_phys_sdram_size(phys_size_t *size) +{ + if (!size) + return -EINVAL; + + *size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE + PHYS_SDRAM_2_SIZE); + + return 0; +} diff --git a/board/phytec/phycore_imx8mp/spl.c b/board/phytec/phycore_imx8mp/spl.c index 492ce3b7ca6e..f24f09301f1e 100644 --- a/board/phytec/phycore_imx8mp/spl.c +++ b/board/phytec/phycore_imx8mp/spl.c @@ -21,6 +21,7 @@ #include #include +#include "lpddr4_timing.h" #include "../common/imx8m_som_detection.h" DECLARE_GLOBAL_DATA_PTR; @@ -33,9 +34,19 @@ int spl_board_boot_device(enum boot_device boot_dev_spl) return BOOT_DEVICE_BOOTROM; } +enum phytec_imx8mp_ddr_eeprom_code { + PHYTEC_IMX8MP_DDR_1GB = 2, + PHYTEC_IMX8MP_DDR_2GB = 3, + PHYTEC_IMX8MP_DDR_4GB = 5, + PHYTEC_IMX8MP_DDR_8GB = 7, + PHYTEC_IMX8MP_DDR_4GB_2GHZ = 8, +}; + void spl_dram_init(void) { int ret; + bool use_2ghz_timings = false; + enum phytec_imx8mp_ddr_eeprom_code size = PHYTEC_EEPROM_INVAL; ret = phytec_eeprom_data_setup_fallback(NULL, 0, EEPROM_ADDR, EEPROM_ADDR_FALLBACK); @@ -49,67 +60,38 @@ void spl_dram_init(void) u8 rev = phytec_get_rev(NULL); u8 somtype = phytec_get_som_type(NULL); - if (rev != PHYTEC_EEPROM_INVAL && (rev >= 3 || (somtype == SOM_TYPE_PCL && rev >= 1))) { - dram_timing.ddrc_cfg[3].val = 0x1323; - dram_timing.ddrc_cfg[4].val = 0x1e84800; - dram_timing.ddrc_cfg[5].val = 0x7a0118; - dram_timing.ddrc_cfg[8].val = 0xc00307a3; - dram_timing.ddrc_cfg[9].val = 0xc50000; - dram_timing.ddrc_cfg[10].val = 0xf4003f; - dram_timing.ddrc_cfg[11].val = 0xf30000; - dram_timing.ddrc_cfg[14].val = 0x2028222a; - dram_timing.ddrc_cfg[15].val = 0x8083f; - dram_timing.ddrc_cfg[16].val = 0xe0e000; - dram_timing.ddrc_cfg[17].val = 0x12040a12; - dram_timing.ddrc_cfg[18].val = 0x2050f0f; - dram_timing.ddrc_cfg[19].val = 0x1010009; - dram_timing.ddrc_cfg[20].val = 0x502; - dram_timing.ddrc_cfg[21].val = 0x20800; - dram_timing.ddrc_cfg[22].val = 0xe100002; - dram_timing.ddrc_cfg[23].val = 0x120; - dram_timing.ddrc_cfg[24].val = 0xc80064; - dram_timing.ddrc_cfg[25].val = 0x3e8001e; - dram_timing.ddrc_cfg[26].val = 0x3207a12; - dram_timing.ddrc_cfg[28].val = 0x4a3820e; - dram_timing.ddrc_cfg[30].val = 0x230e; - dram_timing.ddrc_cfg[37].val = 0x799; - dram_timing.ddrc_cfg[38].val = 0x9141d1c; - dram_timing.ddrc_cfg[74].val = 0x302; - dram_timing.ddrc_cfg[83].val = 0x599; - dram_timing.ddrc_cfg[99].val = 0x302; - dram_timing.ddrc_cfg[108].val = 0x599; - dram_timing.ddrphy_cfg[66].val = 0x18; - dram_timing.ddrphy_cfg[75].val = 0x1e3; - dram_timing.ddrphy_cfg[77].val = 0x1e3; - dram_timing.ddrphy_cfg[79].val = 0x1e3; - dram_timing.ddrphy_cfg[145].val = 0x3e8; - dram_timing.fsp_msg[0].drate = 4000; - dram_timing.fsp_msg[0].fsp_cfg[1].val = 0xfa0; - dram_timing.fsp_msg[0].fsp_cfg[10].val = 0x3ff4; - dram_timing.fsp_msg[0].fsp_cfg[11].val = 0xf3; - dram_timing.fsp_msg[0].fsp_cfg[15].val = 0x3ff4; - dram_timing.fsp_msg[0].fsp_cfg[16].val = 0xf3; - dram_timing.fsp_msg[0].fsp_cfg[22].val = 0xf400; - dram_timing.fsp_msg[0].fsp_cfg[23].val = 0xf33f; - dram_timing.fsp_msg[0].fsp_cfg[28].val = 0xf400; - dram_timing.fsp_msg[0].fsp_cfg[29].val = 0xf33f; - dram_timing.fsp_msg[3].drate = 4000; - dram_timing.fsp_msg[3].fsp_cfg[1].val = 0xfa0; - dram_timing.fsp_msg[3].fsp_cfg[11].val = 0x3ff4; - dram_timing.fsp_msg[3].fsp_cfg[12].val = 0xf3; - dram_timing.fsp_msg[3].fsp_cfg[16].val = 0x3ff4; - dram_timing.fsp_msg[3].fsp_cfg[17].val = 0xf3; - dram_timing.fsp_msg[3].fsp_cfg[23].val = 0xf400; - dram_timing.fsp_msg[3].fsp_cfg[24].val = 0xf33f; - dram_timing.fsp_msg[3].fsp_cfg[29].val = 0xf400; - dram_timing.fsp_msg[3].fsp_cfg[30].val = 0xf33f; - dram_timing.ddrphy_pie[480].val = 0x465; - dram_timing.ddrphy_pie[481].val = 0xfa; - dram_timing.ddrphy_pie[482].val = 0x9c4; - dram_timing.fsp_table[0] = 4000; + if (rev != PHYTEC_EEPROM_INVAL && (rev >= 3 || (somtype == SOM_TYPE_PCL && rev >= 1))) + use_2ghz_timings = true; + + size = phytec_get_imx8m_ddr_size(NULL); + + switch (size) { + case PHYTEC_IMX8MP_DDR_1GB: + if (use_2ghz_timings) + set_dram_timings_2ghz_1gb(); + else + set_dram_timings_1_5ghz_1gb(); + break; + case PHYTEC_IMX8MP_DDR_2GB: + if (use_2ghz_timings) + set_dram_timings_2ghz_2gb(); + break; + case PHYTEC_IMX8MP_DDR_4GB: + set_dram_timings_1_5ghz_4gb(); + break; + case PHYTEC_IMX8MP_DDR_4GB_2GHZ: + set_dram_timings_2ghz_4gb(); + break; + case PHYTEC_IMX8MP_DDR_8GB: + set_dram_timings_2ghz_8gb(); + break; + default: + goto out; } - + ddr_init(&dram_timing); + return; out: + printf("Could not detect correct RAM size. Fallback to default.\n"); ddr_init(&dram_timing); } diff --git a/include/configs/phycore_imx8mp.h b/include/configs/phycore_imx8mp.h index 206c4d50d276..299fabc6a99b 100644 --- a/include/configs/phycore_imx8mp.h +++ b/include/configs/phycore_imx8mp.h @@ -22,6 +22,8 @@ #define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 -#define PHYS_SDRAM_SIZE 0x80000000 +#define PHYS_SDRAM_SIZE (SZ_2G + SZ_1G) /* 3GB */ +#define PHYS_SDRAM_2 0x100000000 +#define PHYS_SDRAM_2_SIZE (SZ_4G + SZ_1G) /* 5GB */ #endif /* __PHYCORE_IMX8MP_H */ From patchwork Tue May 28 13:35:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Teresa Remmet X-Patchwork-Id: 1940511 X-Patchwork-Delegate: festevam@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=phytec.de header.i=@phytec.de header.a=rsa-sha256 header.s=a4 header.b=HpWpo98k; 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Tue, 28 May 2024 15:35:27 +0200 (CEST) Received: from llp-tremmet2.phytec.de (172.25.0.11) by Berlix.phytec.de (172.25.0.12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.6; Tue, 28 May 2024 15:35:26 +0200 From: Teresa Remmet To: CC: Yannic Moog , Fabio Estevam , Tom Rini , Benjamin Hahn , Yashwanth Varakala , Wadim Egorov , Subject: [PATCH 3/4] board: phytec: phycore_imx8mp: Make RAM size configuration fix Date: Tue, 28 May 2024 15:35:14 +0200 Message-ID: <20240528133515.307315-4-t.remmet@phytec.de> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240528133515.307315-1-t.remmet@phytec.de> References: <20240528133515.307315-1-t.remmet@phytec.de> MIME-Version: 1.0 X-Originating-IP: [172.25.0.11] X-ClientProxiedBy: Florix.phytec.de (172.25.0.13) To Berlix.phytec.de (172.25.0.12) X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrLLMWRmVeSWpSXmKPExsWyRpKBR3f+3dA0g5vvRC0eXvW3mDppM7vF 272d7Bbd79QdWDx2zrrL7vHqwCp2j7N3djB69He3sAawRHHZpKTmZJalFunbJXBlHNu8iq2g V75i5e437A2MFyW7GDk5JARMJHrbd7KA2EICS5gkvj8ShbCfMkqcXGEFYrMJaEg8XXGaCcQW EZCSeNm5kbmLkYuDWeA7o8Schf3sIAlhgWCJSztXs4HYLAKqEs+enWUEsXkFLCTuHz3EArFM XmL/wbPMIDangKXEikl9TBDLLCQu7t/DDFEvKHFy5hOwemag+uats5khbAmJgy9eMEPUy0vs unSSEWbmtHOvmSHsUIkjm1YzTWAUmoVk1Cwko2YhGbWAkXkVo1BuZnJ2alFmtl5BRmVJarJe SuomRlCQizBw7WDsm+NxiJGJg/EQowQHs5II75lJoWlCvCmJlVWpRfnxRaU5qcWHGKU5WJTE eVd3BKcKCaQnlqRmp6YWpBbBZJk4OKUaGP02m98+WLhLM2Nr2tEtCS/+3p1iGD3Fl+v8woRN a30ijR8eEbM9fWDmrE3uM9hv/NnOvJNVVt9fK8jvzIw0O5nqt0cZrKJ/nfy0IODFbtsKeemr nz5M6PD918vub3CbddsctlvT3zjq8t+0sPM9uU+nd912ofdv9jZzCT/ROXqAYXl/xPTYLT+V WIozEg21mIuKEwGQIKB4YAIAAA== X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean We might not be able to always rely on the EEPROM introspection data. So add a config option alternative which configures the RAM size to a fix value. We still try to read the EEPROM introspection data at this point. So we can print the SoM information if available. Signed-off-by: Teresa Remmet --- board/phytec/phycore_imx8mp/Kconfig | 48 +++++++++++++++++++++++++++++ board/phytec/phycore_imx8mp/spl.c | 34 +++++++++++++++----- 2 files changed, 74 insertions(+), 8 deletions(-) diff --git a/board/phytec/phycore_imx8mp/Kconfig b/board/phytec/phycore_imx8mp/Kconfig index f846d10bad9e..5ede39abc52b 100644 --- a/board/phytec/phycore_imx8mp/Kconfig +++ b/board/phytec/phycore_imx8mp/Kconfig @@ -12,5 +12,53 @@ config SYS_CONFIG_NAME config IMX_CONFIG default "board/phytec/phycore_imx8mp/imximage-8mp-sd.cfg" +config PHYCORE_IMX8MP_RAM_SIZE_FIX + bool "Set phyCORE-i.MX8MP RAM size fix instead of detecting" + default false + help + RAM size is automatic being detected with the help of + the EEPROM introspection data. Set RAM size to a fix value + instead. + +choice + prompt "phyCORE-i.MX8MP RAM size" + depends on PHYCORE_IMX8MP_RAM_SIZE_FIX + default PHYCORE_IMX8MP_RAM_SIZE_2GB + +config PHYCORE_IMX8MP_RAM_SIZE_1GB + bool "1GB RAM" + help + Set RAM size fix to 1GB for phyCORE-i.MX8MP. + RAM frequency is configured independent. + +config PHYCORE_IMX8MP_RAM_SIZE_2GB + bool "2GB RAM" + help + Set RAM size fix to 2GB for phyCORE-i.MX8MP. + RAM frequency is configured independent. + +config PHYCORE_IMX8MP_RAM_SIZE_4GB + bool "4GB RAM" + help + Set RAM size fix to 4GB for phyCORE-i.MX8MP. + RAM frequency is configured independent. + +config PHYCORE_IMX8MP_RAM_SIZE_8GB + bool "8GB RAM" + select PHYCORE_IMX8MP_USE_2GHZ_RAM_TIMINGS + help + Set RAM size fix to 8GB for phyCORE-i.MX8MP. + Only 2GHz RAMs are supported. + +endchoice + +config PHYCORE_IMX8MP_USE_2GHZ_RAM_TIMINGS + bool "Use 2GHz RAM timings" + depends on PHYCORE_IMX8MP_RAM_SIZE_FIX + default false + help + Use fix 2GHz RAM timings for phyCORE-i.MX8MP instead of + 1.5GHz timings. + source "board/phytec/common/Kconfig" endif diff --git a/board/phytec/phycore_imx8mp/spl.c b/board/phytec/phycore_imx8mp/spl.c index f24f09301f1e..8a0c456859e2 100644 --- a/board/phytec/phycore_imx8mp/spl.c +++ b/board/phytec/phycore_imx8mp/spl.c @@ -50,20 +50,38 @@ void spl_dram_init(void) ret = phytec_eeprom_data_setup_fallback(NULL, 0, EEPROM_ADDR, EEPROM_ADDR_FALLBACK); - if (ret) + if (ret && !IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_FIX)) goto out; ret = phytec_imx8m_detect(NULL); if (!ret) phytec_print_som_info(NULL); - u8 rev = phytec_get_rev(NULL); - u8 somtype = phytec_get_som_type(NULL); - - if (rev != PHYTEC_EEPROM_INVAL && (rev >= 3 || (somtype == SOM_TYPE_PCL && rev >= 1))) - use_2ghz_timings = true; - - size = phytec_get_imx8m_ddr_size(NULL); + if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_FIX)) { + if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_1GB)) + size = PHYTEC_IMX8MP_DDR_1GB; + else if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_2GB)) + size = PHYTEC_IMX8MP_DDR_2GB; + else if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_4GB)) + size = PHYTEC_IMX8MP_DDR_4GB; + else if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_8GB)) + size = PHYTEC_IMX8MP_DDR_8GB; + if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_USE_2GHZ_RAM_TIMINGS)) { + if (size == PHYTEC_IMX8MP_DDR_4GB) + size = PHYTEC_IMX8MP_DDR_4GB_2GHZ; + else + use_2ghz_timings = true; + } + } else { + u8 rev = phytec_get_rev(NULL); + u8 somtype = phytec_get_som_type(NULL); + + if (rev != PHYTEC_EEPROM_INVAL && + (rev >= 3 || (somtype == SOM_TYPE_PCL && rev >= 1))) + use_2ghz_timings = true; + + size = phytec_get_imx8m_ddr_size(NULL); + } switch (size) { case PHYTEC_IMX8MP_DDR_1GB: From patchwork Tue May 28 13:35:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Teresa Remmet X-Patchwork-Id: 1940509 X-Patchwork-Delegate: festevam@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=phytec.de header.i=@phytec.de header.a=rsa-sha256 header.s=a4 header.b=m5Lvvxjn; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; 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bh=Nh73erwLEwZNnmzRjxO2fmTQwAhoN6IC1/cd0nyhjiA=; b=m5LvvxjnkImxe2MkgoBT0yY55LxcnEeavY4EHnoaUT5pctYNFjY0OWvcNgEPNuC4 6Y/K74TF18TyILmMxSPp+pnT8k8vRfOBvhw8s/GTrkA7Mq0fM4Al4Io0Kf9jSZkl fxfORhs9oLPHNzl3C3dQoWDyTwpeqvcpeTeuJtlsIW0=; X-AuditID: ac14000a-03251700000021bc-29-6655dd9ffadb Received: from berlix.phytec.de (Unknown_Domain [172.25.0.12]) (using TLS with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (Client did not present a certificate) by mickerik.phytec.de (PHYTEC Mail Gateway) with SMTP id B3.E8.08636.F9DD5566; Tue, 28 May 2024 15:35:27 +0200 (CEST) Received: from llp-tremmet2.phytec.de (172.25.0.11) by Berlix.phytec.de (172.25.0.12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.6; Tue, 28 May 2024 15:35:27 +0200 From: Teresa Remmet To: CC: Yannic Moog , Fabio Estevam , Tom Rini , Benjamin Hahn , Yashwanth Varakala , Wadim Egorov , Subject: [PATCH 4/4] board: phycore_imx8mp: enable setting 2GHz timings without RAM size Date: Tue, 28 May 2024 15:35:15 +0200 Message-ID: <20240528133515.307315-5-t.remmet@phytec.de> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240528133515.307315-1-t.remmet@phytec.de> References: <20240528133515.307315-1-t.remmet@phytec.de> MIME-Version: 1.0 X-Originating-IP: [172.25.0.11] X-ClientProxiedBy: Florix.phytec.de (172.25.0.13) To Berlix.phytec.de (172.25.0.12) X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrHLMWRmVeSWpSXmKPExsWyRpKBR3f+3dA0g4c/tSweXvW3mDppM7vF 272d7Bbd79QdWDx2zrrL7vHqwCp2j7N3djB69He3sAawRHHZpKTmZJalFunbJXBlPPipVPBf rOLZx3nsDYw/hLoYOTkkBEwkbs3bydrFyMUhJLCESWL2p/uMEM5TRokDc2exgFSxCWhIPF1x mgnEFhGQknjZuZEZpIhZ4DujxJyF/ewgCWGBCIkdz36B2SwCqhKzj91hA7F5BSwk+uatYYRY Jy+x/+BZZhCbU8BSYsWkPrChQkA1F/fvYYaoF5Q4OfMJ2GJmoPrmrbOZIWwJiYMvXjBD1MtL 7Lp0Em7mtHOvmSHsUIkjm1YzTWAUmoVk1Cwko2YhGbWAkXkVo1BuZnJ2alFmtl5BRmVJarJe SuomRlCYizBw7WDsm+NxiJGJg/EQowQHs5II75lJoWlCvCmJlVWpRfnxRaU5qcWHGKU5WJTE eVd3BKcKCaQnlqRmp6YWpBbBZJk4OKUaGH31VvFZVatP+lnKcaRnm5Zb26PLxrGtu/4Uzbjx 1Ys1QJq3rLT9/ARn9Zt1gd/WL+U3Kb32oOE0xz1rkyd7OfsS04sSfun//c9XYpqUrN/8bHNo Fou6vmi0d6/mpy/PZgeIrOaN6fK5lFp2afux+F3Gvp+/eh+J0DG1nTPFs+m+VKxhvBunEktx RqKhFnNRcSIAxMv9D2ECAAA= X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Benjamin Hahn make it possible to set the RAM timing frequency statically independent from the RAM size. Fixed RAM timing frequency can be used while the RAM size is still determined by the EEPROM image. Signed-off-by: Benjamin Hahn Signed-off-by: Teresa Remmet --- board/phytec/phycore_imx8mp/Kconfig | 23 +++++++++++++++++++++-- board/phytec/phycore_imx8mp/spl.c | 12 ++++++++++-- 2 files changed, 31 insertions(+), 4 deletions(-) diff --git a/board/phytec/phycore_imx8mp/Kconfig b/board/phytec/phycore_imx8mp/Kconfig index 5ede39abc52b..bdf9e97beaa6 100644 --- a/board/phytec/phycore_imx8mp/Kconfig +++ b/board/phytec/phycore_imx8mp/Kconfig @@ -52,13 +52,32 @@ config PHYCORE_IMX8MP_RAM_SIZE_8GB endchoice +config PHYCORE_IMX8MP_RAM_FREQ_FIX + bool "Set phyCORE-i.MX8MP RAM frequency fix instead of detecting" + default false + help + RAM frequency is automatic being detected with the help of + the EEPROM introspection data. Set RAM frequency to a fix value + instead. + +choice + prompt "phyCORE-i.MX8MP RAM frequency" + depends on PHYCORE_IMX8MP_RAM_FREQ_FIX + default PHYCORE_IMX8MP_USE_1_5GHZ_RAM_TIMINGS + config PHYCORE_IMX8MP_USE_2GHZ_RAM_TIMINGS bool "Use 2GHz RAM timings" - depends on PHYCORE_IMX8MP_RAM_SIZE_FIX - default false help Use fix 2GHz RAM timings for phyCORE-i.MX8MP instead of 1.5GHz timings. +config PHYCORE_IMX8MP_USE_1_5GHZ_RAM_TIMINGS + depends on !PHYCORE_IMX8MP_RAM_SIZE_8GB + bool "Use 1.5GHz RAM timings" + help + Use fix 1.5GHz RAM timings for phyCORE-i.MX8MP instead of + 2GHz timings. +endchoice + source "board/phytec/common/Kconfig" endif diff --git a/board/phytec/phycore_imx8mp/spl.c b/board/phytec/phycore_imx8mp/spl.c index 8a0c456859e2..30964bc5e547 100644 --- a/board/phytec/phycore_imx8mp/spl.c +++ b/board/phytec/phycore_imx8mp/spl.c @@ -66,11 +66,21 @@ void spl_dram_init(void) size = PHYTEC_IMX8MP_DDR_4GB; else if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_8GB)) size = PHYTEC_IMX8MP_DDR_8GB; + } else { + size = phytec_get_imx8m_ddr_size(NULL); + } + + if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_FREQ_FIX)) { if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_USE_2GHZ_RAM_TIMINGS)) { if (size == PHYTEC_IMX8MP_DDR_4GB) size = PHYTEC_IMX8MP_DDR_4GB_2GHZ; else use_2ghz_timings = true; + } else if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_USE_1_5GHZ_RAM_TIMINGS)) { + if (size == PHYTEC_IMX8MP_DDR_4GB_2GHZ) + size = PHYTEC_IMX8MP_DDR_4GB; + else + use_2ghz_timings = false; } } else { u8 rev = phytec_get_rev(NULL); @@ -79,8 +89,6 @@ void spl_dram_init(void) if (rev != PHYTEC_EEPROM_INVAL && (rev >= 3 || (somtype == SOM_TYPE_PCL && rev >= 1))) use_2ghz_timings = true; - - size = phytec_get_imx8m_ddr_size(NULL); } switch (size) {