From patchwork Tue May 28 11:24:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yannic Moog X-Patchwork-Id: 1940419 X-Patchwork-Delegate: festevam@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=phytec.de header.i=@phytec.de header.a=rsa-sha256 header.s=a4 header.b=ZM2LhzId; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4VpVYj1cN3z20Pb for ; Tue, 28 May 2024 21:25:29 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 96A3A884BC; Tue, 28 May 2024 13:25:10 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=phytec.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=phytec.de header.i=@phytec.de header.b="ZM2LhzId"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 359AE8848A; Tue, 28 May 2024 13:25:09 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED,RCVD_IN_VALIDITY_RPBL_BLOCKED, SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.2 Received: from mickerik.phytec.de (mickerik.phytec.de [91.26.50.163]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 7F38B8848A for ; Tue, 28 May 2024 13:25:03 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=phytec.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=Y.Moog@phytec.de DKIM-Signature: v=1; a=rsa-sha256; d=phytec.de; s=a4; c=relaxed/simple; q=dns/txt; i=@phytec.de; t=1716895503; x=1719487503; h=From:Sender:Reply-To:Subject:Date:Message-ID:To:CC:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=FkF32S43Fc0Qi8zUP8GdrMflu65aJp21weqKajNbBD0=; b=ZM2LhzIdYDxI3ZyKi2km6uhqZ8KY/FLIoUlahkRC0mPoZjHqDpJe49scDXsqnawm mh/oiQ2DNVjmOJI8Hcdsy4wtuwaVd4jKlXWO9nXMVwjM1TU2G17jlrFAZ6e39fsa o2t7fplqnA74emciRexj03IpejiqwW/xW4LZ0AyBvdU=; X-AuditID: ac14000a-03e52700000021bc-7e-6655bf0fc17a Received: from berlix.phytec.de (Unknown_Domain [172.25.0.12]) (using TLS with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (Client did not present a certificate) by mickerik.phytec.de (PHYTEC Mail Gateway) with SMTP id 62.F7.08636.F0FB5566; Tue, 28 May 2024 13:25:03 +0200 (CEST) Received: from lws-moog.phytec.de (172.25.0.11) by Berlix.phytec.de (172.25.0.12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.6; Tue, 28 May 2024 13:25:03 +0200 From: Yannic Moog Date: Tue, 28 May 2024 13:24:59 +0200 Subject: [PATCH 1/2] arm: imx8mm-phycore: move to OF_UPSTREAM MIME-Version: 1.0 Message-ID: <20240528-phytec_imx8_of_upstream-v1-1-c884c1ddca5f@phytec.de> References: <20240528-phytec_imx8_of_upstream-v1-0-c884c1ddca5f@phytec.de> In-Reply-To: <20240528-phytec_imx8_of_upstream-v1-0-c884c1ddca5f@phytec.de> To: Teresa Remmet , Stefano Babic , Fabio Estevam , NXP i.MX U-Boot Team CC: , , Yannic Moog X-Mailer: b4 0.13.0 X-Originating-IP: [172.25.0.11] X-ClientProxiedBy: Berlix.phytec.de (172.25.0.12) To Berlix.phytec.de (172.25.0.12) X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrOLMWRmVeSWpSXmKPExsWyRpKBR5d/f2iawaJ1whYPr/pbtJ/ysXi7 t5PdYsrj9ewW3e/UHVg95s06weKxc9Zddo+zd3YwevR3t7B6bHy3gymANYrLJiU1J7MstUjf LoEro+GpUsGrzUwVi/s+MzYw3vnJ2MXIySEhYCKx6PhZ1i5GLg4hgSVMEn+a17NAOA8ZJaZP a2UGqWITUJF4/OIeK4jNIqAqMe3QW7BuYQFbiWvXfrKB2LwCghInZz4BaubgYBbQlFi/Sx8k zCwgL7H97RxmiBIviWsHjoONEQKyu/cdBYtzCnhLfDn3lB1kr4jANKC9u+azQjRHSFy7uYQd 4lJhifMLprBBNMtKvDjfCxWXl5h27jUzhB0qsfXLdqYJjEKzkJw0C+GkWUhOWsDIvIpRKDcz OTu1KDNbryCjsiQ1WS8ldRMjKPBFGLh2MPbN8TjEyMTBeIhRgoNZSYT3zKTQNCHelMTKqtSi /Pii0pzU4kOM0hwsSuK8qzuCU4UE0hNLUrNTUwtSi2CyTBycUg2MBgvrz3wqdRVT5XxQGn5b sVFzuc/cF2dKl4epyH7YIPWN9dLF8w9vui1LaL7jv2vr88dy0m+3LGzYXrVCMlyWz1Dv83xl 7fXSzSozSy27ut1UtpTHG9xoOa9qcaAi8JPARMcI/aeLnW7Mze2tsuzMCThktzCu4cWzss9T uN8yCgrFaNi+5JqkxFKckWioxVxUnAgA9UL7EGoCAAA= X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The PHYCORE_IMX8MM is used by the phyBOARD-Polis and the phyGATE-Tauri-L. Migrate both boards to OF_UPSTREAM. Linux kernel device trees for both boards can be used as is, corresponding U-Boot device tree files are removed. U-Boot tweaks are kept unchanged. Signed-off-by: Yannic Moog Reviewed-by: Fabio Estevam Acked-by: Teresa Remmet --- arch/arm/dts/Makefile | 2 - arch/arm/dts/imx8mm-phyboard-polis-rdk.dts | 460 --------------------------- arch/arm/dts/imx8mm-phycore-som.dtsi | 440 -------------------------- arch/arm/dts/imx8mm-phygate-tauri-l.dts | 489 ----------------------------- arch/arm/mach-imx/imx8m/Kconfig | 1 + board/phytec/phycore_imx8mm/MAINTAINERS | 3 - configs/imx8mm-phygate-tauri-l_defconfig | 2 +- configs/phycore-imx8mm_defconfig | 2 +- 8 files changed, 3 insertions(+), 1396 deletions(-) diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index c9f1b25ad64..480f8ff569d 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1016,8 +1016,6 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mm-kontron-bl-osm-s.dtb \ imx8mm-mx8menlo.dtb \ imx8mm-phg.dtb \ - imx8mm-phyboard-polis-rdk.dtb \ - imx8mm-phygate-tauri-l.dtb \ imx8mn-bsh-smm-s2.dtb \ imx8mn-bsh-smm-s2pro.dtb \ imx8mq-cm.dtb \ diff --git a/arch/arm/dts/imx8mm-phyboard-polis-rdk.dts b/arch/arm/dts/imx8mm-phyboard-polis-rdk.dts deleted file mode 100644 index 03e7679217b..00000000000 --- a/arch/arm/dts/imx8mm-phyboard-polis-rdk.dts +++ /dev/null @@ -1,460 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2022 PHYTEC Messtechnik GmbH - * Author: Teresa Remmet - */ - -/dts-v1/; - -#include -#include -#include -#include "imx8mm-phycore-som.dtsi" - -/ { - model = "PHYTEC phyBOARD-Polis-i.MX8MM RDK"; - compatible = "phytec,imx8mm-phyboard-polis-rdk", - "phytec,imx8mm-phycore-som", "fsl,imx8mm"; - - chosen { - stdout-path = &uart3; - }; - - bt_osc_32k: bt-lp-clock { - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "bt_osc_32k"; - #clock-cells = <0>; - }; - - can_osc_40m: can-clock { - compatible = "fixed-clock"; - clock-frequency = <40000000>; - clock-output-names = "can_osc_40m"; - #clock-cells = <0>; - }; - - fan { - compatible = "gpio-fan"; - gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = <0 0 - 13000 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fan>; - #cooling-cells = <2>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds>; - - led-0 { - color = ; - function = LED_FUNCTION_DISK; - gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc2"; - }; - - led-1 { - color = ; - function = LED_FUNCTION_DISK; - gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc1"; - }; - - led-2 { - color = ; - function = LED_FUNCTION_CPU; - gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - usdhc1_pwrseq: pwr-seq { - compatible = "mmc-pwrseq-simple"; - post-power-on-delay-ms = <100>; - power-off-delay-us = <60>; - reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; - }; - - reg_can_en: regulator-can-en { - compatible = "regulator-fixed"; - gpio = <&gpio1 9 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can_en>; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "CAN_EN"; - startup-delay-us = <20>; - }; - - reg_usb_otg1_vbus: regulator-usb-otg1 { - compatible = "regulator-fixed"; - gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1pwrgrp>; - regulator-name = "usb_otg1_vbus"; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - }; - - reg_usdhc2_vmmc: regulator-usdhc2 { - compatible = "regulator-fixed"; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - off-on-delay-us = <20000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "VSD_3V3"; - }; - - reg_vcc_3v3: regulator-vcc-3v3 { - compatible = "regulator-fixed"; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "VCC_3V3"; - }; -}; - -/* SPI - CAN MCP251XFD */ -&ecspi1 { - cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - - can0: can@0 { - compatible = "microchip,mcp251xfd"; - clocks = <&can_osc_40m>; - interrupt-parent = <&gpio1>; - interrupts = <8 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can_int>; - reg = <0>; - spi-max-frequency = <20000000>; - xceiver-supply = <®_can_en>; - }; -}; - -&gpio1 { - gpio-line-names = "nINT_ETHPHY", "LED_RED", "WDOG_INT", "X_RTC_INT", - "", "", "", "RESET_ETHPHY", - "CAN_nINT", "CAN_EN", "nENABLE_FLATLINK", "", - "USB_OTG_VBUS_EN", "", "LED_GREEN", "LED_BLUE"; -}; - -&gpio2 { - gpio-line-names = "", "", "", "", - "", "", "BT_REG_ON", "WL_REG_ON", - "BT_DEV_WAKE", "BT_HOST_WAKE", "", "", - "X_SD2_CD_B", "", "", "", - "", "", "", "SD2_RESET_B"; -}; - -&gpio4 { - gpio-line-names = "", "", "", "", - "", "", "", "", - "FAN", "miniPCIe_nPERST", "", "", - "COEX1", "COEX2"; -}; - -&gpio5 { - gpio-line-names = "", "", "", "", - "", "", "", "", - "", "ECSPI1_SS0"; -}; - -&i2c4 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; -}; - -/* PCIe */ -&pcie0 { - assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, - <&clk IMX8MM_CLK_PCIE1_CTRL>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, - <&clk IMX8MM_SYS_PLL2_250M>; - assigned-clock-rates = <10000000>, <250000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio4 9 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pcie_phy { - clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; - fsl,clkreq-unsupported; - fsl,refclk-pad-mode = ; - fsl,tx-deemph-gen1 = <0x2d>; - fsl,tx-deemph-gen2 = <0xf>; - status = "okay"; -}; - -&rv3028 { - trickle-resistor-ohms = <3000>; -}; - -&snvs_pwrkey { - status = "okay"; -}; - -/* UART - RS232/RS485 */ -&uart1 { - assigned-clocks = <&clk IMX8MM_CLK_UART1>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - uart-has-rtscts; - status = "okay"; -}; - -/* UART - Sterling-LWB Bluetooth */ -&uart2 { - assigned-clocks = <&clk IMX8MM_CLK_UART2>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; - fsl,dte-mode; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2_bt>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - clocks = <&bt_osc_32k>; - clock-names = "lpo"; - device-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; - interrupt-names = "host-wakeup"; - interrupt-parent = <&gpio2>; - interrupts = <9 IRQ_TYPE_EDGE_BOTH>; - max-speed = <2000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_bt>; - shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; - vddio-supply = <®_vcc_3v3>; - }; -}; - -/* UART - console */ -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -/* USB */ -&usbotg1 { - adp-disable; - dr_mode = "otg"; - over-current-active-low; - samsung,picophy-pre-emp-curr-control = <3>; - samsung,picophy-dc-vol-level-adjust = <7>; - srp-disable; - vbus-supply = <®_usb_otg1_vbus>; - status = "okay"; -}; - -&usbotg2 { - disable-over-current; - dr_mode = "host"; - samsung,picophy-pre-emp-curr-control = <3>; - samsung,picophy-dc-vol-level-adjust = <7>; - status = "okay"; -}; - -/* SDIO - Sterling-LWB Wifi */ -&usdhc1 { - assigned-clocks = <&clk IMX8MM_CLK_USDHC1>; - assigned-clock-rates = <200000000>; - bus-width = <4>; - mmc-pwrseq = <&usdhc1_pwrseq>; - non-removable; - no-1-8-v; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - brcmf: wifi@1 { - compatible = "brcm,bcm4329-fmac"; - reg = <1>; - }; -}; - -/* SD-Card */ -&usdhc2 { - assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; - assigned-clock-rates = <200000000>; - bus-width = <4>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - disable-wp; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - vmmc-supply = <®_usdhc2_vmmc>; - vqmmc-supply = <®_nvcc_sd2>; - status = "okay"; -}; - -&iomuxc { - pinctrl_bt: btgrp { - fsl,pins = < - MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x00 - MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x00 - MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x00 - >; - }; - - pinctrl_can_en: can-engrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x00 - >; - }; - - pinctrl_can_int: can-intgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x00 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x80 - MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x80 - MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x80 - MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x00 - >; - }; - - pinctrl_fan: fan0grp { - fsl,pins = < - MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x16 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c2 - MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c2 - >; - }; - - pinctrl_leds: leds1grp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x16 - MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x16 - MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x16 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x00 - MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x12 - MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x12 - >; - }; - - pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x40 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x00 - MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x00 - MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x00 - MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x00 - >; - }; - - pinctrl_uart2_bt: uart2btgrp { - fsl,pins = < - MX8MM_IOMUXC_SAI3_RXC_UART2_DTE_RTS_B 0x00 - MX8MM_IOMUXC_SAI3_RXD_UART2_DTE_CTS_B 0x00 - MX8MM_IOMUXC_SAI3_TXC_UART2_DTE_RX 0x00 - MX8MM_IOMUXC_SAI3_TXFS_UART2_DTE_TX 0x00 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x40 - MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x40 - >; - }; - - pinctrl_usbotg1pwrgrp: usbotg1pwrgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x00 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x182 - MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0xc6 - MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc6 - MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc6 - MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc6 - MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc6 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x40 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x192 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d2 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d2 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d2 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d2 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d2 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - >; - }; - - pinctrl_wlan: wlangrp { - fsl,pins = < - MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x00 - >; - }; -}; diff --git a/arch/arm/dts/imx8mm-phycore-som.dtsi b/arch/arm/dts/imx8mm-phycore-som.dtsi deleted file mode 100644 index 92616bc4f71..00000000000 --- a/arch/arm/dts/imx8mm-phycore-som.dtsi +++ /dev/null @@ -1,440 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2022 PHYTEC Messtechnik GmbH - * Author: Teresa Remmet - */ - -#include "imx8mm.dtsi" -#include - -/ { - model = "PHYTEC phyCORE-i.MX8MM"; - compatible = "phytec,imx8mm-phycore-som", "fsl,imx8mm"; - - aliases { - rtc0 = &rv3028; - rtc1 = &snvs_rtc; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0 0x80000000>; - }; - - reg_vdd_3v3_s: regulator-vdd-3v3-s { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "VDD_3V3_S"; - }; -}; - -&A53_0 { - cpu-supply = <®_vdd_arm>; -}; - -&A53_1 { - cpu-supply = <®_vdd_arm>; -}; - -&A53_2 { - cpu-supply = <®_vdd_arm>; -}; - -&A53_3 { - cpu-supply = <®_vdd_arm>; -}; - -&ddrc { - operating-points-v2 = <&ddrc_opp_table>; - - ddrc_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-25000000 { - opp-hz = /bits/ 64 <25000000>; - }; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - - opp-750000000 { - opp-hz = /bits/ 64 <750000000>; - }; - }; -}; - -/* Ethernet */ -&fec1 { - fsl,magic-packet; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - enet-phy-lane-no-swap; - ti,clk-output-sel = ; - ti,fifo-depth = ; - ti,rx-internal-delay = ; - ti,tx-internal-delay = ; - reg = <0>; - reset-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - reset-assert-us = <1000>; - reset-deassert-us = <1000>; - }; - }; -}; - -/* SPI Flash */ -&flexspi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexspi0>; - status = "okay"; - - som_flash: flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <80000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <1>; - }; -}; - -&gpio1 { - gpio-line-names = "nINT_ETHPHY", "", "WDOG_INT", "X_RTC_INT", - "", "", "", "RESET_ETHPHY", - "", "", "nENABLE_FLATLINK"; -}; - -/* I2C1 */ -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default","gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - pmic@8 { - compatible = "nxp,pf8121a"; - reg = <0x08>; - - regulators { - reg_nvcc_sd1: ldo1 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "NVCC_SD1 (LDO1)"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - reg_nvcc_sd2: ldo2 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <1800000>; - regulator-name = "NVCC_SD2 (LDO2)"; - vselect-en; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - reg_vcc_enet: ldo3 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <2500000>; - regulator-min-microvolt = <1500000>; - regulator-name = "VCC_ENET_2V5 (LDO3)"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - reg_vdda_1v8: ldo4 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <1500000>; - regulator-name = "VDDA_1V8 (LDO4)"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-min-microvolt = <1500000>; - regulator-suspend-max-microvolt = <1500000>; - }; - }; - - reg_soc_vdda_phy: buck1 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <900000>; - regulator-min-microvolt = <400000>; - regulator-name = "VDD_SOC_VDDA_PHY_0P8 (BUCK1)"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-min-microvolt = <400000>; - regulator-suspend-max-microvolt = <400000>; - }; - }; - - reg_vdd_gpu_dram: buck2 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1000000>; - regulator-min-microvolt = <1000000>; - regulator-name = "VDD_GPU_DRAM (BUCK2)"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-max-microvolt = <1000000>; - regulator-suspend-min-microvolt = <1000000>; - }; - }; - - reg_vdd_gpu: buck3 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1000000>; - regulator-min-microvolt = <400000>; - regulator-name = "VDD_VPU (BUCK3)"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - reg_vdd_mipi: buck4 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1050000>; - regulator-min-microvolt = <900000>; - regulator-name = "VDD_MIPI_0P9 (BUCK4)"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - reg_vdd_arm: buck5 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1050000>; - regulator-min-microvolt = <400000>; - regulator-name = "VDD_ARM (BUCK5)"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - reg_vdd_1v8: buck6 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <1800000>; - regulator-name = "VDD_1V8 (BUCK6)"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-max-microvolt = <1800000>; - regulator-suspend-min-microvolt = <1800000>; - }; - }; - - reg_nvcc_dram: buck7 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1100000>; - regulator-min-microvolt = <1100000>; - regulator-name = "NVCC_DRAM_1P1V (BUCK7)"; - }; - - reg_vsnvs: vsnvs { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <1800000>; - regulator-name = "NVCC_SNVS_1P8 (VSNVS)"; - }; - }; - }; - - sn65dsi83: bridge@2d { - compatible = "ti,sn65dsi83"; - enable-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sn65dsi83>; - reg = <0x2d>; - status = "disabled"; - }; - - eeprom@51 { - compatible = "atmel,24c32"; - pagesize = <32>; - reg = <0x51>; - vcc-supply = <®_vdd_3v3_s>; - }; - - rv3028: rtc@52 { - compatible = "microcrystal,rv3028"; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - interrupt-parent = <&gpio1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rtc>; - reg = <0x52>; - }; -}; - -/* EMMC */ -&usdhc3 { - assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; - assigned-clock-rates = <400000000>; - bus-width = <8>; - keep-power-in-suspend; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - non-removable; - status = "okay"; -}; - -/* Watchdog */ -&wdog1 { - fsl,ext-reset-output; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - status = "okay"; -}; - -&iomuxc { - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x2 - MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x2 - MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x90 - MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x90 - MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x90 - MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x90 - MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x90 - MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x90 - MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x16 - MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x16 - MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x16 - MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x16 - MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x16 - MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x16 - MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x10 - >; - }; - - pinctrl_flexspi0: flexspi0grp { - fsl,pins = < - MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 - MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 - MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 - MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 - MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 - MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c0 - MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c0 - >; - }; - - pinctrl_i2c1_gpio: i2c1gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x1e0 - MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x1e0 - >; - }; - - pinctrl_rtc: rtcgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0 - >; - }; - - pinctrl_sn65dsi83: sn65dsi83grp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x0 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x26 - >; - }; -}; diff --git a/arch/arm/dts/imx8mm-phygate-tauri-l.dts b/arch/arm/dts/imx8mm-phygate-tauri-l.dts deleted file mode 100644 index 968f475b9a9..00000000000 --- a/arch/arm/dts/imx8mm-phygate-tauri-l.dts +++ /dev/null @@ -1,489 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2023 PHYTEC Messtechnik GmbH - */ - -/dts-v1/; - -#include -#include -#include "imx8mm-phycore-som.dtsi" - -/ { - model = "PHYTEC phyGATE-Tauri-L-iMX8MM"; - compatible = "phytec,imx8mm-phygate-tauri-l", - "phytec,imx8mm-phycore-som", "fsl,imx8mm"; - - chosen { - stdout-path = &uart3; - }; - - can_osc_40m: clock-can { - compatible = "fixed-clock"; - clock-frequency = <40000000>; - clock-output-names = "can_osc_40m"; - #clock-cells = <0>; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpiokeys>; - - key { - gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - label = "KEY-A"; - linux,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds>; - - led-1 { - color = ; - gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "none"; - }; - - led-2 { - color = ; - gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "none"; - }; - }; - - usdhc1_pwrseq: pwr-seq { - compatible = "mmc-pwrseq-simple"; - post-power-on-delay-ms = <100>; - power-off-delay-us = <60>; - reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; - }; - - reg_usb_hub_vbus: regulator-hub-otg1 { - compatible = "regulator-fixed"; - gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbhubpwr>; - regulator-name = "usb_hub_vbus"; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - }; - - reg_usb_otg1_vbus: regulator-usb-otg1 { - compatible = "regulator-fixed"; - gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1pwr>; - regulator-name = "usb_otg1_vbus"; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - }; - - reg_usdhc2_vmmc: regulator-usdhc2 { - compatible = "regulator-fixed"; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - off-on-delay-us = <20000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "VSD_3V3"; - }; -}; - -&ecspi1 { - cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>, - <&gpio5 13 GPIO_ACTIVE_LOW>, - <&gpio5 2 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - /* CAN MCP251XFD */ - can0: can@0 { - compatible = "microchip,mcp251xfd"; - reg = <0>; - clocks = <&can_osc_40m>; - interrupts = <8 IRQ_TYPE_LEVEL_LOW>; - interrupt-parent = <&gpio1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can_int>; - spi-max-frequency = <10000000>; - }; - - tpm: tpm@1 { - compatible = "tcg,tpm_tis-spi"; - interrupts = <11 IRQ_TYPE_LEVEL_LOW>; - interrupt-parent = <&gpio2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tpm>; - reg = <1>; - spi-max-frequency = <38000000>; - }; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_gpio>; - scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - temp_sense0: temperature-sensor@49 { - compatible = "ti,tmp102"; - reg = <0x49>; - interrupt-parent = <&gpio4>; - interrupts = <31 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tempsense>; - #thermal-sensor-cells = <1>; - }; -}; - -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - pinctrl-1 = <&pinctrl_i2c3_gpio>; - scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; -}; - -&i2c4 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - pinctrl-1 = <&pinctrl_i2c4_gpio>; - scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; -}; - -/* PCIe */ -&pcie0 { - assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, - <&clk IMX8MM_CLK_PCIE1_PHY>, - <&clk IMX8MM_CLK_PCIE1_CTRL>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, - <&clk IMX8MM_SYS_PLL2_100M>, - <&clk IMX8MM_SYS_PLL2_250M>; - assigned-clock-rates = <10000000>, <100000000>, <250000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio3 22 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "okay"; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - status = "okay"; -}; - -/* RTC */ -&rv3028 { - trickle-resistor-ohms = <3000>; -}; - -&uart1 { - assigned-clocks = <&clk IMX8MM_CLK_UART1>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -/* UART2 - RS232 */ -&uart2 { - assigned-clocks = <&clk IMX8MM_CLK_UART2>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -/* UART - console */ -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -/* USB */ -&usbotg1 { - adp-disable; - dr_mode = "otg"; - over-current-active-low; - samsung,picophy-pre-emp-curr-control = <3>; - samsung,picophy-dc-vol-level-adjust = <7>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1>; - srp-disable; - vbus-supply = <®_usb_otg1_vbus>; - status = "okay"; -}; - -&usbotg2 { - disable-over-current; - dr_mode = "host"; - samsung,picophy-pre-emp-curr-control = <3>; - samsung,picophy-dc-vol-level-adjust = <7>; - vbus-supply = <®_usb_hub_vbus>; - status = "okay"; -}; - -/* SD-Card */ -&usdhc2 { - assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; - assigned-clock-rates = <200000000>; - bus-width = <4>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - disable-wp; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - vmmc-supply = <®_usdhc2_vmmc>; - vqmmc-supply = <®_nvcc_sd2>; - status = "okay"; -}; - -&iomuxc { - pinctrl_can_int: can-intgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x00 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 - MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 - MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 - >; - }; - - pinctrl_ecspi1_cs: ecspi1csgrp { - fsl,pins = < - MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x00 - MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x00 - MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x00 - >; - }; - - pinctrl_gpiokeys: keygrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x00 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c2 - MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c2 - >; - }; - - pinctrl_i2c2_gpio: i2c2gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1e0 - MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1e0 - >; - }; - - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c2 - MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c2 - >; - }; - - pinctrl_i2c3_gpio: i2c3gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1e0 - MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1e0 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c2 - MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c2 - >; - }; - - pinctrl_i2c4_gpio: i2c4gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x1e0 - MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x1e0 - >; - }; - - pinctrl_leds: leds1grp { - fsl,pins = < - MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x00 - MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x00 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - /* COEX2 */ - MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x00 - /* COEX1 */ - MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x12 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x40 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x40 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO15_PWM4_OUT 0x40 - >; - }; - - pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x40 - >; - }; - - pinctrl_tempsense: tempsensegrp { - fsl,pins = < - MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x00 - >; - }; - - pinctrl_tpm: tpmgrp { - fsl,pins = < - MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x140 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x00 - MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x00 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x00 - MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x00 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 - MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 - >; - }; - - pinctrl_usbhubpwr: usbhubpwrgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x00 - >; - }; - - pinctrl_usbotg1pwr: usbotg1pwrgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x00 - >; - }; - - pinctrl_usbotg1: usbotg1grp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x80 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x182 - MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0xc6 - MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc6 - MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc6 - MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc6 - MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc6 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x40 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x192 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d2 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d2 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d2 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d2 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d2 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - >; - }; -}; diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 23d9217fcc2..f81be42d5b0 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -296,6 +296,7 @@ config TARGET_PHYCORE_IMX8MM select IMX8MM select SUPPORT_SPL select IMX8M_LPDDR4 + imply OF_UPSTREAM config TARGET_PHYCORE_IMX8MP bool "PHYTEC PHYCORE i.MX8MP" diff --git a/board/phytec/phycore_imx8mm/MAINTAINERS b/board/phytec/phycore_imx8mm/MAINTAINERS index e46e3691bac..58c5e2d0af9 100644 --- a/board/phytec/phycore_imx8mm/MAINTAINERS +++ b/board/phytec/phycore_imx8mm/MAINTAINERS @@ -2,10 +2,7 @@ phyCORE-i.MX8M Mini M: Teresa Remmet W: https://www.phytec.eu/product-eu/system-on-modules/phycore-imx-8m-mini-nano/ S: Maintained -F: arch/arm/dts/imx8mm-phyboard-polis-rdk.dts -F: arch/arm/dts/imx8mm-phycore-som.dtsi F: arch/arm/dts/imx8mm-phyboard-polis-rdk-u-boot.dtsi -F: arch/arm/dts/imx8mm-phygate-tauri-l.dts F: arch/arm/dts/imx8mm-phygate-tauri-l-u-boot.dtsi F: board/phytec/phycore_imx8mm/ F: configs/imx8mm-phygate-tauri-l_defconfig diff --git a/configs/imx8mm-phygate-tauri-l_defconfig b/configs/imx8mm-phygate-tauri-l_defconfig index cb292dde4cb..41765f1ddc5 100644 --- a/configs/imx8mm-phygate-tauri-l_defconfig +++ b/configs/imx8mm-phygate-tauri-l_defconfig @@ -8,7 +8,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x3C0000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imx8mm-phygate-tauri-l" +CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mm-phygate-tauri-l" CONFIG_SPL_TEXT_BASE=0x7E1000 CONFIG_TARGET_PHYCORE_IMX8MM=y CONFIG_SYS_MONITOR_LEN=524288 diff --git a/configs/phycore-imx8mm_defconfig b/configs/phycore-imx8mm_defconfig index 22d419024f6..f9fd7255df7 100644 --- a/configs/phycore-imx8mm_defconfig +++ b/configs/phycore-imx8mm_defconfig @@ -9,7 +9,7 @@ CONFIG_SF_DEFAULT_SPEED=80000000 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x3C0000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imx8mm-phyboard-polis-rdk" +CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mm-phyboard-polis-rdk" CONFIG_SPL_TEXT_BASE=0x7E1000 CONFIG_TARGET_PHYCORE_IMX8MM=y CONFIG_SYS_MONITOR_LEN=524288 From patchwork Tue May 28 11:25:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yannic Moog X-Patchwork-Id: 1940418 X-Patchwork-Delegate: festevam@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=phytec.de header.i=@phytec.de header.a=rsa-sha256 header.s=a4 header.b=BXxbC3VI; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4VpVYW1lwQz20Pb for ; Tue, 28 May 2024 21:25:19 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 3E6C0884A0; Tue, 28 May 2024 13:25:10 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=phytec.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=phytec.de header.i=@phytec.de header.b="BXxbC3VI"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 353A288489; Tue, 28 May 2024 13:25:08 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED,RCVD_IN_VALIDITY_RPBL_BLOCKED, SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.2 Received: from mickerik.phytec.de (mickerik.phytec.de [91.26.50.163]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 9450E884A4 for ; Tue, 28 May 2024 13:25:03 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=phytec.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=Y.Moog@phytec.de DKIM-Signature: v=1; a=rsa-sha256; d=phytec.de; s=a4; c=relaxed/simple; q=dns/txt; i=@phytec.de; t=1716895503; x=1719487503; h=From:Sender:Reply-To:Subject:Date:Message-ID:To:CC:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=LldnNxqQg/pXPJq/RF0ON3vWc+APfDcLFLpUjIcC0xo=; b=BXxbC3VIiWFwCSDYHYAV9Y6iCc+V2xF/D0StVRsGd5chw76oJs5kKNA+SeVurgaU 2m9jLXGecxha4Z2byNuqQcu7757hMdpYvXEd0gKDTzX2OOwIetIqal+tKMbbsO1u Ow6l8M9lBCvwuPJrTnc7iRQQHLFsiERKxr2fg9FQpoo=; X-AuditID: ac14000a-03251700000021bc-7f-6655bf0fba13 Received: from berlix.phytec.de (Unknown_Domain [172.25.0.12]) (using TLS with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (Client did not present a certificate) by mickerik.phytec.de (PHYTEC Mail Gateway) with SMTP id C2.F7.08636.F0FB5566; Tue, 28 May 2024 13:25:03 +0200 (CEST) Received: from lws-moog.phytec.de (172.25.0.11) by Berlix.phytec.de (172.25.0.12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.6; Tue, 28 May 2024 13:25:03 +0200 From: Yannic Moog Date: Tue, 28 May 2024 13:25:00 +0200 Subject: [PATCH 2/2] arm: imx8mp-phycore: move to OF_UPSTREAM MIME-Version: 1.0 Message-ID: <20240528-phytec_imx8_of_upstream-v1-2-c884c1ddca5f@phytec.de> References: <20240528-phytec_imx8_of_upstream-v1-0-c884c1ddca5f@phytec.de> In-Reply-To: <20240528-phytec_imx8_of_upstream-v1-0-c884c1ddca5f@phytec.de> To: Teresa Remmet , Stefano Babic , Fabio Estevam , NXP i.MX U-Boot Team CC: , , Yannic Moog X-Mailer: b4 0.13.0 X-Originating-IP: [172.25.0.11] X-ClientProxiedBy: Berlix.phytec.de (172.25.0.12) To Berlix.phytec.de (172.25.0.12) X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrOLMWRmVeSWpSXmKPExsWyRpKBR5d/f2iawc6F0hYPr/pbtJ/ysXi7 t5PdYsrj9ewW3e/UHVg95s06weKxc9Zddo+zd3YwevR3t7B6bHy3gymANYrLJiU1J7MstUjf LoEr4+Jiw4Jnixkrjhz6wNjA+KCVsYuRk0NCwERiysldQDYXh5DAEiaJe70fWSGch4wS06e1 MoNUsQmoSDx+cY8VxGYRUJU4vGgBWFxYwFZix4GpYHFeAUGJkzOfsHQxcnAwC2hKrN+lDxJm FpCX2P52DjNEiZfEnUl9LCC2EJDdve8oWJxTwFviy7mn7CB7RQSmAe3dNZ8VojlC4trNJewQ lwpLnF8whQ2iWVbixfleqLi8xLRzr5kh7FCJrV+2M01gFJqF5KRZCCfNQnLSAkbmVYxCuZnJ 2alFmdl6BRmVJanJeimpmxhBgS/CwLWDsW+OxyFGJg7GQ4wSHMxKIrxnJoWmCfGmJFZWpRbl xxeV5qQWH2KU5mBREudd3RGcKiSQnliSmp2aWpBaBJNl4uCUamBs1blyb5FlllnMqfKNItVv 13ByTa31vlGx61qWx6+PhzV/XGDwenN2/63PtQlnyqc6vGGsPfBBKzO1/Jm/0UQZhgC1vblN nKeZjj1OWcXl0M4ttOJRdGbTeflDonX/JN8+ktGP71b5UptUbOQe9eZ7TNbtex/368afNJ0h mrz7Y1FZh8Oj57FKLMUZiYZazEXFiQCk4aq2agIAAA== X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The PHYCORE_IMX8MP is used by the phyBOARD-Pollux. Migrate board to OF_UPSTREAM. Linux kernel device tree for the board can be used as is, corresponding U-Boot device tree files are removed. U-Boot tweaks are kept unchanged. Signed-off-by: Yannic Moog Reviewed-by: Fabio Estevam Acked-by: Teresa Remmet --- arch/arm/dts/Makefile | 1 - arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts | 361 ---------------------------- arch/arm/dts/imx8mp-phycore-som.dtsi | 323 ------------------------- arch/arm/mach-imx/imx8m/Kconfig | 1 + board/phytec/phycore_imx8mp/MAINTAINERS | 1 - configs/phycore-imx8mp_defconfig | 2 +- 6 files changed, 2 insertions(+), 687 deletions(-) diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 480f8ff569d..d09d0d84bec 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1033,7 +1033,6 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mp-dhcom-pdk3-overlay-rev100.dtbo \ imx8mp-icore-mx8mp-edimm2.2.dtb \ imx8mp-msc-sm2s.dtb \ - imx8mp-phyboard-pollux-rdk.dtb \ imx8mq-pico-pi.dtb \ imx8mq-kontron-pitx-imx8m.dtb \ imx8mq-librem5-r4.dtb diff --git a/arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts b/arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts deleted file mode 100644 index c8640cac3ed..00000000000 --- a/arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts +++ /dev/null @@ -1,361 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2020 PHYTEC Messtechnik GmbH - * Author: Teresa Remmet - */ - -/dts-v1/; - -#include -#include -#include "imx8mp-phycore-som.dtsi" - -/ { - model = "PHYTEC phyBOARD-Pollux i.MX8MP"; - compatible = "phytec,imx8mp-phyboard-pollux-rdk", - "phytec,imx8mp-phycore-som", "fsl,imx8mp"; - - chosen { - stdout-path = &uart1; - }; - - reg_can1_stby: regulator-can1-stby { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1_reg>; - gpio = <&gpio3 20 GPIO_ACTIVE_LOW>; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "can1-stby"; - }; - - reg_can2_stby: regulator-can2-stby { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2_reg>; - gpio = <&gpio3 21 GPIO_ACTIVE_LOW>; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "can2-stby"; - }; - - reg_usb1_vbus: regulator-usb1-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1_vbus>; - gpio = <&gpio1 12 GPIO_ACTIVE_LOW>; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - regulator-name = "usb1_host_vbus"; - }; - - reg_usdhc2_vmmc: regulator-usdhc2 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - startup-delay-us = <100>; - off-on-delay-us = <12000>; - }; -}; - -&eqos { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eqos>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - status = "okay"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x1>; - ti,rx-internal-delay = ; - ti,tx-internal-delay = ; - ti,fifo-depth = ; - ti,clk-output-sel = ; - enet-phy-lane-no-swap; - }; - }; -}; - -/* CAN FD */ -&flexcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - xceiver-supply = <®_can1_stby>; - status = "okay"; -}; - -&flexcan2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - xceiver-supply = <®_can2_stby>; - status = "okay"; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_gpio>; - sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - }; - - leds@62 { - compatible = "nxp,pca9533"; - reg = <0x62>; - - led-1 { - type = ; - }; - - led-2 { - type = ; - }; - - led-3 { - type = ; - }; - }; -}; - -&snvs_pwrkey { - status = "okay"; -}; - -/* debug console */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -/* USB1 Host mode Type-A */ -&usb3_phy0 { - vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; - -&usb3_0 { - status = "okay"; -}; - -&usb_dwc3_0 { - dr_mode = "host"; - status = "okay"; -}; - -/* USB2 4-port USB3.0 HUB */ -&usb3_phy1 { - status = "okay"; -}; - -&usb3_1 { - fsl,permanently-attached; - fsl,disable-port-power-control; - status = "okay"; -}; - -&usb_dwc3_1 { - dr_mode = "host"; - status = "okay"; -}; - -/* RS232/RS485 */ -&uart2 { - assigned-clocks = <&clk IMX8MP_CLK_UART2>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - uart-has-rtscts; - status = "okay"; -}; - -/* SD-Card */ -&usdhc2 { - assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_pins>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_pins>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_pins>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_usdhc2_vmmc>; - bus-width = <4>; - status = "okay"; -}; - -&gpio1 { - gpio-line-names = "", "", "X_PMIC_WDOG_B", "", - "PMIC_SD_VSEL", "", "", "", "", "", - "", "", "USB1_OTG_PWR", "", "", "X_nETHPHY_INT"; -}; - -&gpio2 { - gpio-line-names = "", "", "", "", - "", "", "", "", "", "", - "", "", "X_SD2_CD_B", "", "", "", - "", "", "", "SD2_RESET_B"; -}; - -&gpio3 { - gpio-line-names = "", "", "", "", - "", "", "", "", "", "", - "", "", "", "", "", "", - "", "", "", "", "nCAN1_EN", "nCAN2_EN"; -}; - -&gpio4 { - gpio-line-names = "", "", "", "", - "", "", "", "", "", "", - "", "", "", "", "", "", - "", "", "X_PMIC_IRQ_B", "", "nENET0_INT_PWDN"; -}; - -&iomuxc { - pinctrl_eqos: eqosgrp { - fsl,pins = < - MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 - MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 - MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 - MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 - MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 - MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 - MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 - MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 - MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 - MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 - MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 - MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 - MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 - MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 - MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x10 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x154 - MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x154 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 - MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 - >; - }; - - pinctrl_flexcan1_reg: flexcan1reggrp { - fsl,pins = < - MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x154 - >; - }; - - pinctrl_flexcan2_reg: flexcan2reggrp { - fsl,pins = < - MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x154 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 - MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 - >; - }; - - pinctrl_i2c2_gpio: i2c2gpiogrp { - fsl,pins = < - MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1e2 - MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1e2 - >; - }; - - pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x40 - MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x40 - >; - }; - - pinctrl_usb1_vbus: usb1vbusgrp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x10 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 - MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 - MX8MP_IOMUXC_SAI3_RXC__UART2_DCE_CTS 0x140 - MX8MP_IOMUXC_SAI3_RXD__UART2_DCE_RTS 0x140 - >; - }; - - pinctrl_usdhc2_pins: usdhc2-gpiogrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 - >; - }; -}; diff --git a/arch/arm/dts/imx8mp-phycore-som.dtsi b/arch/arm/dts/imx8mp-phycore-som.dtsi deleted file mode 100644 index 79b290a002c..00000000000 --- a/arch/arm/dts/imx8mp-phycore-som.dtsi +++ /dev/null @@ -1,323 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2020 PHYTEC Messtechnik GmbH - * Author: Teresa Remmet - */ - -#include -#include "imx8mp.dtsi" - -/ { - model = "PHYTEC phyCORE-i.MX8MP"; - compatible = "phytec,imx8mp-phycore-som", "fsl,imx8mp"; - - aliases { - rtc0 = &rv3028; - rtc1 = &snvs_rtc; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0 0x80000000>; - }; -}; - -&A53_0 { - cpu-supply = <&buck2>; -}; - -&A53_1 { - cpu-supply = <&buck2>; -}; - -&A53_2 { - cpu-supply = <&buck2>; -}; - -&A53_3 { - cpu-supply = <&buck2>; -}; - -/* ethernet 1 */ -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy1>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy1: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - interrupt-parent = <&gpio1>; - interrupts = <15 IRQ_TYPE_EDGE_FALLING>; - ti,rx-internal-delay = ; - ti,tx-internal-delay = ; - ti,fifo-depth = ; - ti,clk-output-sel = ; - ti,min-output-impedance; - enet-phy-lane-no-swap; - }; - }; -}; - -&flexspi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexspi0>; - status = "okay"; - - som_flash: flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <80000000>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <4>; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - pmic: pmic@25 { - reg = <0x25>; - compatible = "nxp,pca9450c"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio4>; - interrupts = <18 IRQ_TYPE_LEVEL_LOW>; - - regulators { - buck1: BUCK1 { - regulator-compatible = "BUCK1"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <2187500>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; - }; - - buck2: BUCK2 { - regulator-compatible = "BUCK2"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <2187500>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; - nxp,dvs-run-voltage = <950000>; - nxp,dvs-standby-voltage = <850000>; - }; - - buck4: BUCK4 { - regulator-compatible = "BUCK4"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; - regulator-boot-on; - regulator-always-on; - }; - - buck5: BUCK5 { - regulator-compatible = "BUCK5"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; - regulator-boot-on; - regulator-always-on; - }; - - buck6: BUCK6 { - regulator-compatible = "BUCK6"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1: LDO1 { - regulator-compatible = "LDO1"; - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2: LDO2 { - regulator-compatible = "LDO2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3: LDO3 { - regulator-compatible = "LDO3"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo4: LDO4 { - regulator-compatible = "LDO4"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - }; - - ldo5: LDO5 { - regulator-compatible = "LDO5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; - - eeprom@51 { - compatible = "atmel,24c32"; - reg = <0x51>; - pagesize = <32>; - }; - - rv3028: rtc@52 { - compatible = "microcrystal,rv3028"; - reg = <0x52>; - trickle-resistor-ohms = <3000>; - }; -}; - -/* eMMC */ -&usdhc3 { - assigned-clocks = <&clk IMX8MP_CLK_USDHC3_ROOT>; - assigned-clock-rates = <400000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_fec: fecgrp { - fsl,pins = < - MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 - MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 - MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 - MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 - MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 - MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 - MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 - MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 - MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x12 - MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x12 - MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x14 - MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x14 - MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x14 - MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x14 - MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x11 - >; - }; - - pinctrl_flexspi0: flexspi0grp { - fsl,pins = < - MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 - MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 - MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 - MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 - MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 - MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 - MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 - >; - }; - - pinctrl_i2c1_gpio: i2c1gpiogrp { - fsl,pins = < - MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1e3 - MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1e3 - >; - }; - - pinctrl_pmic: pmicirqgrp { - fsl,pins = < - MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x141 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d2 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d2 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d2 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d2 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d2 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xe6 - >; - }; -}; diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index f81be42d5b0..046c78547b2 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -303,6 +303,7 @@ config TARGET_PHYCORE_IMX8MP select IMX8MP select SUPPORT_SPL select IMX8M_LPDDR4 + imply OF_UPSTREAM config TARGET_IMX8MM_CL_IOT_GATE bool "CompuLab iot-gate-imx8" diff --git a/board/phytec/phycore_imx8mp/MAINTAINERS b/board/phytec/phycore_imx8mp/MAINTAINERS index d3beb978d3a..645476ae30a 100644 --- a/board/phytec/phycore_imx8mp/MAINTAINERS +++ b/board/phytec/phycore_imx8mp/MAINTAINERS @@ -2,7 +2,6 @@ phyCORE-i.MX8M Plus M: Teresa Remmet W: https://www.phytec.eu/product-eu/system-on-modules/phycore-imx-8m-plus/ S: Maintained -F: arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts F: arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi F: board/phytec/phycore_imx8mp/ F: configs/phycore-imx8mp_defconfig diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig index e9a287cb441..6a59a27e3d4 100644 --- a/configs/phycore-imx8mp_defconfig +++ b/configs/phycore-imx8mp_defconfig @@ -9,7 +9,7 @@ CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x3C0000 CONFIG_SYS_I2C_MXC_I2C1=y CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imx8mp-phyboard-pollux-rdk" +CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mp-phyboard-pollux-rdk" CONFIG_SPL_TEXT_BASE=0x920000 CONFIG_TARGET_PHYCORE_IMX8MP=y CONFIG_PHYTEC_SOM_DETECTION=y