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CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(13230031)(35042699013)(82310400017)(1800799015)(376005)(36860700004); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 May 2024 09:29:54.6745 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8862cf3e-b673-4582-8143-08dc7a41bd46 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DB1PEPF000509EB.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: GV2PR08MB9422 X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FORGED_SPF_HELO, GIT_PATCH_0, KAM_LOTSOFHASH, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Hi All, This patch adds new alternatives to the patterns which are affected. The new alternatives with the conditional early clobbers are added before the normal ones in order for LRA to prefer them in the event that we have enough free registers to accommodate them. In case register pressure is too high the normal alternatives will be preferred before a reload is considered as we rather have the tie than a spill. Tests are in the next patch. Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. Ok for master? Thanks, Tamar gcc/ChangeLog: * config/aarch64/aarch64-sve.md (and3, @aarch64_pred__z, *3_cc, *3_ptest, aarch64_pred__z, *3_cc, *3_ptest, aarch64_pred__z, *3_cc, *3_ptest, @aarch64_pred_cmp, *cmp_cc, *cmp_ptest, @aarch64_pred_cmp_wide, *aarch64_pred_cmp_wide_cc, *aarch64_pred_cmp_wide_ptest, @aarch64_brk, *aarch64_brk_cc, *aarch64_brk_ptest, @aarch64_brk, *aarch64_brkn_cc, *aarch64_brkn_ptest, *aarch64_brk_cc, *aarch64_brk_ptest, aarch64_rdffr_z, *aarch64_rdffr_z_ptest, *aarch64_rdffr_ptest, *aarch64_rdffr_z_cc, *aarch64_rdffr_cc): Add new early clobber alternative. * config/aarch64/aarch64-sve2.md (@aarch64_pred_): Likewise. --- -- diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index e3085c0c636f1317409bbf3b5fbaf5342a2df1f6..8fdc1bc3cd43acfcd675a18350c297428c85fe46 100644 --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -1161,8 +1161,10 @@ (define_insn "aarch64_rdffr_z" (reg:VNx16BI FFRT_REGNUM) (match_operand:VNx16BI 1 "register_operand")))] "TARGET_SVE && TARGET_NON_STREAMING" - {@ [ cons: =0, 1 ] - [ Upa , Upa ] rdffr\t%0.b, %1/z + {@ [ cons: =0, 1 ; attrs: pred_clobber ] + [ &Upa , Upa; yes ] rdffr\t%0.b, %1/z + [ ?Upa , Upa; yes ] ^ + [ Upa , Upa; * ] ^ } ) @@ -1179,8 +1181,10 @@ (define_insn "*aarch64_rdffr_z_ptest" UNSPEC_PTEST)) (clobber (match_scratch:VNx16BI 0))] "TARGET_SVE && TARGET_NON_STREAMING" - {@ [ cons: =0, 1 ] - [ Upa , Upa ] rdffrs\t%0.b, %1/z + {@ [ cons: =0, 1 ; attrs: pred_clobber ] + [ &Upa , Upa; yes ] rdffrs\t%0.b, %1/z + [ ?Upa , Upa; yes ] ^ + [ Upa , Upa; * ] ^ } ) @@ -1195,8 +1199,10 @@ (define_insn "*aarch64_rdffr_ptest" UNSPEC_PTEST)) (clobber (match_scratch:VNx16BI 0))] "TARGET_SVE && TARGET_NON_STREAMING" - {@ [ cons: =0, 1 ] - [ Upa , Upa ] rdffrs\t%0.b, %1/z + {@ [ cons: =0, 1 ; attrs: pred_clobber ] + [ &Upa , Upa; yes ] rdffrs\t%0.b, %1/z + [ ?Upa , Upa; yes ] ^ + [ Upa , Upa; * ] ^ } ) @@ -1216,8 +1222,10 @@ (define_insn "*aarch64_rdffr_z_cc" (reg:VNx16BI FFRT_REGNUM) (match_dup 1)))] "TARGET_SVE && TARGET_NON_STREAMING" - {@ [ cons: =0, 1 ] - [ Upa , Upa ] rdffrs\t%0.b, %1/z + {@ [ cons: =0, 1 ; attrs: pred_clobber ] + [ &Upa , Upa; yes ] rdffrs\t%0.b, %1/z + [ ?Upa , Upa; yes ] ^ + [ Upa , Upa; * ] ^ } ) @@ -1233,8 +1241,10 @@ (define_insn "*aarch64_rdffr_cc" (set (match_operand:VNx16BI 0 "register_operand") (reg:VNx16BI FFRT_REGNUM))] "TARGET_SVE && TARGET_NON_STREAMING" - {@ [ cons: =0, 1 ] - [ Upa , Upa ] rdffrs\t%0.b, %1/z + {@ [ cons: =0, 1 ; attrs: pred_clobber ] + [ &Upa , Upa; yes ] rdffrs\t%0.b, %1/z + [ ?Upa , Upa; yes ] ^ + [ Upa , Upa; * ] ^ } ) @@ -6651,8 +6661,10 @@ (define_insn "and3" (and:PRED_ALL (match_operand:PRED_ALL 1 "register_operand") (match_operand:PRED_ALL 2 "register_operand")))] "TARGET_SVE" - {@ [ cons: =0, 1 , 2 ] - [ Upa , Upa, Upa ] and\t%0.b, %1/z, %2.b, %2.b + {@ [ cons: =0, 1 , 2 ; attrs: pred_clobber ] + [ &Upa , Upa, Upa; yes ] and\t%0.b, %1/z, %2.b, %2.b + [ ?Upa , Upa, Upa; yes ] ^ + [ Upa , Upa, Upa; * ] ^ } ) @@ -6679,8 +6691,10 @@ (define_insn "@aarch64_pred__z" (match_operand:PRED_ALL 3 "register_operand")) (match_operand:PRED_ALL 1 "register_operand")))] "TARGET_SVE" - {@ [ cons: =0, 1 , 2 , 3 ] - [ Upa , Upa, Upa, Upa ] \t%0.b, %1/z, %2.b, %3.b + {@ [ cons: =0, 1 , 2 , 3 ; attrs: pred_clobber ] + [ &Upa , Upa, Upa, Upa; yes ] \t%0.b, %1/z, %2.b, %3.b + [ ?Upa , Upa, Upa, Upa; yes ] ^ + [ Upa , Upa, Upa, Upa; * ] ^ } ) @@ -6703,8 +6717,10 @@ (define_insn "*3_cc" (and:PRED_ALL (LOGICAL:PRED_ALL (match_dup 2) (match_dup 3)) (match_dup 4)))] "TARGET_SVE" - {@ [ cons: =0, 1 , 2 , 3 ] - [ Upa , Upa, Upa, Upa ] s\t%0.b, %1/z, %2.b, %3.b + {@ [ cons: =0, 1 , 2 , 3 ; attrs: pred_clobber ] + [ &Upa , Upa, Upa, Upa; yes ] s\t%0.b, %1/z, %2.b, %3.b + [ ?Upa , Upa, Upa, Upa; yes ] ^ + [ Upa , Upa, Upa, Upa; * ] ^ } ) @@ -6723,8 +6739,10 @@ (define_insn "*3_ptest" UNSPEC_PTEST)) (clobber (match_scratch:VNx16BI 0))] "TARGET_SVE" - {@ [ cons: =0, 1 , 2 , 3 ] - [ Upa , Upa, Upa, Upa ] s\t%0.b, %1/z, %2.b, %3.b + {@ [ cons: =0, 1 , 2 , 3 ; attrs: pred_clobber ] + [ &Upa , Upa, Upa, Upa; yes ] s\t%0.b, %1/z, %2.b, %3.b + [ ?Upa , Upa, Upa, Upa; yes ] ^ + [ Upa , Upa, Upa, Upa; * ] ^ } ) @@ -6745,8 +6763,10 @@ (define_insn "aarch64_pred__z" (match_operand:PRED_ALL 2 "register_operand")) (match_operand:PRED_ALL 1 "register_operand")))] "TARGET_SVE" - {@ [ cons: =0, 1 , 2 , 3 ] - [ Upa , Upa, Upa, Upa ] \t%0.b, %1/z, %2.b, %3.b + {@ [ cons: =0, 1 , 2 , 3 ; attrs: pred_clobber ] + [ &Upa , Upa, Upa, Upa; yes ] \t%0.b, %1/z, %2.b, %3.b + [ ?Upa , Upa, Upa, Upa; yes ] ^ + [ Upa , Upa, Upa, Upa; * ] ^ } ) @@ -6770,8 +6790,10 @@ (define_insn "*3_cc" (match_dup 2)) (match_dup 4)))] "TARGET_SVE" - {@ [ cons: =0, 1 , 2 , 3 ] - [ Upa , Upa, Upa, Upa ] s\t%0.b, %1/z, %2.b, %3.b + {@ [ cons: =0, 1 , 2 , 3 ; attrs: pred_clobber ] + [ &Upa , Upa, Upa, Upa; yes ] s\t%0.b, %1/z, %2.b, %3.b + [ ?Upa , Upa, Upa, Upa; yes ] ^ + [ Upa , Upa, Upa, Upa; * ] ^ } ) @@ -6791,8 +6813,10 @@ (define_insn "*3_ptest" UNSPEC_PTEST)) (clobber (match_scratch:VNx16BI 0))] "TARGET_SVE" - {@ [ cons: =0, 1 , 2 , 3 ] - [ Upa , Upa, Upa, Upa ] s\t%0.b, %1/z, %2.b, %3.b + {@ [ cons: =0, 1 , 2 , 3 ; attrs: pred_clobber ] + [ &Upa , Upa, Upa, Upa; yes ] s\t%0.b, %1/z, %2.b, %3.b + [ ?Upa , Upa, Upa, Upa; yes ] ^ + [ Upa , Upa, Upa, Upa; * ] ^ } ) @@ -6813,8 +6837,10 @@ (define_insn "aarch64_pred__z" (not:PRED_ALL (match_operand:PRED_ALL 3 "register_operand"))) (match_operand:PRED_ALL 1 "register_operand")))] "TARGET_SVE" - {@ [ cons: =0, 1 , 2 , 3 ] - [ Upa , Upa, Upa, Upa ] \t%0.b, %1/z, %2.b, %3.b + {@ [ cons: =0, 1 , 2 , 3 ; attrs: pred_clobber ] + [ &Upa , Upa, Upa, Upa; yes ] \t%0.b, %1/z, %2.b, %3.b + [ ?Upa , Upa, Upa, Upa; yes ] ^ + [ Upa , Upa, Upa, Upa; * ] ^ } ) @@ -6839,8 +6865,10 @@ (define_insn "*3_cc" (not:PRED_ALL (match_dup 3))) (match_dup 4)))] "TARGET_SVE" - {@ [ cons: =0, 1 , 2 , 3 ] - [ Upa , Upa, Upa, Upa ] s\t%0.b, %1/z, %2.b, %3.b + {@ [ cons: =0, 1 , 2 , 3 ; attrs: pred_clobber ] + [ &Upa , Upa, Upa, Upa; yes ] s\t%0.b, %1/z, %2.b, %3.b + [ ?Upa , Upa, Upa, Upa; yes ] ^ + [ Upa , Upa, Upa, Upa; * ] ^ } ) @@ -6861,8 +6889,10 @@ (define_insn "*3_ptest" UNSPEC_PTEST)) (clobber (match_scratch:VNx16BI 0))] "TARGET_SVE" - {@ [ cons: =0, 1 , 2 , 3 ] - [ Upa , Upa, Upa, Upa ] s\t%0.b, %1/z, %2.b, %3.b + {@ [ cons: =0, 1 , 2 , 3 ; attrs: pred_clobber ] + [ &Upa , Upa, Upa, Upa; yes ] s\t%0.b, %1/z, %2.b, %3.b + [ ?Upa , Upa, Upa, Upa; yes ] ^ + [ Upa , Upa, Upa, Upa; * ] ^ } ) @@ -8104,9 +8134,13 @@ (define_insn "@aarch64_pred_cmp" UNSPEC_PRED_Z)) (clobber (reg:CC_NZC CC_REGNUM))] "TARGET_SVE" - {@ [ cons: =0 , 1 , 3 , 4 ] - [ Upa , Upl , w , ] cmp\t%0., %1/z, %3., #%4 - [ Upa , Upl , w , w ] cmp\t%0., %1/z, %3., %4. + {@ [ cons: =0 , 1 , 3 , 4 ; attrs: pred_clobber ] + [ &Upa , Upl , w , ; yes ] cmp\t%0., %1/z, %3., #%4 + [ ?Upa , Upl , w , ; yes ] ^ + [ Upa , Upl , w , ; * ] ^ + [ &Upa , Upl , w , w ; yes ] cmp\t%0., %1/z, %3., %4. + [ ?Upa , Upl , w , w ; yes ] ^ + [ Upa , Upl , w , w ; * ] ^ } ) @@ -8136,9 +8170,13 @@ (define_insn_and_rewrite "*cmp_cc" UNSPEC_PRED_Z))] "TARGET_SVE && aarch64_sve_same_pred_for_ptest_p (&operands[4], &operands[6])" - {@ [ cons: =0 , 1 , 2 , 3 ] - [ Upa , Upl , w , ] cmp\t%0., %1/z, %2., #%3 - [ Upa , Upl , w , w ] cmp\t%0., %1/z, %2., %3. + {@ [ cons: =0 , 1 , 2 , 3 ; attrs: pred_clobber ] + [ &Upa , Upl , w , ; yes ] cmp\t%0., %1/z, %2., #%3 + [ ?Upa , Upl , w , ; yes ] ^ + [ Upa , Upl , w , ; * ] ^ + [ &Upa , Upl , w , w ; yes ] cmp\t%0., %1/z, %2., %3. + [ ?Upa , Upl , w , w ; yes ] ^ + [ Upa , Upl , w , w ; * ] ^ } "&& !rtx_equal_p (operands[4], operands[6])" { @@ -8166,9 +8204,13 @@ (define_insn_and_rewrite "*cmp_ptest" (clobber (match_scratch: 0))] "TARGET_SVE && aarch64_sve_same_pred_for_ptest_p (&operands[4], &operands[6])" - {@ [ cons: =0, 1 , 2 , 3 ] - [ Upa , Upl, w , ] cmp\t%0., %1/z, %2., #%3 - [ Upa , Upl, w , w ] cmp\t%0., %1/z, %2., %3. + {@ [ cons: =0, 1 , 2 , 3 ; attrs: pred_clobber ] + [ &Upa , Upl, w , ; yes ] cmp\t%0., %1/z, %2., #%3 + [ ?Upa , Upl, w , ; yes ] ^ + [ Upa , Upl, w , ; * ] ^ + [ &Upa , Upl, w , w ; yes ] cmp\t%0., %1/z, %2., %3. + [ ?Upa , Upl, w , w ; yes ] ^ + [ Upa , Upl, w , w ; * ] ^ } "&& !rtx_equal_p (operands[4], operands[6])" { @@ -8221,8 +8263,10 @@ (define_insn "@aarch64_pred_cmp_wide" UNSPEC_PRED_Z)) (clobber (reg:CC_NZC CC_REGNUM))] "TARGET_SVE" - {@ [ cons: =0, 1 , 2, 3, 4 ] - [ Upa , Upl, , w, w ] cmp\t%0., %1/z, %3., %4.d + {@ [ cons: =0, 1 , 2, 3, 4; attrs: pred_clobber ] + [ &Upa , Upl, , w, w; yes ] cmp\t%0., %1/z, %3., %4.d + [ ?Upa , Upl, , w, w; yes ] ^ + [ Upa , Upl, , w, w; * ] ^ } ) @@ -8254,8 +8298,10 @@ (define_insn "*aarch64_pred_cmp_wide_cc" UNSPEC_PRED_Z))] "TARGET_SVE && aarch64_sve_same_pred_for_ptest_p (&operands[4], &operands[6])" - {@ [ cons: =0, 1 , 2, 3, 6 ] - [ Upa , Upl, w, w, Upl ] cmp\t%0., %1/z, %2., %3.d + {@ [ cons: =0, 1 , 2, 3, 6 ; attrs: pred_clobber ] + [ &Upa , Upl, w, w, Upl; yes ] cmp\t%0., %1/z, %2., %3.d + [ ?Upa , Upl, w, w, Upl; yes ] ^ + [ Upa , Upl, w, w, Upl; * ] ^ } ) @@ -8279,8 +8325,10 @@ (define_insn "*aarch64_pred_cmp_wide_ptest" (clobber (match_scratch: 0))] "TARGET_SVE && aarch64_sve_same_pred_for_ptest_p (&operands[4], &operands[6])" - {@ [ cons: =0, 1 , 2, 3, 6 ] - [ Upa , Upl, w, w, Upl ] cmp\t%0., %1/z, %2., %3.d + {@ [ cons: =0, 1 , 2, 3, 6 ; attrs: pred_clobber ] + [ &Upa , Upl, w, w, Upl; yes ] cmp\t%0., %1/z, %2., %3.d + [ ?Upa , Upl, w, w, Upl; yes ] ^ + [ Upa , Upl, w, w, Upl; * ] ^ } ) @@ -9948,9 +9996,13 @@ (define_insn "@aarch64_brk" (match_operand:VNx16BI 3 "aarch64_simd_reg_or_zero")] SVE_BRK_UNARY))] "TARGET_SVE" - {@ [ cons: =0 , 1 , 2 , 3 ] - [ Upa , Upa , Upa , Dz ] brk\t%0.b, %1/z, %2.b - [ Upa , Upa , Upa , 0 ] brk\t%0.b, %1/m, %2.b + {@ [ cons: =0 , 1 , 2 , 3 ; attrs: pred_clobber ] + [ &Upa , Upa , Upa , Dz; yes ] brk\t%0.b, %1/z, %2.b + [ ?Upa , Upa , Upa , Dz; yes ] ^ + [ Upa , Upa , Upa , Dz; * ] ^ + [ &Upa , Upa , Upa , 0 ; yes ] brk\t%0.b, %1/m, %2.b + [ ?Upa , Upa , Upa , 0 ; yes ] ^ + [ Upa , Upa , Upa , 0 ; * ] ^ } ) @@ -9974,8 +10026,10 @@ (define_insn "*aarch64_brk_cc" (match_dup 3)] SVE_BRK_UNARY))] "TARGET_SVE" - {@ [ cons: =0, 1 , 2 ] - [ Upa , Upa, Upa ] brks\t%0.b, %1/z, %2.b + {@ [ cons: =0, 1 , 2 ; attrs: pred_clobber ] + [ &Upa , Upa, Upa; yes ] brks\t%0.b, %1/z, %2.b + [ ?Upa , Upa, Upa; yes ] ^ + [ Upa , Upa, Upa; * ] ^ } ) @@ -9994,8 +10048,10 @@ (define_insn "*aarch64_brk_ptest" UNSPEC_PTEST)) (clobber (match_scratch:VNx16BI 0))] "TARGET_SVE" - {@ [ cons: =0, 1 , 2 ] - [ Upa , Upa, Upa ] brks\t%0.b, %1/z, %2.b + {@ [ cons: =0, 1 , 2 ; attrs: pred_clobber ] + [ &Upa , Upa, Upa; yes ] brks\t%0.b, %1/z, %2.b + [ ?Upa , Upa, Upa; yes ] ^ + [ Upa , Upa, Upa; * ] ^ } ) @@ -10020,8 +10076,10 @@ (define_insn "@aarch64_brk" (match_operand:VNx16BI 3 "register_operand")] SVE_BRK_BINARY))] "TARGET_SVE" - {@ [ cons: =0, 1 , 2 , 3 ] - [ Upa , Upa, Upa, ] brk\t%0.b, %1/z, %2.b, %.b + {@ [ cons: =0, 1 , 2 , 3 ; attrs: pred_clobber ] + [ &Upa , Upa, Upa, ; yes ] brk\t%0.b, %1/z, %2.b, %.b + [ ?Upa , Upa, Upa, ; yes ] ^ + [ Upa , Upa, Upa, ; * ] ^ } ) @@ -10046,8 +10104,10 @@ (define_insn_and_rewrite "*aarch64_brkn_cc" (match_dup 3)] UNSPEC_BRKN))] "TARGET_SVE" - {@ [ cons: =0, 1 , 2 , 3 ] - [ Upa , Upa, Upa, 0 ] brkns\t%0.b, %1/z, %2.b, %0.b + {@ [ cons: =0, 1 , 2 , 3; attrs: pred_clobber ] + [ &Upa , Upa, Upa, 0; yes ] brkns\t%0.b, %1/z, %2.b, %0.b + [ ?Upa , Upa, Upa, 0; yes ] ^ + [ Upa , Upa, Upa, 0; * ] ^ } "&& (operands[4] != CONST0_RTX (VNx16BImode) || operands[5] != CONST0_RTX (VNx16BImode))" @@ -10072,8 +10132,10 @@ (define_insn_and_rewrite "*aarch64_brkn_ptest" UNSPEC_PTEST)) (clobber (match_scratch:VNx16BI 0))] "TARGET_SVE" - {@ [ cons: =0, 1 , 2 , 3 ] - [ Upa , Upa, Upa, 0 ] brkns\t%0.b, %1/z, %2.b, %0.b + {@ [ cons: =0, 1 , 2 , 3; attrs: pred_clobber ] + [ &Upa , Upa, Upa, 0; yes ] brkns\t%0.b, %1/z, %2.b, %0.b + [ ?Upa , Upa, Upa, 0; yes ] ^ + [ Upa , Upa, Upa, 0; * ] ^ } "&& (operands[4] != CONST0_RTX (VNx16BImode) || operands[5] != CONST0_RTX (VNx16BImode))" @@ -10103,8 +10165,10 @@ (define_insn "*aarch64_brk_cc" (match_dup 3)] SVE_BRKP))] "TARGET_SVE" - {@ [ cons: =0, 1 , 2 , 3 ] - [ Upa , Upa, Upa, Upa ] brks\t%0.b, %1/z, %2.b, %3.b + {@ [ cons: =0, 1 , 2 , 3 , 4; attrs: pred_clobber ] + [ &Upa , Upa, Upa, Upa, ; yes ] brks\t%0.b, %1/z, %2.b, %3.b + [ ?Upa , Upa, Upa, Upa, ; yes ] ^ + [ Upa , Upa, Upa, Upa, ; * ] ^ } ) @@ -10123,8 +10187,10 @@ (define_insn "*aarch64_brk_ptest" UNSPEC_PTEST)) (clobber (match_scratch:VNx16BI 0))] "TARGET_SVE" - {@ [ cons: =0, 1 , 2 , 3 ] - [ Upa , Upa, Upa, Upa ] brks\t%0.b, %1/z, %2.b, %3.b + {@ [ cons: =0, 1 , 2 , 3 ; attrs: pred_clobber ] + [ &Upa , Upa, Upa, Upa; yes ] brks\t%0.b, %1/z, %2.b, %3.b + [ ?Upa , Upa, Upa, Upa; yes ] ^ + [ Upa , Upa, Upa, Upa; * ] ^ } ) diff --git a/gcc/config/aarch64/aarch64-sve2.md b/gcc/config/aarch64/aarch64-sve2.md index aa12baf48355358ca4fefe88157df3aac6eb09bd..1a49494a69d8335e5f7d3ef4bd3a90d0805bba84 100644 --- a/gcc/config/aarch64/aarch64-sve2.md +++ b/gcc/config/aarch64/aarch64-sve2.md @@ -3349,8 +3349,10 @@ (define_insn "@aarch64_pred_" UNSPEC_PRED_Z)) (clobber (reg:CC_NZC CC_REGNUM))] "TARGET_SVE2 && TARGET_NON_STREAMING" - {@ [ cons: =0, 1 , 2, 3, 4 ] - [ Upa , Upl, , w, w ] \t%0., %1/z, %3., %4. + {@ [ cons: =0, 1 , 2, 3, 4; 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CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(13230031)(376005)(36860700004)(35042699013)(1800799015)(82310400017); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 May 2024 09:30:18.1193 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a88e48f0-e229-4068-e70c-08dc7a41cb3f X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DB1PEPF000509F6.eurprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU2PR08MB10037 X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FORGED_SPF_HELO, GIT_PATCH_0, KAM_LOTSOFHASH, KAM_SHORT, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Hi All, This enables the new tuning flag for Neoverse V1, Neoverse V2 and Neoverse N2. It is kept off for generic codegen. Note the reason for the +sve even though they are in aarch64-sve.exp is if the testsuite is ran with a forced SVE off option, e.g. -march=armv8-a+nosve then the intrinsics end up being disabled because the -march is preferred over the -mcpu even though the -mcpu comes later. This prevents the tests from failing in such runs. Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. Ok for master? Thanks, Tamar gcc/ChangeLog: * config/aarch64/tuning_models/neoversen2.h (neoversen2_tunings): Add AARCH64_EXTRA_TUNE_AVOID_PRED_RMW. * config/aarch64/tuning_models/neoversev1.h (neoversev1_tunings): Add AARCH64_EXTRA_TUNE_AVOID_PRED_RMW. * config/aarch64/tuning_models/neoversev2.h (neoversev2_tunings): Add AARCH64_EXTRA_TUNE_AVOID_PRED_RMW. gcc/testsuite/ChangeLog: * gcc.target/aarch64/sve/pred_clobber_1.c: New test. * gcc.target/aarch64/sve/pred_clobber_2.c: New test. * gcc.target/aarch64/sve/pred_clobber_3.c: New test. * gcc.target/aarch64/sve/pred_clobber_4.c: New test. * gcc.target/aarch64/sve/pred_clobber_5.c: New test. --- -- diff --git a/gcc/config/aarch64/tuning_models/neoversen2.h b/gcc/config/aarch64/tuning_models/neoversen2.h index 7e799bbe762fe862e31befed50e54040a7fd1f2f..be9a48ac3adc097f967c217fe09dcac194d7d14f 100644 --- a/gcc/config/aarch64/tuning_models/neoversen2.h +++ b/gcc/config/aarch64/tuning_models/neoversen2.h @@ -236,7 +236,8 @@ static const struct tune_params neoversen2_tunings = (AARCH64_EXTRA_TUNE_CHEAP_SHIFT_EXTEND | AARCH64_EXTRA_TUNE_CSE_SVE_VL_CONSTANTS | AARCH64_EXTRA_TUNE_USE_NEW_VECTOR_COSTS - | AARCH64_EXTRA_TUNE_MATCHED_VECTOR_THROUGHPUT), /* tune_flags. */ + | AARCH64_EXTRA_TUNE_MATCHED_VECTOR_THROUGHPUT + | AARCH64_EXTRA_TUNE_AVOID_PRED_RMW), /* tune_flags. */ &generic_prefetch_tune, AARCH64_LDP_STP_POLICY_ALWAYS, /* ldp_policy_model. */ AARCH64_LDP_STP_POLICY_ALWAYS /* stp_policy_model. */ diff --git a/gcc/config/aarch64/tuning_models/neoversev1.h b/gcc/config/aarch64/tuning_models/neoversev1.h index 9363f2ad98a5279cc99f2f9b1509ba921d582e84..0fc41ce6a41b3135fa06d2bda1f517fdf4f8dbcf 100644 --- a/gcc/config/aarch64/tuning_models/neoversev1.h +++ b/gcc/config/aarch64/tuning_models/neoversev1.h @@ -227,7 +227,8 @@ static const struct tune_params neoversev1_tunings = (AARCH64_EXTRA_TUNE_CSE_SVE_VL_CONSTANTS | AARCH64_EXTRA_TUNE_USE_NEW_VECTOR_COSTS | AARCH64_EXTRA_TUNE_MATCHED_VECTOR_THROUGHPUT - | AARCH64_EXTRA_TUNE_CHEAP_SHIFT_EXTEND), /* tune_flags. */ + | AARCH64_EXTRA_TUNE_CHEAP_SHIFT_EXTEND + | AARCH64_EXTRA_TUNE_AVOID_PRED_RMW), /* tune_flags. */ &generic_prefetch_tune, AARCH64_LDP_STP_POLICY_ALWAYS, /* ldp_policy_model. */ AARCH64_LDP_STP_POLICY_ALWAYS /* stp_policy_model. */ diff --git a/gcc/config/aarch64/tuning_models/neoversev2.h b/gcc/config/aarch64/tuning_models/neoversev2.h index bc01ed767c9b690504eb98456402df5d9d64eee3..f76e4ef358f7dfb9c7d7b470ea7240eaa2120f8e 100644 --- a/gcc/config/aarch64/tuning_models/neoversev2.h +++ b/gcc/config/aarch64/tuning_models/neoversev2.h @@ -236,7 +236,8 @@ static const struct tune_params neoversev2_tunings = (AARCH64_EXTRA_TUNE_CHEAP_SHIFT_EXTEND | AARCH64_EXTRA_TUNE_CSE_SVE_VL_CONSTANTS | AARCH64_EXTRA_TUNE_USE_NEW_VECTOR_COSTS - | AARCH64_EXTRA_TUNE_MATCHED_VECTOR_THROUGHPUT), /* tune_flags. */ + | AARCH64_EXTRA_TUNE_MATCHED_VECTOR_THROUGHPUT + | AARCH64_EXTRA_TUNE_AVOID_PRED_RMW), /* tune_flags. */ &generic_prefetch_tune, AARCH64_LDP_STP_POLICY_ALWAYS, /* ldp_policy_model. */ AARCH64_LDP_STP_POLICY_ALWAYS /* stp_policy_model. */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pred_clobber_1.c b/gcc/testsuite/gcc.target/aarch64/sve/pred_clobber_1.c new file mode 100644 index 0000000000000000000000000000000000000000..934a00a38531c5fd4139d99ff33414904b2c104f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/pred_clobber_1.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mcpu=neoverse-n2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#pragma GCC target "+sve" + +#include + +extern void use(svbool_t); + +/* +** foo: +** ... +** ptrue p([1-9][0-9]?).b, all +** cmplo p0.h, p\1/z, z0.h, z[0-9]+.h +** ... +*/ +void foo (svuint16_t a, uint16_t b) +{ + svbool_t p0 = svcmplt_n_u16 (svptrue_b16 (), a, b); + use (p0); +} diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pred_clobber_2.c b/gcc/testsuite/gcc.target/aarch64/sve/pred_clobber_2.c new file mode 100644 index 0000000000000000000000000000000000000000..58badb66a43b1ac50eeec153b9cac44fc831b145 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/pred_clobber_2.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mcpu=neoverse-v2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#pragma GCC target "+sve" + +#include + +extern void use(svbool_t); + +/* +** foo: +** ... +** ptrue p([1-9][0-9]?).b, all +** cmplo p0.h, p\1/z, z0.h, z[0-9]+.h +** ... +*/ +void foo (svuint16_t a, uint16_t b) +{ + svbool_t p0 = svcmplt_n_u16 (svptrue_b16 (), a, b); + use (p0); +} diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pred_clobber_3.c b/gcc/testsuite/gcc.target/aarch64/sve/pred_clobber_3.c new file mode 100644 index 0000000000000000000000000000000000000000..c67c2bd3422e0bb0c694b5fe0adf0d83e4d967c6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/pred_clobber_3.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mcpu=neoverse-v1" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#pragma GCC target "+sve" + +#include + +extern void use(svbool_t); + +/* +** foo: +** ... +** ptrue p([1-9][0-9]?).b, all +** cmplo p0.h, p\1/z, z0.h, z[0-9]+.h +** ... +*/ +void foo (svuint16_t a, uint16_t b) +{ + svbool_t p0 = svcmplt_n_u16 (svptrue_b16 (), a, b); + use (p0); +} + diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pred_clobber_4.c b/gcc/testsuite/gcc.target/aarch64/sve/pred_clobber_4.c new file mode 100644 index 0000000000000000000000000000000000000000..c0120afe5d523eff8297fadd4fc4c678676413d6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/pred_clobber_4.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#pragma GCC target "+sve" + +#include + +extern void use(svbool_t); + +/* +** foo: +** ... +** ptrue p0.b, all +** cmplo p0.h, p0/z, z0.h, z[0-9]+.h +** ... +*/ +void foo (svuint16_t a, uint16_t b) +{ + svbool_t p0 = svcmplt_n_u16 (svptrue_b16 (), a, b); + use (p0); +} diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pred_clobber_5.c b/gcc/testsuite/gcc.target/aarch64/sve/pred_clobber_5.c new file mode 100644 index 0000000000000000000000000000000000000000..63f0669abd23d45c0ffd77c53859a098a21e0192 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/pred_clobber_5.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mcpu=neoverse-n2 -ffixed-p1 -ffixed-p2 -ffixed-p3 -ffixed-p4 -ffixed-p5 -ffixed-p6 -ffixed-p7 -ffixed-p8 -ffixed-p9 -ffixed-p10 -ffixed-p11 -ffixed-p12 -ffixed-p12 -ffixed-p13 -ffixed-p14 -ffixed-p15" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#pragma GCC target "+sve" + +#include + +extern void use(svbool_t); + +/* +** foo: +** ... +** ptrue p0.b, all +** cmplo p0.h, p0/z, z0.h, z[0-9]+.h +** ... +*/ +void foo (svuint16_t a, uint16_t b) +{ + svbool_t p0 = svcmplt_n_u16 (svptrue_b16 (), a, b); + use (p0); +}