From patchwork Fri May 17 05:26:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Meng, Tingting" X-Patchwork-Id: 1936424 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=MKVnN482; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4VgmzQ3Dlbz1yfq for ; Fri, 17 May 2024 22:50:58 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 82B3388496; Fri, 17 May 2024 14:50:43 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="MKVnN482"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 9664B88491; Fri, 17 May 2024 07:27:39 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-3.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 112BD882D9 for ; Fri, 17 May 2024 07:27:36 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=tingting.meng@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1715923657; x=1747459657; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=kS5WEPKBMPi3jyjTEBadxfZNfAHl5+3GPJAo4n+R58s=; b=MKVnN482jTiBAyOT046j0dYmmKSED0Mk60G4Bf8ULs7ga7wgFgOQCYgs 1BVbAUAD2uTXep/9X3jAGDEbi2r/Lf41CvR7+/cQpA1Htgb5PDoTLGmEI inXJuwlO55Lg8z2zD1kq/5SqlrRWrGp8B3RuZyPtXtcdJFKd77EFF1tJU tYR+c9F2zRUy3Q6am8nArImEkBsgdK/2mp9sztTUb1bDL8m9Z10SgDgCN NKR8f5XQLoCRsgt3o43frwI+boHmtK3J6mYmpcuOqTT3HZwKnhCxBMFRP Qf6E7hISeU+jzKsQDoBrUzHFqjcx+siw8XyiLx6zwbV9OTc/yKy1EbReS A==; X-CSE-ConnectionGUID: BY+4cJFyR/SDO6+skzFbJg== X-CSE-MsgGUID: 7tZNiHYmRLaSWzhuhk9aSA== X-IronPort-AV: E=McAfee;i="6600,9927,11074"; a="11929925" X-IronPort-AV: E=Sophos;i="6.08,166,1712646000"; d="scan'208";a="11929925" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 May 2024 22:27:34 -0700 X-CSE-ConnectionGUID: oO+w8iW4TbOJsOTo7c0VnA== X-CSE-MsgGUID: 4E4bZKq2QamiVaLm1/wWyA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,166,1712646000"; d="scan'208";a="36188217" Received: from pglc00543.png.intel.com ([10.221.239.235]) by fmviesa003.fm.intel.com with ESMTP; 16 May 2024 22:27:30 -0700 From: tingting.meng@intel.com To: u-boot@lists.denx.de Cc: Lukasz Majewski , Sean Anderson , Rayagonda Kokatanur , Tom Rini , Marek , Simon , Tien Fong , Kok Kiang , Dinesh , Boon Khai , Alif , Teik Heng , Hazim , Jit Loon Lim , Sieu Mun Tang , Wan Yee Lau , Tingting Meng Subject: [Agilex7 M-series Platform Enablement v1 01/16] arch: arm: dts: Add dts and dtsi for new platform Agilex7 M-series Date: Fri, 17 May 2024 13:26:46 +0800 Message-Id: <20240517052701.12949-2-tingting.meng@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240517052701.12949-1-tingting.meng@intel.com> References: <20240517052701.12949-1-tingting.meng@intel.com> MIME-Version: 1.0 X-Mailman-Approved-At: Fri, 17 May 2024 14:50:41 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Wan Yee Lau Add Agilex7 M-series dtsi and dts for new platform Agilex7 M-series. Signed-off-by: Wan Yee Lau Signed-off-by: Teik Heng Chong Signed-off-by: Tingting Meng --- ...tsi => socfpga_agilex7m_socdk-u-boot.dtsi} | 37 ++++- ...x_socdk.dts => socfpga_agilex7m_socdk.dts} | 66 +++++++-- arch/arm/dts/socfpga_soc64_u-boot.dtsi | 127 ++++++++++++++++++ 3 files changed, 213 insertions(+), 17 deletions(-) copy arch/arm/dts/{socfpga_agilex_socdk-u-boot.dtsi => socfpga_agilex7m_socdk-u-boot.dtsi} (50%) copy arch/arm/dts/{socfpga_agilex_socdk.dts => socfpga_agilex7m_socdk.dts} (63%) create mode 100644 arch/arm/dts/socfpga_soc64_u-boot.dtsi diff --git a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex7m_socdk-u-boot.dtsi similarity index 50% copy from arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi copy to arch/arm/dts/socfpga_agilex7m_socdk-u-boot.dtsi index 63df28e836..4369f0b545 100644 --- a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex7m_socdk-u-boot.dtsi @@ -2,12 +2,18 @@ /* * U-Boot additions * - * Copyright (C) 2019-2022 Intel Corporation + * Copyright (C) 2024 Intel Corporation */ #include "socfpga_agilex-u-boot.dtsi" +#include "socfpga_soc64_u-boot.dtsi" /{ + chosen { + stdout-path = "serial0:115200n8"; + u-boot,spl-boot-order = &mmc; + }; + aliases { spi0 = &qspi; i2c0 = &i2c1; @@ -23,9 +29,7 @@ }; memory { - /* 8GB */ - reg = <0 0x00000000 0 0x80000000>, - <2 0x80000000 1 0x80000000>; + reg = <0 0x00000000 0 0x80000000>; }; }; @@ -34,22 +38,43 @@ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; bootph-all; + /delete-property/ cdns,read-delay; }; &i2c1 { status = "okay"; }; +&nand { + status = "okay"; + nand-bus-width = <16>; + bootph-all; +}; + &mmc { drvsel = <3>; smplsel = <0>; bootph-all; }; -&qspi { - status = "okay"; +&sdr { + compatible = "intel,sdr-ctl-agilex7m"; + + reg = <0xf8020000 0x100>; +}; + +&socfpga_l3interconnect_firewall { + soc_noc_fw_mpfe_csr_inst_0_mpfe_scr@f8020000 { + intel,offset-settings = + /* Disable MPFE firewall for SMMU */ + <0x00000000 0x00010101 0x00010101>; + }; }; &watchdog0 { bootph-all; }; + +&binman { + /delete-node/ kernel; +}; diff --git a/arch/arm/dts/socfpga_agilex_socdk.dts b/arch/arm/dts/socfpga_agilex7m_socdk.dts similarity index 63% copy from arch/arm/dts/socfpga_agilex_socdk.dts copy to arch/arm/dts/socfpga_agilex7m_socdk.dts index bcdeecc0e0..ba929b9c74 100644 --- a/arch/arm/dts/socfpga_agilex_socdk.dts +++ b/arch/arm/dts/socfpga_agilex7m_socdk.dts @@ -1,11 +1,11 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2019, Intel Corporation + * Copyright (C) 2024, Intel Corporation */ #include "socfpga_agilex.dtsi" / { - model = "SoCFPGA Agilex SoCDK"; + model = "SoCFPGA Agilex7-M SoCDK"; aliases { serial0 = &uart0; @@ -14,10 +14,6 @@ ethernet2 = &gmac2; }; - chosen { - stdout-path = "serial0:115200n8"; - }; - leds { compatible = "gpio-leds"; hps0 { @@ -85,6 +81,36 @@ }; }; +&gmac2 { + status = "okay"; + phy-mode = "rgmii"; + phy-handle = <&phy0>; + + max-frame-size = <3800>; + + mdio2 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy2: ethernet-phy@2 { + reg = <4>; + + txd0-skew-ps = <0>; /* -420ps */ + txd1-skew-ps = <0>; /* -420ps */ + txd2-skew-ps = <0>; /* -420ps */ + txd3-skew-ps = <0>; /* -420ps */ + rxd0-skew-ps = <420>; /* 0ps */ + rxd1-skew-ps = <420>; /* 0ps */ + rxd2-skew-ps = <420>; /* 0ps */ + rxd3-skew-ps = <420>; /* 0ps */ + txen-skew-ps = <0>; /* -420ps */ + txc-skew-ps = <1860>; /* 960ps */ + rxdv-skew-ps = <420>; /* 0ps */ + rxc-skew-ps = <1680>; /* 780ps */ + }; + }; +}; + &mmc { status = "okay"; cap-sd-highspeed; @@ -128,13 +154,31 @@ #size-cells = <1>; qspi_boot: partition@0 { - label = "Boot and fpga data"; - reg = <0x0 0x034B0000>; + label = "u-boot"; + reg = <0x0 0x04200000>; + }; + + root: partition@4200000 { + label = "root"; + reg = <0x04200000 0x0BE00000>; }; + }; + }; +}; - qspi_rootfs: partition@34B0000 { - label = "Root Filesystem - JFFS2"; - reg = <0x034B0000 0x0EB50000>; +&nand { + flash@0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "u-boot"; + reg = <0 0x200000>; + }; + partition@200000 { + label = "root"; + reg = <0x200000 0x3fe00000>; }; }; }; diff --git a/arch/arm/dts/socfpga_soc64_u-boot.dtsi b/arch/arm/dts/socfpga_soc64_u-boot.dtsi new file mode 100644 index 0000000000..d8a121ade8 --- /dev/null +++ b/arch/arm/dts/socfpga_soc64_u-boot.dtsi @@ -0,0 +1,127 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot additions + * + * Copyright (C) 2024 Intel Corporation + */ + +/ { + soc { + socfpga-system-mgr-firewall { + compatible = "intel,socfpga-dtreg"; + #address-cells = <1>; + #size-cells = <1>; + bootph-all; + + i_sys_mgr_core@ffd12000 { + reg = <0xffd12000 0x00000230>; + intel,offset-settings = + /* Enable non-secure interface to DMA */ + <0x00000020 0xff010000 0xff010011>, + /* Enable non-secure interface to DMA periph */ + <0x00000024 0xffffffff 0xffffffff>; + bootph-all; + }; + }; + + socfpga_l3interconnect_firewall:socfpga-l3interconnect-firewall { + compatible = "intel,socfpga-dtreg"; + #address-cells = <1>; + #size-cells = <1>; + bootph-all; + + noc_fw_l4_per_l4_per_scr@ffd21000 { + reg = <0xffd21000 0x00000074>; + intel,offset-settings = + /* Disable L4 periphs firewall */ + <0x00000000 0x01010001 0x01010001>, + <0x00000004 0x01010001 0x01010001>, + <0x0000000c 0x01010001 0x01010001>, + <0x00000010 0x01010001 0x01010001>, + <0x0000001c 0x01010001 0x01010101>, + <0x00000020 0x01010001 0x01010101>, + <0x00000024 0x01010001 0x01010101>, + <0x00000028 0x01010001 0x01010101>, + <0x0000002c 0x01010001 0x01010001>, + <0x00000030 0x01010001 0x01010001>, + <0x00000034 0x01010001 0x01010001>, + <0x00000040 0x01010001 0x01010001>, + <0x00000044 0x01010001 0x01010101>, + <0x00000048 0x01010001 0x01010101>, + <0x00000050 0x01010001 0x01010101>, + <0x00000054 0x01010001 0x01010101>, + <0x00000058 0x01010001 0x01010101>, + <0x0000005c 0x01010001 0x01010101>, + <0x00000060 0x01010001 0x01010101>, + <0x00000064 0x01010001 0x01010101>, + <0x00000068 0x01010001 0x01010101>, + <0x0000006c 0x01010001 0x01010101>, + <0x00000070 0x01010001 0x01010101>; + bootph-all; + }; + + noc_fw_l4_sys_l4_sys_scr@ffd21100 { + reg = <0xffd21100 0x00000098>; + intel,offset-settings = + /* Disable L4 system firewall */ + <0x00000008 0x01010001 0x01010001>, + <0x0000000c 0x01010001 0x01010001>, + <0x00000010 0x01010001 0x01010001>, + <0x00000014 0x01010001 0x01010001>, + <0x00000018 0x01010001 0x01010001>, + <0x0000001c 0x01010001 0x01010001>, + <0x00000020 0x01010001 0x01010001>, + <0x0000002c 0x01010001 0x01010001>, + <0x00000030 0x01010001 0x01010001>, + <0x00000034 0x01010001 0x01010001>, + <0x00000038 0x01010001 0x01010001>, + <0x00000040 0x01010001 0x01010001>, + <0x00000044 0x01010001 0x01010001>, + <0x00000048 0x01010001 0x01010001>, + <0x0000004c 0x01010001 0x01010001>, + <0x00000054 0x01010001 0x01010001>, + <0x00000058 0x01010001 0x01010001>, + <0x0000005c 0x01010001 0x01010001>, + <0x00000060 0x01010001 0x01010101>, + <0x00000064 0x01010001 0x01010101>, + <0x00000068 0x01010001 0x01010101>, + <0x0000006c 0x01010001 0x01010101>, + <0x00000070 0x01010001 0x01010101>, + <0x00000074 0x01010001 0x01010101>, + <0x00000078 0x01010001 0x03010001>, + <0x00000090 0x01010001 0x01010001>, + <0x00000094 0x01010001 0x01010001>; + bootph-all; + }; + + noc_fw_soc2fpga_soc2fpga_scr@ffd21200 { + reg = <0xffd21200 0x00000004>; + /* Disable soc2fpga security access */ + intel,offset-settings = <0x00000000 0x0ffe0101 0x0ffe0101>; + bootph-all; + }; + + noc_fw_lwsoc2fpga_lwsoc2fpga_scr@ffd21300 { + reg = <0xffd21300 0x00000004>; + /* Disable lightweight soc2fpga security access */ + intel,offset-settings = <0x00000000 0x0ffe0101 0x0ffe0101>; + bootph-all; + }; + + noc_fw_tcu_tcu_scr@ffd21400 { + reg = <0xffd21400 0x00000004>; + /* Disable DMA ECC security access, for SMMU use */ + intel,offset-settings = <0x00000000 0x01010001 0x01010001>; + bootph-all; + }; + + noc_fw_priv_MemoryMap_priv@ffd24800 { + reg = <0xffd24800 0x0000000c>; + intel,offset-settings = + /* Enable non-prviledged access to various periphs */ + <0x00000000 0xfff73ffb 0xfff73ffb>; + bootph-all; + }; + }; + }; +}; From patchwork Fri May 17 05:26:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Meng, Tingting" X-Patchwork-Id: 1936425 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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16 May 2024 22:27:39 -0700 X-CSE-ConnectionGUID: mFGCVWNXTbWFTZTNgGxcJQ== X-CSE-MsgGUID: 2KRzmzQgReCi5NBVoNp35g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,166,1712646000"; d="scan'208";a="36188223" Received: from pglc00543.png.intel.com ([10.221.239.235]) by fmviesa003.fm.intel.com with ESMTP; 16 May 2024 22:27:34 -0700 From: tingting.meng@intel.com To: u-boot@lists.denx.de Cc: Lukasz Majewski , Sean Anderson , Rayagonda Kokatanur , Tom Rini , Marek , Simon , Tien Fong , Kok Kiang , Dinesh , Boon Khai , Alif , Teik Heng , Hazim , Jit Loon Lim , Sieu Mun Tang , Wan Yee Lau , Tingting Meng Subject: [Agilex7 M-series Platform Enablement v1 02/16] arch: arm: mach-socfpga: Add Agilex7 M-series mach-socfgpa enablement Date: Fri, 17 May 2024 13:26:47 +0800 Message-Id: <20240517052701.12949-3-tingting.meng@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240517052701.12949-1-tingting.meng@intel.com> References: <20240517052701.12949-1-tingting.meng@intel.com> MIME-Version: 1.0 X-Mailman-Approved-At: Fri, 17 May 2024 14:50:41 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Wan Yee Lau Add platform related files for new platform Agilex7 M-series. Signed-off-by: Wan Yee Lau Signed-off-by: Teik Heng Chong Signed-off-by: Tingting Meng --- arch/arm/mach-socfpga/include/mach/misc.h | 3 +- .../{spl_agilex.c => spl_agilex7m.c} | 45 ++++++++++++------- arch/arm/mach-socfpga/wrap_handoff_soc64.c | 4 ++ board/intel/agilex7m-socdk/MAINTAINERS | 7 +++ board/intel/agilex7m-socdk/socfpga.c | 4 ++ 5 files changed, 45 insertions(+), 18 deletions(-) copy arch/arm/mach-socfpga/{spl_agilex.c => spl_agilex7m.c} (68%) create mode 100644 board/intel/agilex7m-socdk/MAINTAINERS create mode 100644 board/intel/agilex7m-socdk/socfpga.c diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h index 8460acb00d..e271d2855f 100644 --- a/arch/arm/mach-socfpga/include/mach/misc.h +++ b/arch/arm/mach-socfpga/include/mach/misc.h @@ -40,7 +40,8 @@ void socfpga_sdram_remap_zero(void); #endif #if defined(CONFIG_TARGET_SOCFPGA_STRATIX10) || \ - defined(CONFIG_TARGET_SOCFPGA_AGILEX) + defined(CONFIG_TARGET_SOCFPGA_AGILEX) || \ + defined(CONFIG_TARGET_SOCFPGA_AGILEX7M) int is_fpga_config_ready(void); #endif diff --git a/arch/arm/mach-socfpga/spl_agilex.c b/arch/arm/mach-socfpga/spl_agilex7m.c similarity index 68% copy from arch/arm/mach-socfpga/spl_agilex.c copy to arch/arm/mach-socfpga/spl_agilex7m.c index ee5a9dc1e2..ee41db8884 100644 --- a/arch/arm/mach-socfpga/spl_agilex.c +++ b/arch/arm/mach-socfpga/spl_agilex7m.c @@ -1,26 +1,25 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2019 Intel Corporation - * + * Copyright (C) 2024 Intel Corporation */ -#include -#include -#include -#include -#include -#include #include #include #include +#include +#include #include +#include #include #include #include #include #include #include -#include +#include +#include +#include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -40,13 +39,6 @@ void board_init_f(ulong dummy) writel(SYSMGR_WDDBG_PAUSE_ALL_CPU, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG); -#ifdef CONFIG_HW_WATCHDOG - /* Enable watchdog before initializing the HW */ - socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1); - socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0); - hw_watchdog_init(); -#endif - /* ensure all processors are not released prior Linux boot */ writeq(0, CPU_RELEASE_ADDR); @@ -60,11 +52,30 @@ void board_init_f(ulong dummy) hang(); } + /* + * Enable watchdog as early as possible before initializing other + * component. Watchdog need to be enabled after clock driver because + * it will retrieve the clock frequency from clock driver. + */ + if (CONFIG_IS_ENABLED(WDT)) + initr_watchdog(); + preloader_console_init(); print_reset_info(); cm_print_clock_quick_summary(); - firewall_setup(); + ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-system-mgr-firewall", &dev); + if (ret) { + printf("System manager firewall configuration failed: %d\n", ret); + hang(); + } + + ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-l3interconnect-firewall", &dev); + if (ret) { + printf("L3 interconnect firewall configuration failed: %d\n", ret); + hang(); + } + ret = uclass_get_device(UCLASS_CACHE, 0, &dev); if (ret) { debug("CCU init failed: %d\n", ret); diff --git a/arch/arm/mach-socfpga/wrap_handoff_soc64.c b/arch/arm/mach-socfpga/wrap_handoff_soc64.c index 6aa9bb26b4..8c06b3d59e 100644 --- a/arch/arm/mach-socfpga/wrap_handoff_soc64.c +++ b/arch/arm/mach-socfpga/wrap_handoff_soc64.c @@ -39,6 +39,10 @@ static enum endianness check_endianness(u32 handoff) case SOC64_HANDOFF_DDR_PHY_INIT_ENGINE_MAGIC: debug("%s: PHY engine handoff data\n", __func__); return LITTLE_ENDIAN; +#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) + case SOC64_HANDOFF_MAGIC_DDR: + debug("%s: SOC64_HANDOFF_MAGIC_DDR\n", __func__); + return BIG_ENDIAN; #endif default: debug("%s: Unknown endianness!!\n", __func__); diff --git a/board/intel/agilex7m-socdk/MAINTAINERS b/board/intel/agilex7m-socdk/MAINTAINERS new file mode 100644 index 0000000000..feb2916488 --- /dev/null +++ b/board/intel/agilex7m-socdk/MAINTAINERS @@ -0,0 +1,7 @@ +SOCFPGA BOARD +M: Tien Fong Chee +M: Teik Heng Chong +S: Maintained +F: board/intel/agilex7m-socdk/ +F: include/configs/socfpga_agilex7m_socdk.h +F: configs/socfpga_agilex7m_sdmmc_defconfig diff --git a/board/intel/agilex7m-socdk/socfpga.c b/board/intel/agilex7m-socdk/socfpga.c new file mode 100644 index 0000000000..52921d90aa --- /dev/null +++ b/board/intel/agilex7m-socdk/socfpga.c @@ -0,0 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 Intel Corporation + */ From patchwork Fri May 17 05:26:48 2024 Content-Type: text/plain; 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d="scan'208";a="11929947" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 May 2024 22:27:43 -0700 X-CSE-ConnectionGUID: lZBf8YljQPyTa8F7w5OuGQ== X-CSE-MsgGUID: L2KGqWe2SZm9lqERbDUkuw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,166,1712646000"; d="scan'208";a="36188228" Received: from pglc00543.png.intel.com ([10.221.239.235]) by fmviesa003.fm.intel.com with ESMTP; 16 May 2024 22:27:39 -0700 From: tingting.meng@intel.com To: u-boot@lists.denx.de Cc: Lukasz Majewski , Sean Anderson , Rayagonda Kokatanur , Tom Rini , Marek , Simon , Tien Fong , Kok Kiang , Dinesh , Boon Khai , Alif , Teik Heng , Hazim , Jit Loon Lim , Sieu Mun Tang , Wan Yee Lau , Tingting Meng Subject: [Agilex7 M-series Platform Enablement v1 03/16] arch: arm: mach-socfpga: Improve help info. Date: Fri, 17 May 2024 13:26:48 +0800 Message-Id: <20240517052701.12949-4-tingting.meng@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240517052701.12949-1-tingting.meng@intel.com> References: <20240517052701.12949-1-tingting.meng@intel.com> MIME-Version: 1.0 X-Mailman-Approved-At: Fri, 17 May 2024 14:50:41 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Teik Heng Chong To improve help info for bridge enable/disable command. Signed-off-by: Wan Yee Lau Signed-off-by: Teik Heng Chong Signed-off-by: Tingting Meng --- arch/arm/mach-socfpga/misc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 80ad087034..79f7887519 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -210,8 +210,8 @@ static int do_bridge(struct cmd_tbl *cmdtp, int flag, int argc, U_BOOT_CMD(bridge, 3, 1, do_bridge, "SoCFPGA HPS FPGA bridge control", - "enable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" - "bridge disable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" + "enable [mask] - Enable HPS-to-FPGA (Bit 0), LWHPS-to-FPGA (Bit 1), FPGA-to-HPS (Bit 2) bridges \n" + "bridge disable [mask] - Disable HPS-to-FPGA (Bit 0), LWHPS-to-FPGA (Bit 1), FPGA-to-HPS (Bit 2) bridges\n" "" ); From patchwork Fri May 17 05:26:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Meng, Tingting" X-Patchwork-Id: 1936429 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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16 May 2024 22:27:47 -0700 X-CSE-ConnectionGUID: YNR9BhQLQuS5wzUodKS+Bg== X-CSE-MsgGUID: WxbX9eOkRq6IVWatjdghbg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,166,1712646000"; d="scan'208";a="36188231" Received: from pglc00543.png.intel.com ([10.221.239.235]) by fmviesa003.fm.intel.com with ESMTP; 16 May 2024 22:27:43 -0700 From: tingting.meng@intel.com To: u-boot@lists.denx.de Cc: Lukasz Majewski , Sean Anderson , Rayagonda Kokatanur , Tom Rini , Marek , Simon , Tien Fong , Kok Kiang , Dinesh , Boon Khai , Alif , Teik Heng , Hazim , Jit Loon Lim , Sieu Mun Tang , Wan Yee Lau , Tingting Meng Subject: [Agilex7 M-series Platform Enablement v1 04/16] arch: arm: mach-socfpga: Update handoff settings for Agilex7 M-series Date: Fri, 17 May 2024 13:26:49 +0800 Message-Id: <20240517052701.12949-5-tingting.meng@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240517052701.12949-1-tingting.meng@intel.com> References: <20240517052701.12949-1-tingting.meng@intel.com> MIME-Version: 1.0 X-Mailman-Approved-At: Fri, 17 May 2024 14:50:41 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Wan Yee Lau Handoff settings updated for new platform Agilex7 M-series. Signed-off-by: Wan Yee Lau Signed-off-by: Teik Heng Chong Signed-off-by: Tingting Meng --- arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h index d839f28841..747016b436 100644 --- a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h @@ -28,10 +28,20 @@ #define SOC64_HANDOFF_OFFSET_DATA 0x10 #define SOC64_HANDOFF_SIZE 4096 -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10) || \ - IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_SOC64) || \ + IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) #define SOC64_HANDOFF_BASE 0xFFE3F000 +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) +#define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x62C) +/* DDR handoff */ +#define SOC64_HANDOFF_MAGIC_DDR 0x5344524D +#define SOC64_HANDOFF_DDR_BASE (SOC64_HANDOFF_BASE + 0x610) +#define SOC64_HANDOFF_DDR_LEN 2 +#define SOC64_HANDOFF_DDR_INTERLEAVING_MODE_MASK BIT(0) +#define SOC64_HANDOFF_DDR_MEMORY_TYPE_MASK BIT(0) +#else #define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x610) +#endif #elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) #define SOC64_HANDOFF_BASE 0x0007F000 #elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) From patchwork Fri May 17 05:26:50 2024 Content-Type: text/plain; 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Signed-off-by: Wan Yee Lau Signed-off-by: Teik Heng Chong Signed-off-by: Tingting Meng --- .../{socfpga_agilex5_socdk.h => socfpga_agilex7m_socdk.h} | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) copy include/configs/{socfpga_agilex5_socdk.h => socfpga_agilex7m_socdk.h} (55%) diff --git a/include/configs/socfpga_agilex5_socdk.h b/include/configs/socfpga_agilex7m_socdk.h similarity index 55% copy from include/configs/socfpga_agilex5_socdk.h copy to include/configs/socfpga_agilex7m_socdk.h index b5b5bd767f..433556804e 100644 --- a/include/configs/socfpga_agilex5_socdk.h +++ b/include/configs/socfpga_agilex7m_socdk.h @@ -4,9 +4,9 @@ * */ -#ifndef __CONFIG_SOCFGPA_AGILEX5_H__ -#define __CONFIG_SOCFGPA_AGILEX5_H__ +#ifndef __CONFIG_SOCFGPA_AGILEX7M_H__ +#define __CONFIG_SOCFGPA_AGILEX7M_H__ #include -#endif /* __CONFIG_SOCFGPA_AGILEX5_H__ */ +#endif /* __CONFIG_SOCFGPA_AGILEX7M_H__ */ From patchwork Fri May 17 05:26:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Meng, Tingting" X-Patchwork-Id: 1936433 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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d="scan'208";a="36188248" Received: from pglc00543.png.intel.com ([10.221.239.235]) by fmviesa003.fm.intel.com with ESMTP; 16 May 2024 22:27:51 -0700 From: tingting.meng@intel.com To: u-boot@lists.denx.de Cc: Lukasz Majewski , Sean Anderson , Rayagonda Kokatanur , Tom Rini , Marek , Simon , Tien Fong , Kok Kiang , Dinesh , Boon Khai , Alif , Teik Heng , Hazim , Jit Loon Lim , Sieu Mun Tang , Siew Chin Lim , Tingting Meng Subject: [Agilex7 M-series Platform Enablement v1 06/16] include: configs: soc64: Use CONFIG_SPL_ATF to differentiate bootfile Date: Fri, 17 May 2024 13:26:51 +0800 Message-Id: <20240517052701.12949-7-tingting.meng@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240517052701.12949-1-tingting.meng@intel.com> References: <20240517052701.12949-1-tingting.meng@intel.com> MIME-Version: 1.0 X-Mailman-Approved-At: Fri, 17 May 2024 14:50:41 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Siew Chin Lim ATF boot flow (SPL->ATF->U-Boot Proper->OS) boot to OS via kernel.itb file using bootm command. Change to use CONFIG_SPL_ATF to differentiate the bootfile of default environment variable. We shouldn't use CONFIG_FIT because it is enabled by default for U-Boot Proper. Signed-off-by: Siew Chin Lim Signed-off-by: Teik Heng Chong Signed-off-by: Tingting Meng --- arch/arm/Kconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index a0842e1933..56e190adf6 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -21,6 +21,9 @@ config ARM64_CRC32 not be present on all ARMv8.0, but is always present on ARMv8.1 and newer. +config BOOTFILE + default kernel.itb if SPL_ATF && TARGET_SOCFPGA_SOC64 + config COUNTER_FREQUENCY int "Timer clock frequency" depends on ARM64 || CPU_V7A From patchwork Fri May 17 05:26:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Meng, Tingting" X-Patchwork-Id: 1936434 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=N1IC6PGi; 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d="scan'208";a="36188254" Received: from pglc00543.png.intel.com ([10.221.239.235]) by fmviesa003.fm.intel.com with ESMTP; 16 May 2024 22:27:56 -0700 From: tingting.meng@intel.com To: u-boot@lists.denx.de Cc: Lukasz Majewski , Sean Anderson , Rayagonda Kokatanur , Tom Rini , Marek , Simon , Tien Fong , Kok Kiang , Dinesh , Boon Khai , Alif , Teik Heng , Hazim , Jit Loon Lim , Sieu Mun Tang , Wan Yee Lau , Tingting Meng Subject: [Agilex7 M-series Platform Enablement v1 07/16] clk: altera: Add clock support for Agilex7 M-series Date: Fri, 17 May 2024 13:26:52 +0800 Message-Id: <20240517052701.12949-8-tingting.meng@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240517052701.12949-1-tingting.meng@intel.com> References: <20240517052701.12949-1-tingting.meng@intel.com> MIME-Version: 1.0 X-Mailman-Approved-At: Fri, 17 May 2024 14:50:41 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Teik Heng Chong Agilex7 M-series reuse the clock driver from Agilex. Signed-off-by: Wan Yee Lau Signed-off-by: Teik Heng Chong Signed-off-by: Tingting Meng --- arch/arm/mach-socfpga/include/mach/clock_manager.h | 2 +- arch/arm/mach-socfpga/misc.c | 2 +- drivers/clk/altera/Makefile | 1 + 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h index 6c9d32b9dd..77d97193f5 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h @@ -26,7 +26,7 @@ int cm_set_qspi_controller_clk_hz(u32 clk_hz); #include #elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10) #include -#elif defined(CONFIG_TARGET_SOCFPGA_AGILEX) +#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) #include #elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) #include diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 79f7887519..5537445e10 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -252,7 +252,7 @@ void socfpga_get_managers_addr(void) if (ret) hang(); -#ifdef CONFIG_TARGET_SOCFPGA_AGILEX +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) ret = socfpga_get_base_addr("intel,agilex-clkmgr", &socfpga_clkmgr_base); #elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) diff --git a/drivers/clk/altera/Makefile b/drivers/clk/altera/Makefile index 61ffa4179a..858f828e53 100644 --- a/drivers/clk/altera/Makefile +++ b/drivers/clk/altera/Makefile @@ -4,6 +4,7 @@ # obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += clk-agilex.o +obj-$(CONFIG_TARGET_SOCFPGA_AGILEX7M) += clk-agilex.o obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clk-arria10.o obj-$(CONFIG_TARGET_SOCFPGA_N5X) += clk-n5x.o obj-$(CONFIG_TARGET_SOCFPGA_N5X) += clk-mem-n5x.o From patchwork Fri May 17 05:26:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Meng, Tingting" X-Patchwork-Id: 1936436 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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16 May 2024 22:28:04 -0700 X-CSE-ConnectionGUID: zwoMCzeQSqCtVrlMbf9Olg== X-CSE-MsgGUID: MZQN9ctgR1GeSqw+GFkMeQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,166,1712646000"; d="scan'208";a="36188272" Received: from pglc00543.png.intel.com ([10.221.239.235]) by fmviesa003.fm.intel.com with ESMTP; 16 May 2024 22:28:00 -0700 From: tingting.meng@intel.com To: u-boot@lists.denx.de Cc: Lukasz Majewski , Sean Anderson , Rayagonda Kokatanur , Tom Rini , Marek , Simon , Tien Fong , Kok Kiang , Dinesh , Boon Khai , Alif , Teik Heng , Hazim , Jit Loon Lim , Sieu Mun Tang , Wan Yee Lau , Tingting Meng Subject: [Agilex7 M-series Platform Enablement v1 08/16] ddr: altera: Add iossm mailbox for Agilex7 M-series Date: Fri, 17 May 2024 13:26:53 +0800 Message-Id: <20240517052701.12949-9-tingting.meng@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240517052701.12949-1-tingting.meng@intel.com> References: <20240517052701.12949-1-tingting.meng@intel.com> MIME-Version: 1.0 X-Mailman-Approved-At: Fri, 17 May 2024 14:50:41 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Wan Yee Lau Add iossm mailbox driver for Agilex7 M-series. HPS will interact with IO96B and DDR subsystem through software defined mailbox interface. HPS can retrieve memory interface calibration status, IO96B configuration, memory interfae configuration, trigger calibration and etc with the list of supported mailbox command type and opcode. Signed-off-by: Wan Yee Lau Signed-off-by: Teik Heng Chong Signed-off-by: Tingting Meng --- drivers/ddr/altera/iossm_mailbox.c | 637 +++++++++++++++++++++++++++++ drivers/ddr/altera/iossm_mailbox.h | 182 +++++++++ 2 files changed, 819 insertions(+) create mode 100644 drivers/ddr/altera/iossm_mailbox.c create mode 100644 drivers/ddr/altera/iossm_mailbox.h diff --git a/drivers/ddr/altera/iossm_mailbox.c b/drivers/ddr/altera/iossm_mailbox.c new file mode 100644 index 0000000000..f84a3a070d --- /dev/null +++ b/drivers/ddr/altera/iossm_mailbox.c @@ -0,0 +1,637 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 Intel Corporation + */ + +#include +#include +#include +#include +#include +#include +#include "iossm_mailbox.h" + +#define ECC_INTSTATUS_SERR SOCFPGA_SYSMGR_ADDRESS + 0x9C +#define ECC_INISTATUS_DERR SOCFPGA_SYSMGR_ADDRESS + 0xA0 +#define DDR_CSR_CLKGEN_LOCKED_IO96B0_MASK BIT(16) +#define DDR_CSR_CLKGEN_LOCKED_IO96B1_MASK BIT(17) + +#define DDR_CSR_CLKGEN_LOCKED_IO96B_MASK(x) (i == 0 ? DDR_CSR_CLKGEN_LOCKED_IO96B0_MASK : \ + DDR_CSR_CLKGEN_LOCKED_IO96B1_MASK) + +#define IO96B_MB_REQ_SETUP(v, w, x, y, z) usr_req.ip_type = v; \ + usr_req.ip_id = w; \ + usr_req.usr_cmd_type = x; \ + usr_req.usr_cmd_opcode = y; \ + usr_req.cmd_param[0] = z; \ + for (n = 1; n < NUM_CMD_PARAM; n++) \ + usr_req.cmd_param[n] = 0 +#define MAX_RETRY_COUNT 3 + +#define IO96B0_PLL_A_MASK BIT(0) +#define IO96B0_PLL_B_MASK BIT(1) +#define IO96B1_PLL_A_MASK BIT(2) +#define IO96B1_PLL_B_MASK BIT(3) + +/* supported DDR type list */ +static const char *ddr_type_list[7] = { + "DDR4", "DDR5", "DDR5_RDIMM", "LPDDR4", "LPDDR5", "QDRIV", "UNKNOWN" +}; + +static int is_ddr_csr_clkgen_locked(u8 io96b_pll) +{ + int ret = 0; + + if (FIELD_GET(IO96B0_PLL_A_MASK, io96b_pll)) { + ret = wait_for_bit_le32((const void *)(ECC_INTSTATUS_SERR), + DDR_CSR_CLKGEN_LOCKED_IO96B0_MASK, true, TIMEOUT, false); + + if (ret) { + debug("%s: ddr csr io96b_0 clkgenA locked is timeout\n", __func__); + goto err; + } + } + + if (FIELD_GET(IO96B0_PLL_B_MASK, io96b_pll)) { + ret = wait_for_bit_le32((const void *)(ECC_INISTATUS_DERR), + DDR_CSR_CLKGEN_LOCKED_IO96B0_MASK, true, TIMEOUT, false); + + if (ret) { + debug("%s: ddr csr io96b_0 clkgenB locked is timeout\n", __func__); + goto err; + } + } + + if (FIELD_GET(IO96B1_PLL_A_MASK, io96b_pll)) { + ret = wait_for_bit_le32((const void *)(ECC_INTSTATUS_SERR), + DDR_CSR_CLKGEN_LOCKED_IO96B1_MASK, true, TIMEOUT, false); + + if (ret) { + debug("%s: ddr csr io96b_1 clkgenA locked is timeout\n", __func__); + goto err; + } + } + + if (FIELD_GET(IO96B1_PLL_B_MASK, io96b_pll)) { + ret = wait_for_bit_le32((const void *)(ECC_INISTATUS_DERR), + DDR_CSR_CLKGEN_LOCKED_IO96B1_MASK, true, TIMEOUT, false); + + if (ret) { + debug("%s: ddr csr io96b_1 clkgenB locked is timeout\n", __func__); + goto err; + } + } + +err: + return ret; +} + +/* Mailbox request function + * This function will send the request to IOSSM mailbox and wait for response return + * + * @io96b_csr_addr: CSR address for the target IO96B + * @req: Structure contain command request for IOSSM mailbox command + * @resp_data_len: User desire extra response data fields other than + * CMD_RESPONSE_DATA_SHORT field on CMD_RESPONSE_STATUS + * @resp: Structure contain responses returned from the requested IOSSM + * mailbox command + */ +int io96b_mb_req(phys_addr_t io96b_csr_addr, struct io96b_mb_req req, + u32 resp_data_len, struct io96b_mb_resp *resp) +{ + int i, ret; + u32 cmd_req, cmd_resp; + + /* Initialized zeros for responses */ + resp->cmd_resp_status = 0; + for (i = 0; i < NUM_CMD_RESPONSE_DATA; i++) + resp->cmd_resp_data[i] = 0; + + /* Ensure CMD_REQ is cleared before write any command request */ + ret = wait_for_bit_le32((const void *)(io96b_csr_addr + IOSSM_CMD_REQ_OFFSET), + GENMASK(31, 0), 0, TIMEOUT, false); + if (ret) { + printf("%s: CMD_REQ not ready\n", __func__); + + return ret; + } + + /* Write CMD_PARAM_* */ + for (i = 0; i < NUM_CMD_PARAM ; i++) { + switch (i) { + case 0: + if (req.cmd_param[0]) + writel(req.cmd_param[0], io96b_csr_addr + IOSSM_CMD_PARAM_0_OFFSET); + break; + case 1: + if (req.cmd_param[1]) + writel(req.cmd_param[1], io96b_csr_addr + IOSSM_CMD_PARAM_1_OFFSET); + break; + case 2: + if (req.cmd_param[2]) + writel(req.cmd_param[2], io96b_csr_addr + IOSSM_CMD_PARAM_2_OFFSET); + break; + case 3: + if (req.cmd_param[3]) + writel(req.cmd_param[3], io96b_csr_addr + IOSSM_CMD_PARAM_3_OFFSET); + break; + case 4: + if (req.cmd_param[4]) + writel(req.cmd_param[4], io96b_csr_addr + IOSSM_CMD_PARAM_4_OFFSET); + break; + case 5: + if (req.cmd_param[5]) + writel(req.cmd_param[5], io96b_csr_addr + IOSSM_CMD_PARAM_5_OFFSET); + break; + case 6: + if (req.cmd_param[6]) + writel(req.cmd_param[6], io96b_csr_addr + IOSSM_CMD_PARAM_6_OFFSET); + break; + default: + printf("%s: Invalid command parameter\n", __func__); + } + } + + /* Write CMD_REQ (IP_TYPE, IP_INSTANCE_ID, CMD_TYPE and CMD_OPCODE) */ + cmd_req = FIELD_PREP(CMD_TARGET_IP_TYPE_MASK, req.ip_type) | + FIELD_PREP(CMD_TARGET_IP_INSTANCE_ID_MASK, req.ip_id) | + FIELD_PREP(CMD_TYPE_MASK, req.usr_cmd_type) | + FIELD_PREP(CMD_OPCODE_MASK, req.usr_cmd_opcode); + writel(cmd_req, io96b_csr_addr + IOSSM_CMD_REQ_OFFSET); + + debug("%s: Write 0x%x to IOSSM_CMD_REQ_OFFSET 0x%llx\n", __func__, cmd_req, + io96b_csr_addr + IOSSM_CMD_REQ_OFFSET); + /* Read CMD_RESPONSE_READY in CMD_RESPONSE_STATUS */ + ret = wait_for_bit_le32((const void *)(io96b_csr_addr + IOSSM_CMD_RESPONSE_STATUS_OFFSET), + IOSSM_STATUS_COMMAND_RESPONSE_READY, 1, TIMEOUT, false); + if (ret) { + printf("%s: CMD_RESPONSE ERROR:\n", __func__); + + cmd_resp = readl(io96b_csr_addr + IOSSM_CMD_RESPONSE_STATUS_OFFSET); + + printf("%s: STATUS_GENERAL_ERROR: 0x%lx\n", __func__, + IOSSM_STATUS_GENERAL_ERROR(cmd_resp)); + printf("%s: STATUS_CMD_RESPONSE_ERROR: 0x%lx\n", __func__, + IOSSM_STATUS_CMD_RESPONSE_ERROR(cmd_resp)); + } + + /* read CMD_RESPONSE_STATUS */ + resp->cmd_resp_status = readl(io96b_csr_addr + IOSSM_CMD_RESPONSE_STATUS_OFFSET); + + debug("%s: CMD_RESPONSE_STATUS 0x%llx: 0x%x\n", __func__, io96b_csr_addr + + IOSSM_CMD_RESPONSE_STATUS_OFFSET, resp->cmd_resp_status); + + /* read CMD_RESPONSE_DATA_* */ + for (i = 0; i < resp_data_len; i++) { + switch (i) { + case 0: + resp->cmd_resp_data[i] = + readl(io96b_csr_addr + IOSSM_CMD_RESPONSE_DATA_0_OFFSET); + + debug("%s: IOSSM_CMD_RESPONSE_DATA_0_OFFSET 0x%llx: 0x%x\n", __func__, + io96b_csr_addr + IOSSM_CMD_RESPONSE_DATA_0_OFFSET, + resp->cmd_resp_data[i]); + break; + case 1: + resp->cmd_resp_data[i] = + readl(io96b_csr_addr + IOSSM_CMD_RESPONSE_DATA_1_OFFSET); + + debug("%s: IOSSM_CMD_RESPONSE_DATA_1_OFFSET 0x%llx: 0x%x\n", __func__, + io96b_csr_addr + IOSSM_CMD_RESPONSE_DATA_1_OFFSET, + resp->cmd_resp_data[i]); + break; + case 2: + resp->cmd_resp_data[i] = + readl(io96b_csr_addr + IOSSM_CMD_RESPONSE_DATA_2_OFFSET); + + debug("%s: IOSSM_CMD_RESPONSE_DATA_2_OFFSET 0x%llx: 0x%x\n", __func__, + io96b_csr_addr + IOSSM_CMD_RESPONSE_DATA_2_OFFSET, + resp->cmd_resp_data[i]); + break; + default: + printf("%s: Invalid response data\n", __func__); + } + } + + resp->cmd_resp_status = readl(io96b_csr_addr + IOSSM_CMD_RESPONSE_STATUS_OFFSET); + + debug("%s: CMD_RESPONSE_STATUS 0x%llx: 0x%x\n", __func__, io96b_csr_addr + + IOSSM_CMD_RESPONSE_STATUS_OFFSET, resp->cmd_resp_status); + + /* write CMD_RESPONSE_READY = 0 */ + clrbits_le32((u32 *)(uintptr_t)(io96b_csr_addr + IOSSM_CMD_RESPONSE_STATUS_OFFSET), + IOSSM_STATUS_COMMAND_RESPONSE_READY); + + resp->cmd_resp_status = readl(io96b_csr_addr + IOSSM_CMD_RESPONSE_STATUS_OFFSET); + + debug("%s: CMD_RESPONSE_READY 0x%llx: 0x%x\n", __func__, io96b_csr_addr + + IOSSM_CMD_RESPONSE_STATUS_OFFSET, resp->cmd_resp_status); + + return 0; +} + +/* + * Initial function to be called to set memory interface IP type and instance ID + * IP type and instance ID need to be determined before sending mailbox command + */ +void io96b_mb_init(struct io96b_info *io96b_ctrl) +{ + struct io96b_mb_req usr_req; + struct io96b_mb_resp usr_resp; + u8 ip_type_ret, instance_id_ret; + int i, j, k, n; + + debug("%s: num_instance %d\n", __func__, io96b_ctrl->num_instance); + + for (i = 0; i < io96b_ctrl->num_instance; i++) { + debug("%s: get memory interface IO96B %d\n", __func__, i); + + IO96B_MB_REQ_SETUP(0, + 0, + CMD_GET_SYS_INFO, + GET_MEM_INTF_INFO, + 0); + + /* Get memory interface IP type and instance ID (IP identifier) */ + io96b_mb_req(io96b_ctrl->io96b[i].io96b_csr_addr, usr_req, 2, &usr_resp); + + debug("%s: get response from memory interface IO96B %d\n", __func__, i); + + /* Retrieve number of memory interface(s) */ + io96b_ctrl->io96b[i].mb_ctrl.num_mem_interface = + IOSSM_CMD_RESPONSE_DATA_SHORT(usr_resp.cmd_resp_status) & 0x3; + + debug("%s: IO96B %d: num_mem_interface: 0x%x\n", __func__, i, + io96b_ctrl->io96b[i].mb_ctrl.num_mem_interface); + + /* Retrieve memory interface IP type and instance ID (IP identifier) */ + j = 0; + for (k = 0; k < io96b_ctrl->io96b[i].mb_ctrl.num_mem_interface; k++) { + ip_type_ret = FIELD_GET(INTF_IP_TYPE_MASK, usr_resp.cmd_resp_data[k]); + instance_id_ret = FIELD_GET(INTF_INSTANCE_ID_MASK, + usr_resp.cmd_resp_data[k]); + + if (ip_type_ret) { + io96b_ctrl->io96b[i].mb_ctrl.ip_type[j] = ip_type_ret; + io96b_ctrl->io96b[i].mb_ctrl.ip_id[j] = instance_id_ret; + + debug("%s: IO96B %d mem_interface %d: ip_type_ret: 0x%x\n", + __func__, i, j, ip_type_ret); + debug("%s: IO96B %d mem_interface %d: instance_id_ret: 0x%x\n", + __func__, i, j, instance_id_ret); + + j++; + } + } + } +} + +int io96b_cal_status(phys_addr_t addr) +{ + int ret; + u32 cal_success, cal_fail; + phys_addr_t status_addr = addr + IOSSM_STATUS_OFFSET; + + /* Ensure calibration completed */ + ret = wait_for_bit_le32((const void *)status_addr, IOSSM_STATUS_CAL_BUSY, false, + TIMEOUT, false); + if (ret) { + printf("%s: SDRAM calibration IO96b instance 0x%llx timeout\n", __func__, + status_addr); + + hang(); + } + + /* Calibration status */ + cal_success = readl(status_addr) & IOSSM_STATUS_CAL_SUCCESS; + cal_fail = readl(status_addr) & IOSSM_STATUS_CAL_FAIL; + + if (cal_success && !cal_fail) + return 0; + else + return -EPERM; +} + +void init_mem_cal(struct io96b_info *io96b_ctrl) +{ + int count, i, ret; + + /* Initialize overall calibration status */ + io96b_ctrl->overall_cal_status = false; + + if (io96b_ctrl->ckgen_lock) { + ret = is_ddr_csr_clkgen_locked(io96b_ctrl->io96b_pll); + if (ret) { + printf("%s: iossm IO96B ckgena_lock is not locked\n", __func__); + hang(); + } + } + + /* Check initial calibration status for the assigned IO96B */ + count = 0; + for (i = 0; i < io96b_ctrl->num_instance; i++) { + ret = io96b_cal_status(io96b_ctrl->io96b[i].io96b_csr_addr); + if (ret) { + io96b_ctrl->io96b[i].cal_status = false; + + printf("%s: Initial DDR calibration IO96B_%d failed %d\n", __func__, + i, ret); + + hang(); + } + + io96b_ctrl->io96b[i].cal_status = true; + + printf("%s: Initial DDR calibration IO96B_%d succeed\n", __func__, i); + + count++; + } + + if (count == io96b_ctrl->num_instance) + io96b_ctrl->overall_cal_status = true; +} + +/* Trying 3 times re-calibration if initial calibration failed */ +int trig_mem_cal(struct io96b_info *io96b_ctrl) +{ + struct io96b_mb_req usr_req; + struct io96b_mb_resp usr_resp; + bool recal_success; + int i, j, k, n; + u32 cal_stat_offset; + u8 cal_stat, trig_cal_stat; + int count = 0; + + for (i = 0; i < io96b_ctrl->num_instance; i++) { + if (!io96b_ctrl->io96b[i].cal_status) { + for (j = 0; j < io96b_ctrl->io96b[i].mb_ctrl.num_mem_interface; j++) { + /* Get the memory calibration status for memory interface */ + IO96B_MB_REQ_SETUP(0, + 0, + CMD_TRIG_MEM_CAL_OP, + GET_MEM_CAL_STATUS, + 0); + + io96b_mb_req(io96b_ctrl->io96b[i].io96b_csr_addr, usr_req, + 2, &usr_resp); + + recal_success = false; + + /* Re-calibration first memory interface with failed calibration */ + for (k = 0; k < MAX_RETRY_COUNT; k++) { + cal_stat_offset = usr_resp.cmd_resp_data[j]; + cal_stat = readl(io96b_ctrl->io96b[i].io96b_csr_addr + + cal_stat_offset); + if (cal_stat == INTF_MEM_CAL_STATUS_SUCCESS) { + recal_success = true; + break; + } + + IO96B_MB_REQ_SETUP(io96b_ctrl->io96b[i].mb_ctrl.ip_type[j], + io96b_ctrl->io96b[i].mb_ctrl.ip_id[j], + CMD_TRIG_MEM_CAL_OP, + TRIG_MEM_CAL, + 0); + + io96b_mb_req(io96b_ctrl->io96b[i].io96b_csr_addr, usr_req, + 2, &usr_resp); + + trig_cal_stat = + IOSSM_CMD_RESPONSE_DATA_SHORT(usr_resp.cmd_resp_status) & + BIT(0); + + debug("%s: Memory calibration triggered status = %d\n", + __func__, trig_cal_stat); + + udelay(1); + + IO96B_MB_REQ_SETUP(0, + 0, + CMD_TRIG_MEM_CAL_OP, + GET_MEM_CAL_STATUS, + 0); + + io96b_mb_req(io96b_ctrl->io96b[i].io96b_csr_addr, usr_req, + 2, &usr_resp); + } + + if (!recal_success) { + printf("%s: Error as SDRAM calibration failed\n", __func__); + + hang(); + } + } + + io96b_ctrl->io96b[i].cal_status = true; + io96b_ctrl->overall_cal_status = io96b_ctrl->io96b[i].cal_status; + + printf("%s: Initial DDR calibration IO96B_%d succeed\n", __func__, i); + + count++; + } + } + + if (io96b_ctrl->overall_cal_status) + debug("%s: Overall SDRAM calibration success\n", __func__); + + return 0; +} + +int get_mem_technology(struct io96b_info *io96b_ctrl) +{ + struct io96b_mb_req usr_req; + struct io96b_mb_resp usr_resp; + int i, j, n; + u8 ddr_type_ret; + + /* Initialize ddr type */ + io96b_ctrl->ddr_type = ddr_type_list[6]; + + /* Get and ensure all memory interface(s) same DDR type */ + for (i = 0; i < io96b_ctrl->num_instance; i++) { + for (j = 0; j < io96b_ctrl->io96b[i].mb_ctrl.num_mem_interface; j++) { + IO96B_MB_REQ_SETUP(io96b_ctrl->io96b[i].mb_ctrl.ip_type[j], + io96b_ctrl->io96b[i].mb_ctrl.ip_id[j], + CMD_GET_MEM_INFO, + GET_MEM_TECHNOLOGY, + 0); + + io96b_mb_req(io96b_ctrl->io96b[i].io96b_csr_addr, usr_req, 0, &usr_resp); + + ddr_type_ret = + IOSSM_CMD_RESPONSE_DATA_SHORT(usr_resp.cmd_resp_status) + & GENMASK(2, 0); + + if (!strcmp(io96b_ctrl->ddr_type, "UNKNOWN")) + io96b_ctrl->ddr_type = ddr_type_list[ddr_type_ret]; + + if (ddr_type_list[ddr_type_ret] != io96b_ctrl->ddr_type) { + printf("%s: Mismatch DDR type on IO96B_%d\n", __func__, i); + + return -EINVAL; + } + } + } + + return 0; +} + +int get_mem_width_info(struct io96b_info *io96b_ctrl) +{ + struct io96b_mb_req usr_req; + struct io96b_mb_resp usr_resp; + int i, j, n; + u16 memory_size; + u16 total_memory_size = 0; + + /* Get all memory interface(s) total memory size on all instance(s) */ + for (i = 0; i < io96b_ctrl->num_instance; i++) { + memory_size = 0; + for (j = 0; j < io96b_ctrl->io96b[i].mb_ctrl.num_mem_interface; j++) { + IO96B_MB_REQ_SETUP(io96b_ctrl->io96b[i].mb_ctrl.ip_type[j], + io96b_ctrl->io96b[i].mb_ctrl.ip_id[j], + CMD_GET_MEM_INFO, + GET_MEM_WIDTH_INFO, + 0); + + io96b_mb_req(io96b_ctrl->io96b[i].io96b_csr_addr, usr_req, + 2, &usr_resp); + + memory_size = memory_size + + (usr_resp.cmd_resp_data[1] & GENMASK(7, 0)); + } + + if (!memory_size) { + printf("%s: Failed to get valid memory size\n", __func__); + + return -EINVAL; + } + + io96b_ctrl->io96b[i].size = memory_size; + + total_memory_size = total_memory_size + memory_size; + } + + if (!total_memory_size) { + printf("%s: Failed to get valid memory size\n", __func__); + + return -EINVAL; + } + + io96b_ctrl->overall_size = total_memory_size; + + return 0; +} + +int ecc_enable_status(struct io96b_info *io96b_ctrl) +{ + struct io96b_mb_req usr_req; + struct io96b_mb_resp usr_resp; + int i, j, n; + bool ecc_stat_set = false; + bool ecc_stat; + + /* Initialize ECC status */ + io96b_ctrl->ecc_status = false; + + /* Get and ensure all memory interface(s) same ECC status */ + for (i = 0; i < io96b_ctrl->num_instance; i++) { + for (j = 0; j < io96b_ctrl->io96b[i].mb_ctrl.num_mem_interface; j++) { + IO96B_MB_REQ_SETUP(io96b_ctrl->io96b[i].mb_ctrl.ip_type[j], + io96b_ctrl->io96b[i].mb_ctrl.ip_id[j], + CMD_TRIG_CONTROLLER_OP, + ECC_ENABLE_STATUS, + 0); + + io96b_mb_req(io96b_ctrl->io96b[i].io96b_csr_addr, usr_req, 0, &usr_resp); + + ecc_stat = (IOSSM_CMD_RESPONSE_DATA_SHORT(usr_resp.cmd_resp_status) + & GENMASK(1, 0)) == 0 ? false : true; + + if (!ecc_stat_set) { + io96b_ctrl->ecc_status = ecc_stat; + ecc_stat_set = true; + } + + if (ecc_stat != io96b_ctrl->ecc_status) { + printf("%s: Mismatch DDR ECC status on IO96B_%d\n", __func__, i); + + return -EINVAL; + } + } + } + + debug("%s: ECC enable status: %d\n", __func__, io96b_ctrl->ecc_status); + + return 0; +} + +int bist_mem_init_start(struct io96b_info *io96b_ctrl) +{ + struct io96b_mb_req usr_req; + struct io96b_mb_resp usr_resp; + int i, j, n; + bool bist_start, bist_success; + u32 start; + + /* Full memory initialization BIST performed on all memory interface(s) */ + for (i = 0; i < io96b_ctrl->num_instance; i++) { + for (j = 0; j < io96b_ctrl->io96b[i].mb_ctrl.num_mem_interface; j++) { + bist_start = false; + bist_success = false; + + /* Start memory initialization BIST on full memory address */ + IO96B_MB_REQ_SETUP(io96b_ctrl->io96b[i].mb_ctrl.ip_type[j], + io96b_ctrl->io96b[i].mb_ctrl.ip_id[j], + CMD_TRIG_CONTROLLER_OP, + BIST_MEM_INIT_START, + BIST_FULL_MEM); + + io96b_mb_req(io96b_ctrl->io96b[i].io96b_csr_addr, usr_req, 0, &usr_resp); + + bist_start = IOSSM_CMD_RESPONSE_DATA_SHORT(usr_resp.cmd_resp_status) + & BIT(0); + + if (!bist_start) { + printf("%s: Failed to initialize memory on IO96B_%d\n", __func__, + i); + printf("%s: BIST_MEM_INIT_START Error code 0x%lx\n", __func__, + IOSSM_STATUS_CMD_RESPONSE_ERROR(usr_resp.cmd_resp_status)); + + return -EINVAL; + } + + /* Polling for the initiated memory initialization BIST status */ + start = get_timer(0); + while (!bist_success) { + IO96B_MB_REQ_SETUP(io96b_ctrl->io96b[i].mb_ctrl.ip_type[j], + io96b_ctrl->io96b[i].mb_ctrl.ip_id[j], + CMD_TRIG_CONTROLLER_OP, + BIST_MEM_INIT_STATUS, + 0); + + io96b_mb_req(io96b_ctrl->io96b[i].io96b_csr_addr, usr_req, 0, + &usr_resp); + + bist_success = + IOSSM_CMD_RESPONSE_DATA_SHORT(usr_resp.cmd_resp_status) + & BIT(0); + + if (!bist_success && (get_timer(start) > TIMEOUT)) { + printf("%s: Timeout initialize memory on IO96B_%d\n", + __func__, i); + printf("%s: BIST_MEM_INIT_STATUS Error code 0x%lx\n", + __func__, + IOSSM_STATUS_CMD_RESPONSE_ERROR(usr_resp.cmd_resp_status)); + + return -ETIMEDOUT; + } + + udelay(1); + } + } + + debug("%s: Memory initialized successfully on IO96B_%d\n", __func__, i); + } + return 0; +} diff --git a/drivers/ddr/altera/iossm_mailbox.h b/drivers/ddr/altera/iossm_mailbox.h new file mode 100644 index 0000000000..2a10b0dba6 --- /dev/null +++ b/drivers/ddr/altera/iossm_mailbox.h @@ -0,0 +1,182 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2024 Intel Corporation + */ + +#define TIMEOUT_120000MS 120000 +#define TIMEOUT TIMEOUT_120000MS +#define IOSSM_STATUS_CAL_SUCCESS BIT(0) +#define IOSSM_STATUS_CAL_FAIL BIT(1) +#define IOSSM_STATUS_CAL_BUSY BIT(2) +#define IOSSM_STATUS_COMMAND_RESPONSE_READY BIT(0) +#define IOSSM_CMD_RESPONSE_STATUS_OFFSET 0x45C +#define IOSSM_CMD_RESPONSE_DATA_0_OFFSET 0x458 +#define IOSSM_CMD_RESPONSE_DATA_1_OFFSET 0x454 +#define IOSSM_CMD_RESPONSE_DATA_2_OFFSET 0x450 +#define IOSSM_CMD_REQ_OFFSET 0x43C +#define IOSSM_CMD_PARAM_0_OFFSET 0x438 +#define IOSSM_CMD_PARAM_1_OFFSET 0x434 +#define IOSSM_CMD_PARAM_2_OFFSET 0x430 +#define IOSSM_CMD_PARAM_3_OFFSET 0x42C +#define IOSSM_CMD_PARAM_4_OFFSET 0x428 +#define IOSSM_CMD_PARAM_5_OFFSET 0x424 +#define IOSSM_CMD_PARAM_6_OFFSET 0x420 +#define IOSSM_STATUS_OFFSET 0x400 +#define IOSSM_CMD_RESPONSE_DATA_SHORT_MASK GENMASK(31, 16) +#define IOSSM_CMD_RESPONSE_DATA_SHORT(n) FIELD_GET(IOSSM_CMD_RESPONSE_DATA_SHORT_MASK, n) +#define IOSSM_STATUS_CMD_RESPONSE_ERROR_MASK GENMASK(7, 5) +#define IOSSM_STATUS_CMD_RESPONSE_ERROR(n) FIELD_GET(IOSSM_STATUS_CMD_RESPONSE_ERROR_MASK, n) +#define IOSSM_STATUS_GENERAL_ERROR_MASK GENMASK(4, 1) +#define IOSSM_STATUS_GENERAL_ERROR(n) FIELD_GET(IOSSM_STATUS_GENERAL_ERROR_MASK, n) +#define MAX_IO96B_SUPPORTED 2 +#define NUM_CMD_RESPONSE_DATA 3 +#define NUM_CMD_PARAM 6 + +/* supported mailbox command type */ +enum iossm_mailbox_cmd_type { + CMD_NOP, + CMD_GET_SYS_INFO, + CMD_GET_MEM_INFO, + CMD_GET_MEM_CAL_INFO, + CMD_TRIG_CONTROLLER_OP, + CMD_TRIG_MEM_CAL_OP +}; + +/* supported mailbox command opcode */ +enum iossm_mailbox_cmd_opcode { + GET_MEM_INTF_INFO = 0x0001, + GET_MEM_TECHNOLOGY, + GET_MEMCLK_FREQ_KHZ, + GET_MEM_WIDTH_INFO, + ECC_ENABLE_SET = 0x0101, + ECC_ENABLE_STATUS, + ECC_INTERRUPT_STATUS, + ECC_INTERRUPT_ACK, + ECC_INTERRUPT_MASK, + ECC_WRITEBACK_ENABLE, + ECC_SCRUB_IN_PROGRESS_STATUS = 0x0201, + ECC_SCRUB_MODE_0_START, + ECC_SCRUB_MODE_1_START, + BIST_STANDARD_MODE_START = 0x0301, + BIST_RESULTS_STATUS, + BIST_MEM_INIT_START, + BIST_MEM_INIT_STATUS, + BIST_SET_DATA_PATTERN_UPPER, + BIST_SET_DATA_PATTERN_LOWER, + TRIG_MEM_CAL = 0x000a, + GET_MEM_CAL_STATUS +}; + +/* response data of cmd opcode GET_MEM_INTF_INFO */ +#define INTF_IP_TYPE_MASK GENMASK(31, 29) +#define INTF_INSTANCE_ID_MASK GENMASK(28, 24) + +/* response data of cmd opcode GET_MEM_CAL_STATUS */ +#define INTF_UNUSED 0x0 +#define INTF_MEM_CAL_STATUS_SUCCESS 0x1 +#define INTF_MEM_CAL_STATUS_FAIL 0x2 +#define INTF_MEM_CAL_STATUS_ONGOING 0x4 + +/* cmd opcode BIST_MEM_INIT_START, BIST performed on full memory address range */ +#define BIST_FULL_MEM BIT(6) + +/* + * IOSSM mailbox required information + * + * @num_mem_interface: Number of memory interfaces instantiated + * @ip_type: IP type implemented on the IO96B + * @ip_instance_id: IP identifier for every IP instance implemented on the IO96B + */ +struct io96b_mb_ctrl { + u32 num_mem_interface; + u32 ip_type[2]; + u32 ip_id[2]; +}; + +/* CMD_REQ Register Definition */ +#define CMD_TARGET_IP_TYPE_MASK GENMASK(31, 29) +#define CMD_TARGET_IP_INSTANCE_ID_MASK GENMASK(28, 24) +#define CMD_TYPE_MASK GENMASK(23, 16) +#define CMD_OPCODE_MASK GENMASK(15, 0) + +/* + * IOSSM mailbox request + * @ip_type: IP type for the specified memory interface + * @ip_id: IP instance ID for the specified memory interface + * @usr_cmd_type: User desire IOSSM mailbox command type + * @usr_cmd_opcode: User desire IOSSM mailbox command opcode + * @cmd_param_*: Parameters (if applicable) for the requested IOSSM mailbox command + */ +struct io96b_mb_req { + u32 ip_type; + u32 ip_id; + u32 usr_cmd_type; + u32 usr_cmd_opcode; + u32 cmd_param[NUM_CMD_PARAM]; +}; + +/* + * IOSSM mailbox response outputs + * + * @cmd_resp_status: Command Interface status + * @cmd_resp_data_*: More spaces for command response + */ +struct io96b_mb_resp { + u32 cmd_resp_status; + u32 cmd_resp_data[NUM_CMD_RESPONSE_DATA]; +}; + +/* + * IO96B instance specific information + * + * @size: Memory size + * @io96b_csr_addr: IO96B instance CSR address + * @cal_status: IO96B instance calibration status + * @mb_ctrl: IOSSM mailbox required information + */ +struct io96b_instance { + u16 size; + phys_addr_t io96b_csr_addr; + bool cal_status; + struct io96b_mb_ctrl mb_ctrl; +}; + +/* + * Overall IO96B instance(s) information + * + * @num_instance: Number of instance(s) assigned to HPS + * @overall_cal_status: Overall calibration status for all IO96B instance(s) + * @ddr_type: DDR memory type + * @ecc_status: ECC enable status (false = disabled, true = enabled) + * @overall_size: Total DDR memory size + * @io96b[]: IO96B instance specific information + * @ckgen_lock: IO96B GEN PLL lock (false = not locked, true = locked) + * @num_port: Number of IO96B port. Example bit 0 represent port 0, bit 1 represent port 1, and so on + * @io96b_pll: Selected IO96B PLL. Example bit 0: EMIF0 PLL A selected, + * bit 1: EMIF0 PLL B selected, bit 2 - EMIF1 PLL A selected, + * bit 3: EMIF1 PLL B selected + */ +struct io96b_info { + u8 num_instance; + bool overall_cal_status; + const char *ddr_type; + bool ecc_status; + u16 overall_size; + struct io96b_instance io96b[MAX_IO96B_SUPPORTED]; + bool ckgen_lock; + u8 num_port; + u8 io96b_pll; +}; + +int io96b_mb_req(phys_addr_t io96b_csr_addr, struct io96b_mb_req req, + u32 resp_data_len, struct io96b_mb_resp *resp); + +/* Supported IOSSM mailbox function */ +void io96b_mb_init(struct io96b_info *io96b_ctrl); +int io96b_cal_status(phys_addr_t addr); +void init_mem_cal(struct io96b_info *io96b_ctrl); +int trig_mem_cal(struct io96b_info *io96b_ctrl); +int get_mem_technology(struct io96b_info *io96b_ctrl); +int get_mem_width_info(struct io96b_info *io96b_ctrl); +int ecc_enable_status(struct io96b_info *io96b_ctrl); +int bist_mem_init_start(struct io96b_info *io96b_ctrl); From patchwork Fri May 17 05:26:54 2024 Content-Type: text/plain; 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d="scan'208";a="11930002" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 May 2024 22:28:09 -0700 X-CSE-ConnectionGUID: Yyy/mMB+Q8WObKO5Weukyw== X-CSE-MsgGUID: 0Y8PZ29PSD66ed6wVVmCEQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,166,1712646000"; d="scan'208";a="36188282" Received: from pglc00543.png.intel.com ([10.221.239.235]) by fmviesa003.fm.intel.com with ESMTP; 16 May 2024 22:28:04 -0700 From: tingting.meng@intel.com To: u-boot@lists.denx.de Cc: Lukasz Majewski , Sean Anderson , Rayagonda Kokatanur , Tom Rini , Marek , Simon , Tien Fong , Kok Kiang , Dinesh , Boon Khai , Alif , Teik Heng , Hazim , Jit Loon Lim , Sieu Mun Tang , Tingting Meng Subject: [Agilex7 M-series Platform Enablement v1 09/16] ddr: altera: Add uibssm mailbox for Agilex7 M-series Date: Fri, 17 May 2024 13:26:54 +0800 Message-Id: <20240517052701.12949-10-tingting.meng@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240517052701.12949-1-tingting.meng@intel.com> References: <20240517052701.12949-1-tingting.meng@intel.com> MIME-Version: 1.0 X-Mailman-Approved-At: Fri, 17 May 2024 14:50:41 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Teik Heng Chong Add uibssm mailbox driver for Agilex7 M-series. HPS will interact with UIB and HBM subsystem through software defined mailbox interface. HPS can retrieve memory interface calibration status, UIB configuration, memory interfae configuration, trigger calibration and etc with the list of supported mailbox command type and opcode. Signed-off-by: Teik Heng Chong Signed-off-by: Tingting Meng --- drivers/ddr/altera/uibssm_mailbox.c | 311 ++++++++++++++++++++++++++++ drivers/ddr/altera/uibssm_mailbox.h | 117 +++++++++++ 2 files changed, 428 insertions(+) create mode 100644 drivers/ddr/altera/uibssm_mailbox.c create mode 100644 drivers/ddr/altera/uibssm_mailbox.h diff --git a/drivers/ddr/altera/uibssm_mailbox.c b/drivers/ddr/altera/uibssm_mailbox.c new file mode 100644 index 0000000000..a6e2a5f44b --- /dev/null +++ b/drivers/ddr/altera/uibssm_mailbox.c @@ -0,0 +1,311 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 Intel Corporation + */ +#include +#include +#include +#include +#include "uibssm_mailbox.h" + +#define MAX_RETRIES 3 + +int uib_bist_mem_init_start(struct uib_info *uib_ctrl) +{ + struct uib_mb_resp usr_resp; + bool bist_start = false; + bool bist_success = false; + u32 start; + + /* + * Full memory initialization BIST performed on all UIB channels + * start memory initialization BIST on full memory address + */ + uib_mb_req(uib_ctrl->uib[0].uib_csr_addr, + UIB_CMD_TRIG_CONTROLLER_OP, + UIB_BIST_MEM_INIT_START, + UIB_BIST_FULL_MEM, &usr_resp); + + bist_start = UIBSSM_CMD_RESPONSE_DATA_SHORT(usr_resp.cmd_resp_status) & + UIB_BIST_INITIATE_PASS; + if (!bist_start) { + printf("%s: Failed to initialized memory on UIB\n", __func__); + + return -EINVAL; + } + + /* Polling for the initiated memory initialization BIST status */ + start = get_timer(0); + while (!bist_success) { + /* + * cmd_param_0 is not used in BIST status request, + * hence set the value to 0 + */ + uib_mb_req(uib_ctrl->uib[0].uib_csr_addr, + UIB_CMD_TRIG_CONTROLLER_OP, + UIB_BIST_MEM_INIT_STATUS, + 0, &usr_resp); + + bist_success = UIBSSM_CMD_RESPONSE_DATA_SHORT(usr_resp.cmd_resp_status) & BIT(0); + if (!bist_success && (get_timer(start) > TIMEOUT)) { + printf("%s: Timeout initialize memory on UIB\n", __func__); + + return -ETIMEDOUT; + } + + udelay(1); + } + + debug("%s: Memory initialized successfully on UIB\n", __func__); + + return 0; +} + +int uib_cal_status(phys_addr_t addr) +{ + int ret = 0; + phys_addr_t status_addr = addr + UIB_R_INITSTS_OFFSET; + + /* Ensure calibration completed */ + ret = wait_for_bit_le32((const void *)status_addr, UIB_R_INITSTS_INITSTS_PASS, true, + TIMEOUT, false); + if (ret) + printf("%s: HBM calibration UIB instance 0x%llx timeout\n", __func__, status_addr); + + return ret; +} + +void uib_init_mem_cal(struct uib_info *uib_ctrl) +{ + int i, ret; + + if (!uib_ctrl->num_instance) { + uib_ctrl->overall_cal_status = false; + } else { + uib_ctrl->overall_cal_status = true; + + /* Check initial calibration status for the assigned UIB */ + for (i = 0; i < uib_ctrl->num_instance; i++) { + ret = uib_cal_status(uib_ctrl->uib[i].uib_csr_addr); + if (ret) { + uib_ctrl->uib[i].cal_status = false; + uib_ctrl->overall_cal_status = false; + + printf("%s: Initial HBM calibration UIB_%d failed\n", __func__, i); + break; + } + + uib_ctrl->uib[i].cal_status = true; + + debug("%s: Initial HBM calibration UIB_%d succeed\n", __func__, i); + } + } +} + +/* Trying 3 times re-calibration if initial calibration failed */ +void uib_trig_mem_cal(struct uib_info *uib_ctrl) +{ + int i, j, cal_stat; + + if (!uib_ctrl->num_instance) { + uib_ctrl->overall_cal_status = false; + } else { + uib_ctrl->overall_cal_status = true; + + for (i = 0; i < uib_ctrl->num_instance; i++) { + uib_ctrl->uib[i].cal_status = false; + + /* Initiate Re-calibration */ + for (j = 0; j < MAX_RETRIES; j++) { + clrsetbits_le32(uib_ctrl->uib[i].uib_csr_addr + + UIB_R_INITCTL_OFFSET, + UIB_R_INITCTL_INITTYPE_MASK | + UIB_R_INITCTL_INITREQ_MASK, + UIB_R_INITCTL_INITTYPE(UIB_RST_REQUEST_WITH_CAL) | + UIB_R_INITCTL_INITREQ(1)); + + cal_stat = uib_cal_status(uib_ctrl->uib[i].uib_csr_addr); + if (cal_stat) + continue; + + debug("%s: HBM re-calibration UIB_%d succeed\n", __func__, i); + + uib_ctrl->uib[i].cal_status = true; + break; + } + + if (!uib_ctrl->uib[i].cal_status) { + uib_ctrl->overall_cal_status = false; + + printf("%s: HBM re-calibration UIB_%d failed\n", __func__, i); + break; + } + } + } +} + +static void uib_mailbox_write_request(u32 data, u32 target_write_addr, phys_addr_t csr_addr) +{ + int ret; + + /* + * Read from chms0020 MBWRADDR_VALID and ensure its not set or + * wait till it get cleared by controller + */ + debug("%s: #1 Read MBWRADDR_VALID from UIB_R_MBWRCTL\n", __func__); + ret = wait_for_bit_le32((const void *)csr_addr + UIB_R_MBWRCTL, + UIB_R_MBWRCTL_MBWRADDR_VALID, false, TIMEOUT, false); + if (ret) { + printf("%s: TIMEOUT!!! MBWRADDR_VALID is not zero\n", __func__); + + hang(); + } + + /* Write to chms0024 MBWRADDR */ + debug("%s: #2 Write 0x%x to UIB_R_MBWRADDR\n", __func__, target_write_addr); + writel(target_write_addr, csr_addr + UIB_R_MBWRADDR); + + /* + * Write 1 to chms0020 MBWRADDR_VALID to indicate the address is now valid + * for FW to read + */ + debug("%s: #3 Write 1 to MBWRADDR_VALID for FW to read address\n", __func__); + setbits_le32(csr_addr + UIB_R_MBWRCTL, UIB_R_MBWRCTL_MBWRADDR_VALID); + + /* + * Read from chms0020 MBWRDATA_VALID and ensure its not set or + * wait till it get cleared by controller + */ + debug("%s: #4 Read MBWRDATA_VALID from UIB_R_MBWRCTL\n", __func__); + ret = wait_for_bit_le32((const void *)csr_addr + UIB_R_MBWRCTL, + UIB_R_MBWRCTL_MBWRDATA_VALID, false, TIMEOUT, false); + if (ret) { + printf("%s: TIMEOUT!!! MBWRADDR_VALID is not zero\n", __func__); + + hang(); + } + + /* + * Read from chms0020 MBWRDATA_END and ensure its not set or + * wait till it get cleared by controller + */ + debug("%s: #5 Read R_MBWRCTL_MBWRDATA_END from UIB_R_MBWRCTL\n", __func__); + ret = wait_for_bit_le32((const void *)csr_addr + UIB_R_MBWRCTL, + UIB_R_MBWRCTL_MBWRDATA_END, false, TIMEOUT, false); + if (ret) { + printf("%s: TIMEOUT!!! MBWRDATA_END is not zero\n", __func__); + + hang(); + } + + /* Write to chms0028 MMR_MBWRDATA */ + debug("%s: #6 Write 0x%x to UIB_R_MBWRDATA\n", __func__, data); + writel(data, csr_addr + UIB_R_MBWRDATA); + + /* + * Write 1 to chms0020 MBWRDATA_END to indicate if the is the last burst + * for FW to read for the + */ + debug("%s: #7 Write 1 to MBWRDATA_END to inform FW this is last burst of data to read\n", + __func__); + setbits_le32(csr_addr + UIB_R_MBWRCTL, UIB_R_MBWRCTL_MBWRDATA_END); + + /* Write 1 to chms0020 MBWRDATA_VALID to indicate the data is now valid for FW to read */ + debug("%s: #8 Write 1 to MBWRDATA_VALID for FW to read data\n", __func__); + setbits_le32(csr_addr + UIB_R_MBWRCTL, UIB_R_MBWRCTL_MBWRDATA_VALID); +} + +static u32 uib_mailbox_read_request(u32 target_read_addr, phys_addr_t csr_addr) +{ + int ret; + u32 reg, rd_data = 0; + + /* + * Read from chms0030 MBRDADDR_VALID and ensure its not set or + * wait till it get cleared by controller + */ + debug("%s: #1 Read MBRDADDR_VALID from UIB_R_MBRDCTL\n", __func__); + ret = wait_for_bit_le32((const void *)csr_addr + UIB_R_MBRDCTL, + UIB_R_MBRDCTL_MBRDADDR_VALID, false, TIMEOUT, false); + if (ret) { + printf("%s: TIMEOUT!!! MBRDADDR_VALID is not zero\n", __func__); + + hang(); + } + + /* Write to chms0034 MBRDADDR */ + debug("%s: #2 Write 0x%x to UIB_R_MBRDADDR\n", __func__, target_read_addr); + writel(target_read_addr, csr_addr + UIB_R_MBRDADDR); + + /* + * Write 1 to chms0030 MBRDADDR_VALID to indicate the address is now valid + * for FW to read + */ + debug("%s: #3 Write 1 to MBRDADDR_VALID for FW to read address\n", __func__); + setbits_le32(csr_addr + UIB_R_MBRDCTL, UIB_R_MBRDCTL_MBRDADDR_VALID); + + /* + * Continuously poll the chms0030 MBRDDATA_VALID. If MBRDDATA_VALID are set, read + * chms0038 MBRDDATA and chms0030 MBRDDATA_END to retrieve the and + * status accordingly + */ + debug("%s: #4 Read MBRDDATA_VALID from UIB_R_MBRDCTL\n", __func__); + ret = wait_for_bit_le32((const void *)csr_addr + UIB_R_MBRDCTL, + UIB_R_MBRDCTL_MBRDDATA_VALID, false, TIMEOUT, false); + if (ret) { + printf("%s: TIMEOUT!!! MBRDDATA_VALID is not zero\n", __func__); + + hang(); + } + + reg = readl(csr_addr + UIB_R_MBRRDATA); + debug("%s: #5 Read data from UIB_R_MBRRDATA = 0x%x\n", __func__, reg); + rd_data = reg; + + reg = readl(csr_addr + UIB_R_MBRDCTL); + debug("%s: #6 Read end of read burst status from UIB_R_MBRDCTL = 0x%x\n", __func__, reg); + + /* + * Once done retrieving the data, write 1 to chms0030 MBRDDATA_VALID, + * chms0030 MBRDDATA_END to clear the register + */ + debug("%s: #7 Write 1 to MBRDDATA_VALID for FW to read address\n", __func__); + setbits_le32(csr_addr + UIB_R_MBRDCTL, UIB_R_MBRDCTL_MBRDDATA_VALID | + UIB_R_MBWRCTL_MBWRDATA_END); + + return rd_data; +} + +int uib_mb_req(phys_addr_t uib_csr_addr, u32 usr_cmd_type, u32 usr_cmd_opcode, + u32 cmd_param_0, struct uib_mb_resp *resp) +{ + u32 cmd_req; + + /* Initialized zeros for responses */ + resp->cmd_resp_status = 0; + + /* Write CMD_REQ (CMD_TYPE and CMD_OPCODE) */ + cmd_req = FIELD_PREP(CMD_TYPE_MASK, usr_cmd_type) | + FIELD_PREP(CMD_OPCODE_MASK, usr_cmd_opcode); + uib_mailbox_write_request(cmd_req, 0, uib_csr_addr); + + debug("%s: Write 0x%x to UIBSSM_CMD_REQ_OFFSET 0x%llx\n", __func__, cmd_req, uib_csr_addr); + + /* Write CMD_PARAM_* */ + if (cmd_param_0) + uib_mailbox_write_request(cmd_param_0, 0, uib_csr_addr); + else + debug("%s: cmd_param_0 is NULL\n", __func__); + + /* read CMD_RESPONSE_STATUS */ + resp->cmd_resp_status = uib_mailbox_read_request(0, uib_csr_addr); + + debug("%s: CMD_RESPONSE_STATUS 0x%llx: 0x%x\n", __func__, + uib_csr_addr, resp->cmd_resp_status); + debug("%s: STATUS_CMD_RESPONSE_ERROR: 0x%lx\n", __func__, + UIBSSM_CMD_RESPONSE_ERROR(resp->cmd_resp_status)); + debug("%s: STATUS_GENERAL_ERROR: 0x%lx\n", __func__, + UIBSSM_GENERAL_ERROR(resp->cmd_resp_status)); + + return 0; +} diff --git a/drivers/ddr/altera/uibssm_mailbox.h b/drivers/ddr/altera/uibssm_mailbox.h new file mode 100644 index 0000000000..5d0dc0f475 --- /dev/null +++ b/drivers/ddr/altera/uibssm_mailbox.h @@ -0,0 +1,117 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2024 Intel Corporation + */ +#include + +#define TIMEOUT_120000MS 120000 +#define TIMEOUT TIMEOUT_120000MS + +#define UIBSSM_CMD_RESPONSE_DATA_SHORT_MASK GENMASK(31, 16) +#define UIBSSM_CMD_RESPONSE_DATA_SHORT(x) FIELD_GET(UIBSSM_CMD_RESPONSE_DATA_SHORT_MASK, x) +#define UIBSSM_CMD_RESPONSE_ERROR_MASK GENMASK(7, 5) +#define UIBSSM_CMD_RESPONSE_ERROR(x) FIELD_GET(UIBSSM_CMD_RESPONSE_ERROR_MASK, x) +#define UIBSSM_GENERAL_ERROR_MASK GENMASK(4, 1) +#define UIBSSM_GENERAL_ERROR(x) FIELD_GET(UIBSSM_GENERAL_ERROR_MASK, x) + +/* UIB Responder Initialization Control Register */ +#define UIB_R_INITCTL_OFFSET 0x10 +#define UIB_R_INITCTL_INITREQ_MASK BIT(0) +#define UIB_R_INITCTL_INITTYPE_MASK GENMASK(11, 8) +#define UIB_R_INITCTL_INITREQ(x) FIELD_PREP(UIB_R_INITCTL_INITREQ_MASK, x) +#define UIB_R_INITCTL_INITTYPE(x) FIELD_PREP(UIB_R_INITCTL_INITTYPE_MASK, x) +#define UIB_RST_REQUEST_WITH_CAL 5 + +/* UIB Initialization control and status registers */ +#define UIB_R_INITSTS_OFFSET 0x14 +#define UIB_R_INITSTS_INITSTS_PASS BIT(1) +#define MAX_UIB_SUPPORTED 8 + +#define UIB_R_MBWRCTL 0x20 +#define UIB_R_MBWRADDR 0x24 +#define UIB_R_MBWRDATA 0x28 +#define UIB_R_MBWRCTL_MBWRADDR_VALID BIT(0) +#define UIB_R_MBWRCTL_MBWRDATA_VALID BIT(4) +#define UIB_R_MBWRCTL_MBWRDATA_END BIT(7) + +#define UIB_R_MBRDCTL 0x30 +#define UIB_R_MBRDADDR 0x34 +#define UIB_R_MBRRDATA 0x38 +#define UIB_R_MBRDCTL_MBRDADDR_VALID BIT(0) +#define UIB_R_MBRDCTL_MBRDDATA_VALID BIT(4) +#define UIB_R_MBRDCTL_MBRDDATA_END BIT(7) + +/* Responder Error Mask Register */ +#define UIB_R_ERRMSK_PSEUDO_CH0_OFFSET 0x520 +#define UIB_R_ERRMSK_PSEUDO_CH1_OFFSET 0X820 +#define UIB_DRAM_SBE_MSK BIT(25) +#define UIB_INTERNAL_CORR_ERR_MSK BIT(30) +#define UIB_DRAM_SBE(x) FIELD_PREP(UIB_DRAM_SBE_MSK, x) +#define UIB_INTERNAL_CORR_ERR(x) FIELD_PREP(UIB_INTERNAL_CORR_ERR_MSK, x) + +/* CMD_REQ Register Definition */ +#define CMD_TYPE_MASK GENMASK(23, 16) +#define CMD_OPCODE_MASK GENMASK(15, 0) + +/* supported mailbox command type */ +enum uibssm_mailbox_cmd_type { + UIB_CMD_TRIG_CONTROLLER_OP = 0x04 +}; + +/* supported mailbox command opcode */ +enum uibssm_mailbox_cmd_opcode { + UIB_BIST_MEM_INIT_START = 0x0303, + UIB_BIST_MEM_INIT_STATUS +}; + +/* CMD_PARAM_0 for opcode UIB_BIST_MEM_INIT_START */ +#define UIB_BIST_FULL_MEM BIT(6) + +/* UIBSSM_CMD_RESPONSE_DATA_SHORT for opcode UIB_BIST_MEM_INIT_START */ +#define UIB_BIST_INITIATE_PASS BIT(0) + +/* + * UIBSSM mailbox response outputs + * + * @cmd_resp_status: Command Interface status + */ +struct uib_mb_resp { + u32 cmd_resp_status; +}; + +/* + * UIB instance specific information + * + * @uib_csr_addr: UIB instance CSR address + * @cal_status: UIB instance calibration status + */ +struct uib_instance { + phys_addr_t uib_csr_addr; + bool cal_status; +}; + +/* + * Overall UIB instance(s) information + * + * @num_instance: Number of instance(s) assigned to HPS + * @overall_cal_status: Overall calibration status for all UIB instance(s) + * @ecc_status: ECC enable status (false = disabled, true = enabled) + * @overall_size: Total HBM memory size + * @uib: UIB instance specific information + */ +struct uib_info { + u8 num_instance; + bool overall_cal_status; + bool ecc_status; + u16 overall_size; + struct uib_instance uib[MAX_UIB_SUPPORTED]; +}; + +/* Supported UIB function */ +int uib_mb_req(phys_addr_t uib_csr_addr, + u32 usr_cmd_type, u32 usr_cmd_opcode, + u32 cmd_param_0, struct uib_mb_resp *resp); +int uib_cal_status(phys_addr_t addr); +void uib_init_mem_cal(struct uib_info *uib_ctrl); +void uib_trig_mem_cal(struct uib_info *uib_ctrl); +int uib_bist_mem_init_start(struct uib_info *uib_ctrl); From patchwork Fri May 17 05:26:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Meng, Tingting" X-Patchwork-Id: 1936439 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=Yubf0lKd; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; 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16 May 2024 22:28:09 -0700 From: tingting.meng@intel.com To: u-boot@lists.denx.de Cc: Lukasz Majewski , Sean Anderson , Rayagonda Kokatanur , Tom Rini , Marek , Simon , Tien Fong , Kok Kiang , Dinesh , Boon Khai , Alif , Teik Heng , Hazim , Jit Loon Lim , Sieu Mun Tang , Wan Yee Lau , Tingting Meng Subject: [Agilex7 M-series Platform Enablement v1 10/16] ddr: altera: Add DDR driver for Agilex7 M-series Date: Fri, 17 May 2024 13:26:55 +0800 Message-Id: <20240517052701.12949-11-tingting.meng@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240517052701.12949-1-tingting.meng@intel.com> References: <20240517052701.12949-1-tingting.meng@intel.com> MIME-Version: 1.0 X-Mailman-Approved-At: Fri, 17 May 2024 14:50:41 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Wan Yee Lau This is for new platform enablement for Agilex7 M-series. Add DDR driver for Agilex7 M-series. This driver is designed to support DDR and HBM memory. The official HBM handoff is not ready yet, therefore hardcoded handoff is used for HBM driver validation on mUDV board. Signed-off-by: Wan Yee Lau Signed-off-by: Teik Heng Chong Signed-off-by: Tingting Meng --- .../include/mach/base_addr_soc64.h | 6 +- .../include/mach/system_manager_soc64.h | 7 +- drivers/ddr/altera/Makefile | 3 +- drivers/ddr/altera/sdram_agilex7m.c | 527 ++++++++++++++++++ drivers/ddr/altera/sdram_soc64.c | 15 +- drivers/ddr/altera/sdram_soc64.h | 15 +- 6 files changed, 565 insertions(+), 8 deletions(-) create mode 100644 drivers/ddr/altera/sdram_agilex7m.c diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h index 65721098b2..1f935fcdec 100644 --- a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h @@ -45,12 +45,15 @@ #define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xf8000400 #define SOCFPGA_HMC_MMR_IO48_ADDRESS 0xf8010000 #define SOCFPGA_SDR_ADDRESS 0xf8011000 +#define SOCFPGA_FW_MPFE_SCR_ADDRESS 0xf8020000 #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || \ - IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) + IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) || \ + IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) #define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020200 #else #define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020100 #endif +#define SOCFPGA_F2SDRAM_MGR_ADDRESS 0xf8024000 #define SOCFPGA_SMMU_ADDRESS 0xfa000000 #define SOCFPGA_MAILBOX_ADDRESS 0xffa30000 #define SOCFPGA_UART0_ADDRESS 0xffc02000 @@ -74,6 +77,7 @@ #define SOCFPGA_FIREWALL_SOC2FPGA 0xffd21200 #define SOCFPGA_FIREWALL_LWSOC2FPGA 0xffd21300 #define SOCFPGA_FIREWALL_TCU 0xffd21400 +#define SOCFPGA_FIREWALL_PRIV_MEMORYMAP_PRIV 0xffd24800 #define SOCFPGA_DMANONSECURE_ADDRESS 0xffda0000 #define SOCFPGA_DMASECURE_ADDRESS 0xffda1000 #define SOCFPGA_OCRAM_ADDRESS 0xffe00000 diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h index a8009664fe..815bdf8ce1 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2019-2021 Intel Corporation + * Copyright (C) 2019-2024 Intel Corporation */ #ifndef _SYSTEM_MANAGER_SOC64_H_ @@ -103,6 +103,11 @@ void populate_sysmgr_pinmux(void); #define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_MASK (BIT(29) | BIT(28)) #define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_SHIFT 28 +#define ALT_SYSMGR_SCRATCH_REG_8_DDR_DBE_MASK BIT(31) +#define ALT_SYSMGR_SCRATCH_REG_8_DDR_PROGRESS_MASK BIT(30) +#define ALT_SYSMGR_SCRATCH_REG_8_OCRAM_DBE_MASK BIT(29) +#define ALT_SYSMGR_SCRATCH_REG_8_IO96B_HPS_MASK GENMASK(28, 27) + #define SYSMGR_SDMMC SYSMGR_SOC64_SDMMC #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0) diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile index 9fa5d85a27..1dac088b39 100644 --- a/drivers/ddr/altera/Makefile +++ b/drivers/ddr/altera/Makefile @@ -4,7 +4,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2010, Thomas Chou -# Copyright (C) 2014-2021 Altera Corporation +# Copyright (C) 2014-2024 Altera Corporation ifdef CONFIG_$(SPL_)ALTERA_SDRAM obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o @@ -12,4 +12,5 @@ obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += sdram_soc64.o sdram_s10.o obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += sdram_soc64.o sdram_agilex.o obj-$(CONFIG_TARGET_SOCFPGA_N5X) += sdram_soc64.o sdram_n5x.o +obj-$(CONFIG_TARGET_SOCFPGA_AGILEX7M) += sdram_soc64.o sdram_agilex7m.o iossm_mailbox.o uibssm_mailbox.o endif diff --git a/drivers/ddr/altera/sdram_agilex7m.c b/drivers/ddr/altera/sdram_agilex7m.c new file mode 100644 index 0000000000..4d585501e6 --- /dev/null +++ b/drivers/ddr/altera/sdram_agilex7m.c @@ -0,0 +1,527 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 Intel Corporation + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "iossm_mailbox.h" +#include "uibssm_mailbox.h" +#include "sdram_soc64.h" + +/* NOCPLL register */ +#define SYSMGR_HMC_CLK 0xB4 +#define SYSMGR_HMC_CLK_NOCPLL BIT(8) + +/* MPFE NOC registers */ +#define F2SDRAM_SIDEBAND_FLAGOUTSET0 0x50 +#define F2SDRAM_SIDEBAND_FLAGOUTSTATUS0 0x58 +#define SIDEBANDMGR_FLAGOUTSET0_REG SOCFPGA_F2SDRAM_MGR_ADDRESS +\ + F2SDRAM_SIDEBAND_FLAGOUTSET0 +#define SIDEBANDMGR_FLAGOUTSTATUS0_REG SOCFPGA_F2SDRAM_MGR_ADDRESS +\ + F2SDRAM_SIDEBAND_FLAGOUTSTATUS0 + +#define SIDEBANDMGR_FLAGOUTSET0_REG_MULTICHANNEL BIT(4) +#define SIDEBANDMGR_FLAGOUTSET0_REG_INTERLEAVING BIT(5) + +/* Reset type */ +enum reset_type { + POR_RESET, + WARM_RESET, + COLD_RESET, + NCONFIG, + JTAG_CONFIG, + RSU_RECONFIG +}; + +phys_addr_t io96b_csr_reg_addr[] = { + 0xf8400000, /* IO96B_0 CSR registers address */ + 0xf8800000 /* IO96B_1 CSR registers address */ +}; + +phys_addr_t uib_csr_reg_addr[] = { + 0xf8400000, /* UIB_0 CSR registers address */ + 0xf8410000, /* UIB_1 CSR registers address */ + 0xf8420000, /* UIB_2 CSR registers address */ + 0xf8430000, /* UIB_3 CSR registers address */ + 0xf8440000, /* UIB_4 CSR registers address */ + 0xf8450000, /* UIB_5 CSR registers address */ + 0xf8460000, /* UIB_6 CSR registers address */ + 0xf8470000 /* UIB_7 CSR registers address */ +}; + +static enum reset_type get_reset_type(u32 reg) +{ + return FIELD_GET(ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_MASK, reg); +} + +bool is_ddr_init_hang(void) +{ + u32 reg = readl(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_BOOT_SCRATCH_COLD8); + + debug("%s: 0x%x\n", __func__, reg); + + if (reg & ALT_SYSMGR_SCRATCH_REG_8_DDR_PROGRESS_MASK) + return true; + + return false; +} + +void ddr_init_inprogress(bool start) +{ + if (start) + setbits_le32(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_BOOT_SCRATCH_COLD8, + ALT_SYSMGR_SCRATCH_REG_8_DDR_PROGRESS_MASK); + else + clrbits_le32(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_BOOT_SCRATCH_COLD8, + ALT_SYSMGR_SCRATCH_REG_8_DDR_PROGRESS_MASK); +} + +static const char *memory_type_in_use(struct udevice *dev) +{ + struct altera_sdram_plat *plat = dev_get_plat(dev); + + return (plat->mem_type == DDR_MEMORY ? "DDR" : "HBM"); +} + +static bool is_ddr_in_use(struct udevice *dev) +{ + struct altera_sdram_plat *plat = dev_get_plat(dev); + + return (plat->mem_type == DDR_MEMORY ? true : false); +} + +void update_uib_assigned_to_hps(u8 num_uib_instance) +{ + u32 reg = readl(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_BOOT_SCRATCH_COLD8); + + reg = reg & ~ALT_SYSMGR_SCRATCH_REG_8_IO96B_HPS_MASK; + + writel(reg | FIELD_PREP(ALT_SYSMGR_SCRATCH_REG_8_IO96B_HPS_MASK, num_uib_instance), + socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD8); +} + +void update_io96b_assigned_to_hps(u8 num_io96b_instance) +{ + u32 reg = readl(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_BOOT_SCRATCH_COLD8); + + reg = reg & ~ALT_SYSMGR_SCRATCH_REG_8_IO96B_HPS_MASK; + + writel(reg | FIELD_PREP(ALT_SYSMGR_SCRATCH_REG_8_IO96B_HPS_MASK, num_io96b_instance), + socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD8); +} + +int populate_ddr_handoff(struct udevice *dev, struct io96b_info *io96b_ctrl, + struct uib_info *uib_ctrl) +{ + struct altera_sdram_plat *plat = dev_get_plat(dev); + int i; + u8 count = 0; + u32 len = SOC64_HANDOFF_DDR_LEN; + u32 handoff_table[len]; + + /* Read handoff for DDR configuration */ + socfpga_handoff_read((void *)SOC64_HANDOFF_DDR_BASE, handoff_table, len); + + /* Interleaving Mode */ + if (handoff_table[0] & SOC64_HANDOFF_DDR_INTERLEAVING_MODE_MASK) + plat->multichannel_interleaving = true; + else + plat->multichannel_interleaving = false; + + debug("%s: MPFE-EMIF is in %s mode\n", __func__, + plat->multichannel_interleaving ? "interleaving" : "multichannel"); + + /* Memory type */ + if (handoff_table[2] & SOC64_HANDOFF_DDR_MEMORY_TYPE_MASK) + plat->mem_type = HBM_MEMORY; + else + plat->mem_type = DDR_MEMORY; + + debug("%s: Memory type is %s\n", __func__, plat->mem_type ? "HBM" : "DDR"); + + if (plat->mem_type == HBM_MEMORY) { + /* Assign UIB CSR base address if it is valid */ + for (i = 0; i < MAX_UIB_SUPPORTED; i++) { + if (handoff_table[3] & BIT(i)) { + uib_ctrl->uib[i].uib_csr_addr = uib_csr_reg_addr[i]; + + debug("%s: UIB 0x%llx CSR enabled\n", __func__, + uib_ctrl->uib[i].uib_csr_addr); + + count++; + } + } + + uib_ctrl->num_instance = count; + update_uib_assigned_to_hps(count); + + debug("%s: returned num_instance 0x%x\n", __func__, uib_ctrl->num_instance); + + /* + * HBM memory size + * 1 UIB channel has 2 pseudo channels + * 1 pseudo channel is 1GB, hence 1 UIB channel is 2GB + */ + uib_ctrl->overall_size = uib_ctrl->num_instance * SZ_2G; + + /* UIB ECC status */ + uib_ctrl->ecc_status = handoff_table[4]; + + debug("%s: ECC status 0x%x\n", __func__, uib_ctrl->ecc_status); + } else { + /* Assign IO96B CSR base address if it is valid */ + for (i = 0; i < MAX_IO96B_SUPPORTED; i++) { + if (handoff_table[1] & BIT(i)) { + io96b_ctrl->io96b[i].io96b_csr_addr = io96b_csr_reg_addr[i]; + + debug("%s: IO96B 0x%llx CSR enabled\n", __func__, + io96b_ctrl->io96b[i].io96b_csr_addr); + + count++; + } + } + + io96b_ctrl->num_instance = count; + + update_io96b_assigned_to_hps(count); + + debug("%s: returned num_instance 0x%x\n", __func__, io96b_ctrl->num_instance); + } + + return 0; +} + +int config_mpfe_sideband_mgr(struct udevice *dev) +{ + struct altera_sdram_plat *plat = dev_get_plat(dev); + u32 reg, mask; + int ret = 0; + + if (plat->multichannel_interleaving) { + mask = SIDEBANDMGR_FLAGOUTSET0_REG_INTERLEAVING; + setbits_le32(SIDEBANDMGR_FLAGOUTSET0_REG, mask); + } else { + mask = SIDEBANDMGR_FLAGOUTSET0_REG_MULTICHANNEL; + setbits_le32(SIDEBANDMGR_FLAGOUTSET0_REG, mask); + } + + reg = readl(SIDEBANDMGR_FLAGOUTSTATUS0_REG); + + debug("%s: F2SDRAM_SIDEBAND_FLAGOUTSTATUS0: 0x%x\n", __func__, reg); + + if ((reg & mask) == SIDEBANDMGR_FLAGOUTSET0_REG_INTERLEAVING) + debug("%s: Interleaving bit is set\n", __func__); + else if ((reg & mask) == SIDEBANDMGR_FLAGOUTSET0_REG_MULTICHANNEL) + debug("%s: Multichannel bit is set\n", __func__); + else + ret = -EINVAL; + + return ret; +} + +bool hps_ocram_dbe_status(void) +{ + u32 reg = readl(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_BOOT_SCRATCH_COLD8); + + if (reg & ALT_SYSMGR_SCRATCH_REG_8_OCRAM_DBE_MASK) + return true; + + return false; +} + +bool ddr_ecc_dbe_status(void) +{ + u32 reg = readl(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_BOOT_SCRATCH_COLD8); + + if (reg & ALT_SYSMGR_SCRATCH_REG_8_DDR_DBE_MASK) + return true; + + return false; +} + +int sdram_mmr_init_full(struct udevice *dev) +{ + struct altera_sdram_plat *plat = dev_get_plat(dev); + struct altera_sdram_priv *priv = dev_get_priv(dev); + struct io96b_info *io96b_ctrl = malloc(sizeof(*io96b_ctrl)); + struct uib_info *uib_ctrl = malloc(sizeof(*uib_ctrl)); + struct bd_info bd = {0}; + bool full_mem_init = false; + phys_size_t hw_size; + int ret = 0; + int i; + u32 reg = readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD0); + enum reset_type reset_t = get_reset_type(reg); + + /* Populating DDR handoff data */ + debug("DDR: Populating DDR handoff\n"); + + ret = populate_ddr_handoff(dev, io96b_ctrl, uib_ctrl); + if (ret) { + printf("DDR: Failed to populate DDR handoff\n"); + + goto err; + } + + debug("%s: Address MPFE 0x%llx\n", memory_type_in_use(dev), plat->mpfe_base_addr); + + /* DDR initialization progress status tracking */ + bool is_ddr_hang_be4_rst = is_ddr_init_hang(); + + printf("%s: SDRAM init in progress ...\n", memory_type_in_use(dev)); + + ddr_init_inprogress(true); + + if (is_ddr_in_use(dev)) { + /* Configure if polling is needed for IO96B GEN PLL locked */ + io96b_ctrl->ckgen_lock = false; + + /* Ensure calibration status passing */ + init_mem_cal(io96b_ctrl); + } + + /* Configuring MPFE sideband manager registers - multichannel or interleaving */ + debug("%s: MPFE configuration in progress ...\n", memory_type_in_use(dev)); + + ret = config_mpfe_sideband_mgr(dev); + if (ret) { + printf("%s: Failed to configure multichannel/interleaving mode\n", + memory_type_in_use(dev)); + + goto err; + } + + debug("%s: MPFE configuration completed\n", memory_type_in_use(dev)); + + debug("%s: Waiting for NOCPLL locked ...\n", memory_type_in_use(dev)); + + /* Ensure NOCPLL locked */ + ret = wait_for_bit_le32((const void *)socfpga_get_sysmgr_addr() + SYSMGR_HMC_CLK + , SYSMGR_HMC_CLK_NOCPLL, true, TIMEOUT, false); + if (ret) { + printf("%s: NOCPLL is not locked\n", memory_type_in_use(dev)); + + goto err; + } + + debug("%s: NOCPLL locked\n", memory_type_in_use(dev)); + + debug("%s: Checking calibration...\n", memory_type_in_use(dev)); + + if (is_ddr_in_use(dev)) { + /* Initiate IOSSM mailbox */ + io96b_mb_init(io96b_ctrl); + + /* Need to trigger re-calibration for DDR DBE */ + if (ddr_ecc_dbe_status()) { + for (i = 0; i < io96b_ctrl->num_instance; i++) + io96b_ctrl->io96b[i].cal_status = false; + + io96b_ctrl->overall_cal_status &= io96b_ctrl->io96b[i].cal_status; + } + + /* Trigger re-calibration if calibration failed */ + if (!(io96b_ctrl->overall_cal_status)) { + printf("DDR: Re-calibration in progress...\n"); + + trig_mem_cal(io96b_ctrl); + } + + printf("DDR: Calibration success\n"); + + /* DDR type */ + ret = get_mem_technology(io96b_ctrl); + if (ret) { + printf("DDR: Failed to get DDR type\n"); + + goto err; + } + + /* DDR size */ + ret = get_mem_width_info(io96b_ctrl); + if (ret) { + printf("DDR: Failed to get DDR size\n"); + + goto err; + } + } else { + /* Ensure calibration status passing */ + uib_init_mem_cal(uib_ctrl); + + /* Need to trigger re-calibration for HBM DBE */ + if (ddr_ecc_dbe_status()) { + for (i = 0; i < uib_ctrl->num_instance; i++) + uib_ctrl->uib[i].cal_status = false; + + uib_ctrl->overall_cal_status = false; + } + + /* Trigger re-calibration if calibration failed */ + if (!(uib_ctrl->overall_cal_status)) { + printf("HBM: Re-calibration in progress...\n"); + + uib_trig_mem_cal(uib_ctrl); + } + + if (!(uib_ctrl->overall_cal_status)) { + printf("HBM: Retry calibration failed & not able to re-calibrate\n"); + + ret = -EINVAL; + goto err; + } + + debug("HBM: Setting Error Mask Register\n"); + + /* Responder Error Mask Register */ + for (i = 0; i < uib_ctrl->num_instance; i++) { + clrsetbits_le32(uib_ctrl->uib[i].uib_csr_addr + + UIB_R_ERRMSK_PSEUDO_CH0_OFFSET, + UIB_DRAM_SBE_MSK | UIB_INTERNAL_CORR_ERR_MSK, + UIB_DRAM_SBE(0x1) | UIB_INTERNAL_CORR_ERR(0x1)); + + debug("HBM: Error Mask Pseudo CH0 addr: 0x%llx\n", + uib_ctrl->uib[i].uib_csr_addr + + UIB_R_ERRMSK_PSEUDO_CH0_OFFSET); + + debug("HBM: Error Mask Pseudo CH0 value: 0x%x\n", + readl(uib_ctrl->uib[i].uib_csr_addr + + UIB_R_ERRMSK_PSEUDO_CH0_OFFSET)); + + clrsetbits_le32(uib_ctrl->uib[i].uib_csr_addr + + UIB_R_ERRMSK_PSEUDO_CH1_OFFSET, + UIB_DRAM_SBE_MSK | UIB_INTERNAL_CORR_ERR_MSK, + UIB_DRAM_SBE(0x1) | UIB_INTERNAL_CORR_ERR(0x1)); + + debug("HBM: Error Mask Pseudo CH1 addr: 0x%llx\n", + uib_ctrl->uib[i].uib_csr_addr + + UIB_R_ERRMSK_PSEUDO_CH1_OFFSET); + + debug("HBM: Error Mask Pseudo CH1 value: 0x%x\n\n", + readl(uib_ctrl->uib[i].uib_csr_addr + + UIB_R_ERRMSK_PSEUDO_CH1_OFFSET)); + } + + printf("HBM: Calibration success\n"); + } + + /* Get bank configuration from devicetree */ + ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL, + (phys_size_t *)&gd->ram_size, &bd); + if (ret) { + printf("%s: Failed to decode memory node\n", memory_type_in_use(dev)); + + goto err; + } + + if (!is_ddr_in_use(dev)) + hw_size = uib_ctrl->overall_size; + else + hw_size = (phys_size_t)io96b_ctrl->overall_size * SZ_1G / SZ_8; + + if (gd->ram_size != hw_size) { + printf("%s: Warning: DRAM size from device tree (%lld MiB)\n", + memory_type_in_use(dev), gd->ram_size >> 20); + printf(" mismatch with hardware (%lld MiB).\n", + hw_size >> 20); + } + + if (gd->ram_size > hw_size) { + printf("%s: Error: DRAM size from device tree is greater\n", + memory_type_in_use(dev)); + printf(" than hardware size.\n"); + + hang(); + } + + printf("%s: %lld MiB\n", (is_ddr_in_use(dev) ? io96b_ctrl->ddr_type : "HBM"), + gd->ram_size >> 20); + + if (is_ddr_in_use(dev)) { + /* ECC status */ + ret = ecc_enable_status(io96b_ctrl); + if (ret) { + printf("DDR: Failed to get DDR ECC status\n"); + + goto err; + } + + /* + * Is HPS cold or warm reset? If yes, Skip full memory initialization if ECC + * enabled to preserve memory content + */ + if (io96b_ctrl->ecc_status) { + full_mem_init = hps_ocram_dbe_status() | ddr_ecc_dbe_status() | + is_ddr_hang_be4_rst; + if (full_mem_init || !(reset_t == WARM_RESET || reset_t == COLD_RESET)) { + debug("%s: Needed to fully initialize DDR memory\n", + io96b_ctrl->ddr_type); + + ret = bist_mem_init_start(io96b_ctrl); + if (ret) { + printf("%s: Failed to fully initialize DDR memory\n", + io96b_ctrl->ddr_type); + + goto err; + } + } + } + } else { + debug("HBM: ECC enable status: %d\n", uib_ctrl->ecc_status); + + /* + * Is HPS cold or warm reset? If yes, Skip full memory initialization if ECC + * enabled to preserve memory content + */ + if (uib_ctrl->ecc_status) { + full_mem_init = hps_ocram_dbe_status() | ddr_ecc_dbe_status() | + is_ddr_hang_be4_rst; + if (full_mem_init || !(reset_t == WARM_RESET || reset_t == COLD_RESET)) { + debug("HBM: Needed to fully initialize HBM memory\n"); + + ret = uib_bist_mem_init_start(uib_ctrl); + if (ret) { + printf("HBM: Failed to fully initialize HBM memory\n"); + + goto err; + } + } + } + } + + /* Ensure sanity memory test passing */ + sdram_size_check(&bd); + + printf("%s: size check success\n", (is_ddr_in_use(dev) ? io96b_ctrl->ddr_type : "HBM")); + + sdram_set_firewall(&bd); + + printf("%s: firewall init success\n", (is_ddr_in_use(dev) ? io96b_ctrl->ddr_type : "HBM")); + + priv->info.base = bd.bi_dram[0].start; + priv->info.size = gd->ram_size; + + /* Ending DDR driver initialization success tracking */ + ddr_init_inprogress(false); + + printf("%s init success\n", (is_ddr_in_use(dev) ? io96b_ctrl->ddr_type : "HBM")); + +err: + free(io96b_ctrl); + free(uib_ctrl); + + return ret; +} diff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c index 4716abfc9a..a0cc9be25e 100644 --- a/drivers/ddr/altera/sdram_soc64.c +++ b/drivers/ddr/altera/sdram_soc64.c @@ -1,7 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2016-2022 Intel Corporation - * + * Copyright (C) 2016-2024 Intel Corporation */ #include @@ -28,6 +27,7 @@ #define PGTABLE_OFF 0x4000 +#if !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) u32 hmc_readl(struct altera_sdram_plat *plat, u32 reg) { return readl(plat->iomhc + reg); @@ -99,6 +99,7 @@ int emif_reset(struct altera_sdram_plat *plat) debug("DDR: %s triggered successly\n", __func__); return 0; } +#endif #if !IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) int poll_hmc_clock_status(void) @@ -322,7 +323,12 @@ static int altera_sdram_of_to_plat(struct udevice *dev) /* These regs info are part of DDR handoff in bitstream */ #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) return 0; -#endif +#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) + addr = dev_read_addr_index(dev, 0); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + plat->mpfe_base_addr = addr; +#else addr = dev_read_addr_index(dev, 0); if (addr == FDT_ADDR_T_NONE) @@ -338,7 +344,7 @@ static int altera_sdram_of_to_plat(struct udevice *dev) if (addr == FDT_ADDR_T_NONE) return -EINVAL; plat->hmc = (void __iomem *)addr; - +#endif return 0; } @@ -385,6 +391,7 @@ static const struct udevice_id altera_sdram_ids[] = { { .compatible = "altr,sdr-ctl-s10" }, { .compatible = "intel,sdr-ctl-agilex" }, { .compatible = "intel,sdr-ctl-n5x" }, + { .compatible = "intel,sdr-ctl-agilex7m" }, { /* sentinel */ } }; diff --git a/drivers/ddr/altera/sdram_soc64.h b/drivers/ddr/altera/sdram_soc64.h index 87a70a861b..02019ac9e5 100644 --- a/drivers/ddr/altera/sdram_soc64.h +++ b/drivers/ddr/altera/sdram_soc64.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2017-2019 Intel Corporation + * Copyright (C) 2017-2024 Intel Corporation */ #ifndef _SDRAM_SOC64_H_ @@ -13,11 +13,24 @@ struct altera_sdram_priv { struct reset_ctl_bulk resets; }; +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) +enum memory_type { + DDR_MEMORY = 0, + HBM_MEMORY +}; + +struct altera_sdram_plat { + fdt_addr_t mpfe_base_addr; + bool multichannel_interleaving; + enum memory_type mem_type; +}; +#else struct altera_sdram_plat { void __iomem *hmc; void __iomem *ddr_sch; void __iomem *iomhc; }; +#endif /* ECC HMC registers */ #define DDRIOCTRL 0x8 From patchwork Fri May 17 05:26:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Meng, Tingting" X-Patchwork-Id: 1936443 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=E/iNMTSt; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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16 May 2024 22:28:13 -0700 From: tingting.meng@intel.com To: u-boot@lists.denx.de Cc: Lukasz Majewski , Sean Anderson , Rayagonda Kokatanur , Tom Rini , Marek , Simon , Tien Fong , Kok Kiang , Dinesh , Boon Khai , Alif , Teik Heng , Hazim , Jit Loon Lim , Sieu Mun Tang , Sin Hui Kho , Tingting Meng Subject: [Agilex7 M-series Platform Enablement v1 11/16] ddr: altera: soc64: Restructure SDRAM firewall function Date: Fri, 17 May 2024 13:26:56 +0800 Message-Id: <20240517052701.12949-12-tingting.meng@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240517052701.12949-1-tingting.meng@intel.com> References: <20240517052701.12949-1-tingting.meng@intel.com> MIME-Version: 1.0 X-Mailman-Approved-At: Fri, 17 May 2024 14:50:41 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Sin Hui Kho Restructure SDRAM firewall function. Move the non-F2SDRAM firewall configuration to an individual function, in preparation to support F2SDRAM firewall configuration. Signed-off-by: Sin Hui Kho Signed-off-by: Tingting Meng --- drivers/ddr/altera/sdram_soc64.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c index a0cc9be25e..8f2085f3a0 100644 --- a/drivers/ddr/altera/sdram_soc64.c +++ b/drivers/ddr/altera/sdram_soc64.c @@ -253,7 +253,7 @@ phys_size_t sdram_calculate_size(struct altera_sdram_plat *plat) return size; } -void sdram_set_firewall(struct bd_info *bd) +static void sdram_set_firewall_non_f2sdram(struct bd_info *bd) { u32 i; phys_size_t value; @@ -289,7 +289,7 @@ void sdram_set_firewall(struct bd_info *bd) FW_MPU_DDR_SCR_NONMPUREGION0ADDR_BASEEXT + (i * 4 * sizeof(u32))); - /* Setting non-secure MPU limit and limit extexded */ + /* Setting non-secure MPU limit and limit extended */ value = bd->bi_dram[i].start + bd->bi_dram[i].size - 1; lower = lower_32_bits(value); @@ -302,7 +302,7 @@ void sdram_set_firewall(struct bd_info *bd) FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT + (i * 4 * sizeof(u32))); - /* Setting non-secure Non-MPU limit and limit extexded */ + /* Setting non-secure Non-MPU limit and limit extended */ FW_MPU_DDR_SCR_WRITEL(lower, FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT + (i * 4 * sizeof(u32))); @@ -315,6 +315,11 @@ void sdram_set_firewall(struct bd_info *bd) } } +void sdram_set_firewall(struct bd_info *bd) +{ + sdram_set_firewall_non_f2sdram(bd); +} + static int altera_sdram_of_to_plat(struct udevice *dev) { struct altera_sdram_plat *plat = dev_get_plat(dev); From patchwork Fri May 17 05:26:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Meng, Tingting" X-Patchwork-Id: 1936444 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=fJiaYNIg; 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16 May 2024 22:28:17 -0700 From: tingting.meng@intel.com To: u-boot@lists.denx.de Cc: Lukasz Majewski , Sean Anderson , Rayagonda Kokatanur , Tom Rini , Marek , Simon , Tien Fong , Kok Kiang , Dinesh , Boon Khai , Alif , Teik Heng , Hazim , Jit Loon Lim , Sieu Mun Tang , Tingting Meng Subject: [Agilex7 M-series Platform Enablement v1 12/16] ddr: altera: soc64: Clean up bit-shift by zero bit Date: Fri, 17 May 2024 13:26:57 +0800 Message-Id: <20240517052701.12949-13-tingting.meng@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240517052701.12949-1-tingting.meng@intel.com> References: <20240517052701.12949-1-tingting.meng@intel.com> MIME-Version: 1.0 X-Mailman-Approved-At: Fri, 17 May 2024 14:50:41 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Teik Heng Chong Clean up bit-shift by zero bit Signed-off-by: Teik Heng Chong Signed-off-by: Tingting Meng --- drivers/ddr/altera/sdram_soc64.h | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/ddr/altera/sdram_soc64.h b/drivers/ddr/altera/sdram_soc64.h index 02019ac9e5..add7df01a5 100644 --- a/drivers/ddr/altera/sdram_soc64.h +++ b/drivers/ddr/altera/sdram_soc64.h @@ -92,7 +92,7 @@ struct altera_sdram_plat { #define NIOSRESERVED2 0x118 #define DRAMADDRW_CFG_COL_ADDR_WIDTH(x) \ - (((x) >> 0) & 0x1F) + ((x) & 0x1F) #define DRAMADDRW_CFG_ROW_ADDR_WIDTH(x) \ (((x) >> 5) & 0x1F) #define DRAMADDRW_CFG_BANK_ADDR_WIDTH(x) \ @@ -103,7 +103,7 @@ struct altera_sdram_plat { (((x) >> 16) & 0x7) #define CTRLCFG0_CFG_MEMTYPE(x) \ - (((x) >> 0) & 0xF) + ((x) & 0xF) #define CTRLCFG0_CFG_DIMM_TYPE(x) \ (((x) >> 4) & 0x7) #define CTRLCFG0_CFG_AC_POS(x) \ @@ -112,17 +112,17 @@ struct altera_sdram_plat { (((x) >> 9) & 0x1F) #define CTRLCFG1_CFG_DBC3_BURST_LEN(x) \ - (((x) >> 0) & 0x1F) + ((x) & 0x1F) #define CTRLCFG1_CFG_ADDR_ORDER(x) \ (((x) >> 5) & 0x3) #define CTRLCFG1_CFG_CTRL_EN_ECC(x) \ (((x) >> 7) & 0x1) #define DRAMTIMING0_CFG_TCL(x) \ - (((x) >> 0) & 0x7F) + ((x) & 0x7F) #define CALTIMING0_CFG_ACT_TO_RDWR(x) \ - (((x) >> 0) & 0x3F) + ((x) & 0x3F) #define CALTIMING0_CFG_ACT_TO_PCH(x) \ (((x) >> 6) & 0x3F) #define CALTIMING0_CFG_ACT_TO_ACT(x) \ @@ -131,7 +131,7 @@ struct altera_sdram_plat { (((x) >> 18) & 0x3F) #define CALTIMING1_CFG_RD_TO_RD(x) \ - (((x) >> 0) & 0x3F) + ((x) & 0x3F) #define CALTIMING1_CFG_RD_TO_RD_DC(x) \ (((x) >> 6) & 0x3F) #define CALTIMING1_CFG_RD_TO_RD_DB(x) \ @@ -142,7 +142,7 @@ struct altera_sdram_plat { (((x) >> 24) & 0x3F) #define CALTIMING2_CFG_RD_TO_WR_DB(x) \ - (((x) >> 0) & 0x3F) + ((x) & 0x3F) #define CALTIMING2_CFG_RD_TO_WR_PCH(x) \ (((x) >> 6) & 0x3F) #define CALTIMING2_CFG_RD_AP_TO_VALID(x) \ @@ -153,7 +153,7 @@ struct altera_sdram_plat { (((x) >> 24) & 0x3F) #define CALTIMING3_CFG_WR_TO_WR_DB(x) \ - (((x) >> 0) & 0x3F) + ((x) & 0x3F) #define CALTIMING3_CFG_WR_TO_RD(x) \ (((x) >> 6) & 0x3F) #define CALTIMING3_CFG_WR_TO_RD_DC(x) \ @@ -164,7 +164,7 @@ struct altera_sdram_plat { (((x) >> 24) & 0x3F) #define CALTIMING4_CFG_WR_AP_TO_VALID(x) \ - (((x) >> 0) & 0x3F) + ((x) & 0x3F) #define CALTIMING4_CFG_PCH_TO_VALID(x) \ (((x) >> 6) & 0x3F) #define CALTIMING4_CFG_PCH_ALL_TO_VALID(x) \ @@ -175,7 +175,7 @@ struct altera_sdram_plat { (((x) >> 26) & 0x3F) #define CALTIMING9_CFG_4_ACT_TO_ACT(x) \ - (((x) >> 0) & 0xFF) + ((x) & 0xFF) /* Firewall DDR scheduler MPFE */ #define FW_HMC_ADAPTOR_REG_ADDR 0xf8020004 From patchwork Fri May 17 05:26:58 2024 Content-Type: text/plain; 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d="scan'208";a="11930036" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 May 2024 22:28:26 -0700 X-CSE-ConnectionGUID: T04dqJnrQ5u28rnFp9tGTg== X-CSE-MsgGUID: RnAl30SpQoW4AkFW/wjObA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,166,1712646000"; d="scan'208";a="36188368" Received: from pglc00543.png.intel.com ([10.221.239.235]) by fmviesa003.fm.intel.com with ESMTP; 16 May 2024 22:28:22 -0700 From: tingting.meng@intel.com To: u-boot@lists.denx.de Cc: Lukasz Majewski , Sean Anderson , Rayagonda Kokatanur , Tom Rini , Marek , Simon , Tien Fong , Kok Kiang , Dinesh , Boon Khai , Alif , Teik Heng , Hazim , Jit Loon Lim , Sieu Mun Tang , Tingting Meng Subject: [Agilex7 M-series Platform Enablement v1 13/16] ddr: altera: soc64: Fix dram size calculation in clamshell mode Date: Fri, 17 May 2024 13:26:58 +0800 Message-Id: <20240517052701.12949-14-tingting.meng@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240517052701.12949-1-tingting.meng@intel.com> References: <20240517052701.12949-1-tingting.meng@intel.com> MIME-Version: 1.0 X-Mailman-Approved-At: Fri, 17 May 2024 14:50:41 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Teik Heng Chong This patch is to fix wrong memory size calculation in clamshell mode Signed-off-by: Teik Heng Chong Signed-off-by: Tingting Meng --- drivers/ddr/altera/sdram_soc64.c | 16 +++++++++++++++- drivers/ddr/altera/sdram_soc64.h | 5 +++++ 2 files changed, 20 insertions(+), 1 deletion(-) diff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c index 8f2085f3a0..27580cce2f 100644 --- a/drivers/ddr/altera/sdram_soc64.c +++ b/drivers/ddr/altera/sdram_soc64.c @@ -27,6 +27,9 @@ #define PGTABLE_OFF 0x4000 +#define SINGLE_RANK_CLAMSHELL 0xC3C3 +#define DUAL_RANK_CLAMSHELL 0xA5A5 + #if !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) u32 hmc_readl(struct altera_sdram_plat *plat, u32 reg) { @@ -240,8 +243,19 @@ phys_size_t sdram_calculate_size(struct altera_sdram_plat *plat) { u32 dramaddrw = hmc_readl(plat, DRAMADDRW); + u32 reg_ctrlcfg6_value = hmc_readl(plat, CTRLCFG6); + u32 cs_rank = CTRLCFG6_CFG_CS_CHIP(reg_ctrlcfg6_value); + u32 cs_addr_width; + + if (cs_rank == SINGLE_RANK_CLAMSHELL) + cs_addr_width = 0; + else if (cs_rank == DUAL_RANK_CLAMSHELL) + cs_addr_width = 1; + else + cs_addr_width = DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw); + phys_size_t size = (phys_size_t)1 << - (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) + + (cs_addr_width + DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) + DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) + DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) + diff --git a/drivers/ddr/altera/sdram_soc64.h b/drivers/ddr/altera/sdram_soc64.h index add7df01a5..8b3b53cf5d 100644 --- a/drivers/ddr/altera/sdram_soc64.h +++ b/drivers/ddr/altera/sdram_soc64.h @@ -78,6 +78,8 @@ struct altera_sdram_plat { #define CTRLCFG0 0x28 #define CTRLCFG1 0x2c #define CTRLCFG3 0x34 +#define CTRLCFG5 0x3c +#define CTRLCFG6 0x40 #define DRAMTIMING0 0x50 #define CALTIMING0 0x7c #define CALTIMING1 0x80 @@ -118,6 +120,9 @@ struct altera_sdram_plat { #define CTRLCFG1_CFG_CTRL_EN_ECC(x) \ (((x) >> 7) & 0x1) +#define CTRLCFG6_CFG_CS_CHIP(x) \ + ((x) & 0xFFFF) + #define DRAMTIMING0_CFG_TCL(x) \ ((x) & 0x7F) From patchwork Fri May 17 05:26:59 2024 Content-Type: text/plain; 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d="scan'208";a="11930056" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 May 2024 22:28:30 -0700 X-CSE-ConnectionGUID: Vu/g5S0KSfqpTXWFOsejRw== X-CSE-MsgGUID: XmcuVA04QgeAM8OV5JAZ4Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,166,1712646000"; d="scan'208";a="36188418" Received: from pglc00543.png.intel.com ([10.221.239.235]) by fmviesa003.fm.intel.com with ESMTP; 16 May 2024 22:28:26 -0700 From: tingting.meng@intel.com To: u-boot@lists.denx.de Cc: Lukasz Majewski , Sean Anderson , Rayagonda Kokatanur , Tom Rini , Marek , Simon , Tien Fong , Kok Kiang , Dinesh , Boon Khai , Alif , Teik Heng , Hazim , Jit Loon Lim , Sieu Mun Tang , Wan Yee Lau , Tingting Meng Subject: [Agilex7 M-series Platform Enablement v1 14/16] arch: arm: mach-socfpga: Update kconfig for new platform Agilex7 M-series Date: Fri, 17 May 2024 13:26:59 +0800 Message-Id: <20240517052701.12949-15-tingting.meng@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240517052701.12949-1-tingting.meng@intel.com> References: <20240517052701.12949-1-tingting.meng@intel.com> MIME-Version: 1.0 X-Mailman-Approved-At: Fri, 17 May 2024 14:50:41 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Wan Yee Lau Update Kconfig for new platform Agilex7 M-series. Signed-off-by: Wan Yee Lau Signed-off-by: Teik Heng Chong Signed-off-by: Tingting Meng --- arch/arm/Kconfig | 4 +++- arch/arm/mach-socfpga/Kconfig | 19 +++++++++++++++++++ 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 56e190adf6..f68b680d82 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -32,7 +32,9 @@ config COUNTER_FREQUENCY ROCKCHIP_RK3288 || ROCKCHIP_RK322X || ROCKCHIP_RK3036 default 25000000 if ARCH_LX2160A || ARCH_LX2162A || ARCH_LS1088A default 100000000 if ARCH_ZYNQMP - default 200000000 if ARCH_SOCFPGA && ARM64 && TARGET_SOCFPGA_AGILEX5 + default 400000000 if ARCH_SOCFPGA && ARM64 && !TARGET_SOCFPGA_AGILEX7M + default 200000000 if ARCH_SOCFPGA && ARM64 && TARGET_SOCFPGA_AGILEX5 && \ + TARGET_SOCFPGA_AGILEX7M default 0 help For platforms with ARMv8-A and ARMv7-A which features a system diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 1008232cac..2ca6336f21 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -59,6 +59,18 @@ config TARGET_SOCFPGA_AGILEX select SPL_CLK if SPL select TARGET_SOCFPGA_SOC64 +config TARGET_SOCFPGA_AGILEX7M + bool + select ARMV8_MULTIENTRY + select ARMV8_SET_SMPEN + select BINMAN if SPL_ATF + select CLK + select FPGA_INTEL_SDM_MAILBOX + select GICV2 + select NCORE_CACHE + select SPL_CLK if SPL + select TARGET_SOCFPGA_SOC64 + config TARGET_SOCFPGA_AGILEX5 bool select BINMAN if SPL_ATF @@ -139,6 +151,10 @@ config TARGET_SOCFPGA_AGILEX_SOCDK bool "Intel SOCFPGA SoCDK (Agilex)" select TARGET_SOCFPGA_AGILEX +config TARGET_SOCFPGA_AGILEX7M_SOCDK + bool "Intel SOCFPGA SoCDK (Agilex7 M-series)" + select TARGET_SOCFPGA_AGILEX7M + config TARGET_SOCFPGA_AGILEX5_SOCDK bool "Intel SOCFPGA SoCDK (Agilex5)" select TARGET_SOCFPGA_AGILEX5 @@ -216,6 +232,7 @@ config TARGET_SOCFPGA_TERASIC_SOCKIT endchoice config SYS_BOARD + default "agilex7m-socdk" if TARGET_SOCFPGA_AGILEX7M_SOCDK default "agilex5-socdk" if TARGET_SOCFPGA_AGILEX5_SOCDK default "agilex-socdk" if TARGET_SOCFPGA_AGILEX_SOCDK default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK @@ -238,6 +255,7 @@ config SYS_BOARD default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA config SYS_VENDOR + default "intel" if TARGET_SOCFPGA_AGILEX7M_SOCDK default "intel" if TARGET_SOCFPGA_AGILEX5_SOCDK default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK default "intel" if TARGET_SOCFPGA_N5X_SOCDK @@ -261,6 +279,7 @@ config SYS_SOC default "socfpga" config SYS_CONFIG_NAME + default "socfpga_agilex7m_socdk" if TARGET_SOCFPGA_AGILEX7M_SOCDK default "socfpga_agilex5_socdk" if TARGET_SOCFPGA_AGILEX5_SOCDK default "socfpga_agilex_socdk" if TARGET_SOCFPGA_AGILEX_SOCDK default "socfpga_arria5_secu1" if TARGET_SOCFPGA_ARRIA5_SECU1 From patchwork Fri May 17 05:27:00 2024 Content-Type: text/plain; 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Signed-off-by: Wan Yee Lau Signed-off-by: Teik Heng Chong Signed-off-by: Tingting Meng --- arch/arm/dts/Makefile | 1 + arch/arm/mach-socfpga/Makefile | 18 ++++++++++++++++++ board/intel/agilex7m-socdk/Makefile | 7 +++++++ 3 files changed, 26 insertions(+) create mode 100644 board/intel/agilex7m-socdk/Makefile diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 7b7788f755..c056e0e78e 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -547,6 +547,7 @@ dtb-$(CONFIG_TARGET_THUNDERX_88XX) += thunderx-88xx.dtb dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_agilex_socdk.dtb \ socfpga_agilex5_socdk.dtb \ + socfpga_agilex7m_socdk.dtb \ socfpga_arria5_secu1.dtb \ socfpga_arria5_socdk.dtb \ socfpga_arria10_chameleonv3_270_2.dtb \ diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 67c6a8dfec..856fd597f6 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -65,6 +65,21 @@ obj-y += reset_manager_s10.o obj-y += wrap_pll_config_soc64.o endif +ifdef CONFIG_TARGET_SOCFPGA_AGILEX7M +obj-y += clock_manager_agilex.o +obj-y += lowlevel_init_soc64.o +obj-y += mailbox_s10.o +obj-y += misc_soc64.o +obj-y += mmu-arm64_s10.o +obj-y += reset_manager_s10.o +obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += secure_vab.o +obj-y += system_manager_soc64.o +obj-y += timer_s10.o +obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += vab.o +obj-y += wrap_handoff_soc64.o +obj-y += wrap_pll_config_soc64.o +endif + ifdef CONFIG_TARGET_SOCFPGA_N5X obj-y += clock_manager_n5x.o obj-y += lowlevel_init_soc64.o @@ -107,6 +122,9 @@ endif ifdef CONFIG_TARGET_SOCFPGA_AGILEX5 obj-y += spl_soc64.o endif +ifdef CONFIG_TARGET_SOCFPGA_AGILEX7M +obj-y += spl_agilex7m.o +endif else obj-$(CONFIG_SPL_ATF) += secure_reg_helper.o obj-$(CONFIG_SPL_ATF) += smc_api.o diff --git a/board/intel/agilex7m-socdk/Makefile b/board/intel/agilex7m-socdk/Makefile new file mode 100644 index 0000000000..ff5d9dde3b --- /dev/null +++ b/board/intel/agilex7m-socdk/Makefile @@ -0,0 +1,7 @@ + +# Copyright (C) 2024 Intel Corporation +# +# SPDX-License-Identifier: GPL-2.0 +# + +obj-y := socfpga.o From patchwork Fri May 17 05:27:01 2024 Content-Type: text/plain; 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d="scan'208";a="11930074" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 May 2024 22:28:39 -0700 X-CSE-ConnectionGUID: 204sq+iBRsyLcus6RM2pdw== X-CSE-MsgGUID: k3akPkfvSM2YGQXYDuoSew== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,166,1712646000"; d="scan'208";a="36188505" Received: from pglc00543.png.intel.com ([10.221.239.235]) by fmviesa003.fm.intel.com with ESMTP; 16 May 2024 22:28:35 -0700 From: tingting.meng@intel.com To: u-boot@lists.denx.de Cc: Lukasz Majewski , Sean Anderson , Rayagonda Kokatanur , Tom Rini , Marek , Simon , Tien Fong , Kok Kiang , Dinesh , Boon Khai , Alif , Teik Heng , Hazim , Jit Loon Lim , Sieu Mun Tang , Wan Yee Lau , Tingting Meng Subject: [Agilex7 M-series Platform Enablement v1 16/16] configs: Add defconfig for Agilex7 M-series Date: Fri, 17 May 2024 13:27:01 +0800 Message-Id: <20240517052701.12949-17-tingting.meng@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240517052701.12949-1-tingting.meng@intel.com> References: <20240517052701.12949-1-tingting.meng@intel.com> MIME-Version: 1.0 X-Mailman-Approved-At: Fri, 17 May 2024 14:50:41 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Wan Yee Lau Add defconfig for Agilex7 M-series. Signed-off-by: Wan Yee Lau Signed-off-by: Teik Heng Chong Signed-off-by: Tingting Meng --- ...onfig => socfpga_agilex7m_sdmmc_defconfig} | 110 +++++++++--------- 1 file changed, 54 insertions(+), 56 deletions(-) copy configs/{socfpga_agilex5_defconfig => socfpga_agilex7m_sdmmc_defconfig} (56%) diff --git a/configs/socfpga_agilex5_defconfig b/configs/socfpga_agilex7m_sdmmc_defconfig similarity index 56% copy from configs/socfpga_agilex5_defconfig copy to configs/socfpga_agilex7m_sdmmc_defconfig index f39954aea8..12414e2e5f 100644 --- a/configs/socfpga_agilex5_defconfig +++ b/configs/socfpga_agilex7m_sdmmc_defconfig @@ -1,50 +1,69 @@ CONFIG_ARM=y +CONFIG_COUNTER_FREQUENCY=400000000 CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds" -CONFIG_SYS_SPI_U_BOOT_OFFS=0x04000000 CONFIG_ARCH_SOCFPGA=y -CONFIG_TEXT_BASE=0x80200000 +CONFIG_TEXT_BASE=0x200000 CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_NR_DRAM_BANKS=2 +CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x04100000 +CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_SPI_U_BOOT_OFFS=0x04000000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex5_socdk" -CONFIG_TARGET_SOCFPGA_AGILEX5_SOCDK=y -CONFIG_IDENT_STRING="socfpga_agilex5" +CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex7m_socdk" +CONFIG_SPL_TEXT_BASE=0xFFE00000 +CONFIG_TARGET_SOCFPGA_AGILEX7M_SOCDK=y +CONFIG_IDENT_STRING="socfpga_agilex7m" CONFIG_SPL_FS_FAT=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_SPL_FIT_SIGNATURE=y CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_LOAD_FIT_ADDRESS=0x82000000 +CONFIG_SPL_LOAD_FIT_ADDRESS=0x02000000 +CONFIG_SYS_LOAD_ADDR=0x02000000 # CONFIG_USE_SPL_FIT_GENERATOR is not set -CONFIG_QSPI_BOOT=y +# CONFIG_NAND_BOOT is not set +# CONFIG_QSPI_BOOT is not set CONFIG_BOOTDELAY=5 CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,115200 initrd=0x90000000 root=/dev/ram0 rw init=/sbin/init ramdisk_size=10000000 earlycon panic=-1 nosmp kvm-arm.mode=nvhe" -CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_BOOTARGS="earlycon panic=-1" # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x3ff00000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xffe3f000 +CONFIG_SPL_SYS_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SPL_SYS_MALLOC_ADDR=0x3fa00000 +CONFIG_SPL_SYS_MALLOC_SIZE=0x500000 +CONFIG_SPL_BSS_MAX_SIZE=0x100000 CONFIG_SPL_CRC32=y +CONFIG_SPL_MTD_SUPPORT=y +# CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_CACHE=y +CONFIG_SPL_SPI_LOAD=y CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y -CONFIG_SYS_PROMPT="SOCFPGA_AGILEX5 # " +CONFIG_SYS_PROMPT="SOCFPGA_AGILEX7M # " CONFIG_CMD_NVEDIT_SELECT=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y -CONFIG_CMD_SF=y -CONFIG_DOS_PARTITION=y -CONFIG_SPL_DOS_PARTITION=y -CONFIG_SPL_SYS_DISABLE_DCACHE_OPS=y +CONFIG_CMD_MMC=y CONFIG_CMD_MTD=y -# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +# CONFIG_CMD_NAND_TRIMFFS is not set +# CONFIG_CMD_NAND_LOCK_UNLOCK is not set CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_CACHE=y CONFIG_SPL_SPI_FLASH_MTD=y CONFIG_SPI_FLASH_MTD=y -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_MTDIDS_DEFAULT="nand0=ffb90000.nand.0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=ffb90000.nand.0:2m(u-boot),-(root)" +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_CMD_UBI=y CONFIG_CMD_UBIFS=y CONFIG_MTD_UBI=y @@ -53,9 +72,8 @@ CONFIG_MTD_UBI_BEB_LIMIT=20 # CONFIG_ISO_PARTITION is not set # CONFIG_EFI_PARTITION is not set CONFIG_OF_LIST="" -CONFIG_ENV_IS_IN_UBI=y -CONFIG_ENV_UBI_PART="root" -CONFIG_ENV_UBI_VOLUME="env" +CONFIG_ENV_IS_IN_FAT=y +CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y @@ -65,52 +83,32 @@ CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y CONFIG_MISC=y +CONFIG_MMC_DW=y +CONFIG_SYS_MMC_MAX_BLK_COUNT=256 CONFIG_MTD=y CONFIG_DM_MTD=y +# CONFIG_NAND_DENALI_DT is not set +# CONFIG_SYS_NAND_U_BOOT_LOCATIONS is not set +CONFIG_SYS_NAND_U_BOOT_OFFS=0x0 +CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND=0x100000 +CONFIG_SPL_NAND_FRAMEWORK=y CONFIG_SF_DEFAULT_MODE=0x2003 CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y -CONFIG_UBI_SILENCE_MSG=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y -CONFIG_RGMII=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_MII=y CONFIG_DM_RESET=y CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y -CONFIG_CADENCE_QSPI=y -CONFIG_DESIGNWARE_SPI=y +# CONFIG_CADENCE_QSPI is not set +# CONFIG_DESIGNWARE_SPI is not set CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_DWC2=y -CONFIG_USB_XHCI_HCD=y -CONFIG_UBIFS_SILENCE_MSG=y +CONFIG_DESIGNWARE_WATCHDOG=y +CONFIG_WDT=y # CONFIG_SPL_USE_TINY_PRINTF is not set CONFIG_PANIC_HANG=y -CONFIG_SPL_SPI_LOAD=y -CONFIG_SYS_LOAD_ADDR=0x82000000 -CONFIG_WDT=y -CONFIG_CMD_WDT=y -CONFIG_DESIGNWARE_WATCHDOG=y -CONFIG_SPL_WDT=y -CONFIG_WATCHDOG_AUTOSTART=n -CONFIG_TIMER=y -CONFIG_DESIGNWARE_APB_TIMER=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80300000 -CONFIG_SPL_MAX_SIZE=0x40000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0xbff00000 -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK=0x7f000 -CONFIG_SYS_SPL_MALLOC=y -CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y -CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0xbfa00000 -CONFIG_SYS_SPL_MALLOC_SIZE=0x500000 -CONFIG_SPL_BSS_MAX_SIZE=0x100000 -# CONFIG_EFI_LOADER is not set -CONFIG_I3C=y -CONFIG_DW_I3C_MASTER=y -CONFIG_CMD_I3C=y -CONFIG_SYS_MAXARGS=32 -CONFIG_CMD_TIMER=y -# CONFIG_BOOTFILE="Image" is not set for CONFIG_SPL_ATF=y -CONFIG_USE_BOOTFILE=y -CONFIG_BOOTFILE="kernel.itb"