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Mon, 13 May 2024 11:49:37 -0700 (PDT) Received: from vineet-framework.hq.rivosinc.com ([50.145.13.30]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-6f4d2a66585sm7944336b3a.10.2024.05.13.11.49.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 11:49:37 -0700 (PDT) From: Vineet Gupta To: gcc-patches@gcc.gnu.org Cc: Jeff Law , kito.cheng@gmail.com, Palmer Dabbelt , =?utf-8?q?Christoph_M=C3=BCllner?= , Robin Dapp , gnu-toolchain@rivosinc.com, Vineet Gupta Subject: [PATCH v2 1/2] RISC-V: avoid LUI based const materialization ... [part of PR/106265] Date: Mon, 13 May 2024 11:49:31 -0700 Message-Id: <20240513184932.662109-2-vineetg@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513184932.662109-1-vineetg@rivosinc.com> References: <20240513184932.662109-1-vineetg@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-9.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_SHORT, LIKELY_SPAM_BODY, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Apologies for the delay in getting this out. Needed to fix one ICE with glibc build and fresh round of testing: both testsuite and SPEC runs (which are similar to v1 in terms of Cactu gains, but some more minor regressions elsewhere gcc). Again those seem so small that IMHO this should still go in. I'll investigate those next as well as an existing weirdnes in glibc tempnam which I spotted during the debugging. Changes since v1 [1] - Tighten the main conditition to avoid stack regs as destination (to avoid making them potentially unaligned with -2047 addend: this might be OK execution/ABI wise, but undesirable/ugly still specially when coming from compiler codegen). - Ensure that first alternative is always split - Remove "&& 1" from split condition. That was tripping up glibc build with illegal operands `add s0, s0, 2048`. [1] https://gcc.gnu.org/pipermail/gcc-patches/2024-March/647877.html --- ... if the constant can be represented as sum of two S12 values. The two S12 values could instead be fused with subsequent ADD insn. The helps - avoid an additional LUI insn - side benefits of not clobbering a reg e.g. w/o patch w/ patch long | | plus(unsigned long i) | li a5,4096 | { | addi a5,a5,-2032 | addi a0, a0, 2047 return i + 2064; | add a0,a0,a5 | addi a0, a0, 17 } | ret | ret NOTE: In theory not having const in a standalone reg might seem less CSE friendly, but for workloads in consideration these mat are from very late LRA reloads and follow on GCSE is not doing much currently. The real benefit however is seen in base+offset computation for array accesses and especially for stack accesses which are finalized late in optim pipeline, during LRA register allocation. Often the finalized offsets trigger LRA reloads resulting in mind boggling repetition of exact same insn sequence including LUI based constant materialization. This shaves off 290 billion dynamic instrustions (QEMU icounts) in SPEC 2017 Cactu benchmark which is over 10% of workload. In the rest of suite, there additional 10 billion shaved, with both gains and losses in indiv workloads as is usual with compiler changes. 500.perlbench_r-0 | 1,214,534,029,025 | 1,212,887,959,387 | 500.perlbench_r-1 | 740,383,419,739 | 739,280,308,163 | 500.perlbench_r-2 | 692,074,638,817 | 691,118,734,547 | 502.gcc_r-0 | 190,820,141,435 | 190,857,065,988 | 502.gcc_r-1 | 225,747,660,839 | 225,809,444,357 | <- -0.02% 502.gcc_r-2 | 220,370,089,641 | 220,406,367,876 | <- -0.03% 502.gcc_r-3 | 179,111,460,458 | 179,135,609,723 | <- -0.02% 502.gcc_r-4 | 219,301,546,340 | 219,320,416,956 | <- -0.01% 503.bwaves_r-0 | 278,733,324,691 | 278,733,323,575 | <- -0.01% 503.bwaves_r-1 | 442,397,521,282 | 442,397,519,616 | 503.bwaves_r-2 | 344,112,218,206 | 344,112,216,760 | 503.bwaves_r-3 | 417,561,469,153 | 417,561,467,597 | 505.mcf_r | 669,319,257,525 | 669,318,763,084 | 507.cactuBSSN_r | 2,852,767,394,456 | 2,564,736,063,742 | <+ 10.10% 508.namd_r | 1,855,884,342,110 | 1,855,881,110,934 | 510.parest_r | 1,654,525,521,053 | 1,654,402,859,174 | 511.povray_r | 2,990,146,655,619 | 2,990,060,324,589 | 519.lbm_r | 1,158,337,294,525 | 1,158,337,294,529 | 520.omnetpp_r | 1,021,765,791,283 | 1,026,165,661,394 | 521.wrf_r | 1,715,955,652,503 | 1,714,352,737,385 | 523.xalancbmk_r | 849,846,008,075 | 849,836,851,752 | 525.x264_r-0 | 277,801,762,763 | 277,488,776,427 | 525.x264_r-1 | 927,281,789,540 | 926,751,516,742 | 525.x264_r-2 | 915,352,631,375 | 914,667,785,953 | 526.blender_r | 1,652,839,180,887 | 1,653,260,825,512 | 527.cam4_r | 1,487,053,494,925 | 1,484,526,670,770 | 531.deepsjeng_r | 1,641,969,526,837 | 1,642,126,598,866 | 538.imagick_r | 2,098,016,546,691 | 2,097,997,929,125 | 541.leela_r | 1,983,557,323,877 | 1,983,531,314,526 | 544.nab_r | 1,516,061,611,233 | 1,516,061,407,715 | 548.exchange2_r | 2,072,594,330,215 | 2,072,591,648,318 | 549.fotonik3d_r | 1,001,499,307,366 | 1,001,478,944,189 | 554.roms_r | 1,028,799,739,111 | 1,028,780,904,061 | 557.xz_r-0 | 363,827,039,684 | 363,057,014,260 | 557.xz_r-1 | 906,649,112,601 | 905,928,888,732 | 557.xz_r-2 | 509,023,898,187 | 508,140,356,932 | 997.specrand_fr | 402,535,577 | 403,052,561 | 999.specrand_ir | 402,535,577 | 403,052,561 | This should still be considered damage control as the real/deeper fix would be to reduce number of LRA reloads or CSE/anchor those during LRA constraint sub-pass (re)runs (thats a different PR/114729. Implementation Details (for posterity) -------------------------------------- - basic idea is to have a splitter selected via a new predicate for constant being possible sum of two S12 and provide the transform. This is however a 2 -> 2 transform which combine can't handle. So we specify it using a define_insn_and_split. - the initial loose "i" constraint caused LRA to accept invalid insns thus needing a tighter new constraint as well. - An additional fallback alternate with catch-all "r" register constraint also needed to allow any "reloads" that LRA might require for ADDI with const larger than S12. Testing -------- This is testsuite clean (rv64 only). I'll rely on post-commit CI multlib run for any possible fallout for other setups such as rv32. | | gcc | g++ | gfortran | | rv64imafdc_zba_zbb_zbs_zicond/ lp64d/ medlow | 41 / 17 | 8 / 3 | 7 / 2 | | rv64imafdc_zba_zbb_zbs_zicond/ lp64d/ medlow | 41 / 17 | 8 / 3 | 7 / 2 | I also threw this into a buildroot run, it obviously boots Linux to userspace. bloat-o-meter on glibc and kernel show overall decrease in staic instruction counts with some minor spot increases. These are generally in the category of - LUI + ADDI are 2 byte each vs. two ADD being 4 byte each. - Knock on effects due to inlining changes. - Sometimes the slightly shorter 2-insn seq in a mult-exit function can cause in-place epilogue duplication (vs. a jump back). This is slightly larger but more efficient in execution. In summary nothing to fret about. | linux/scripts/bloat-o-meter build-gcc-240131/target/lib/libc.so.6 \ build-gcc-240131-new-splitter-1-variant/target/lib/libc.so.6 | | add/remove: 0/0 grow/shrink: 21/49 up/down: 520/-3056 (-2536) | Function old new delta | getnameinfo 2756 2892 +136 ... | tempnam 136 144 +8 | padzero 276 284 +8 ... | __GI___register_printf_specifier 284 280 -4 | __EI_xdr_array 468 464 -4 | try_file_lock 268 260 -8 | pthread_create@GLIBC_2 3520 3508 -12 | __pthread_create_2_1 3520 3508 -12 ... | _nss_files_setnetgrent 932 904 -28 | _nss_dns_gethostbyaddr2_r 1524 1480 -44 | build_trtable 3312 3208 -104 | printf_positional 25000 22580 -2420 | Total: Before=2107999, After=2105463, chg -0.12% gcc/ChangeLog: * config/riscv/riscv.h: New macros to check for sum of two S12 range. * config/riscv/constraints.md: New constraint. * config/riscv/predicates.md: New Predicate. * config/riscv/riscv.md: New splitter. * config/riscv/riscv.cc (riscv_reg_frame_related): New helper. * config/riscv/riscv-protos.h: New helper prototype. gcc/testsuite/ChangeLog: * gcc.target/riscv/sum-of-two-s12-const-1.c: New test: checks for new patterns output. * gcc.target/riscv/sum-of-two-s12-const-2.c: Ditto. * gcc.target/riscv/sum-of-two-s12-const-3.c: New test: should not ICE. Signed-off-by: Vineet Gupta --- gcc/config/riscv/constraints.md | 6 +++ gcc/config/riscv/predicates.md | 6 +++ gcc/config/riscv/riscv-protos.h | 1 + gcc/config/riscv/riscv.cc | 11 +++++ gcc/config/riscv/riscv.h | 15 +++++++ gcc/config/riscv/riscv.md | 40 +++++++++++++++++ .../gcc.target/riscv/sum-of-two-s12-const-1.c | 45 +++++++++++++++++++ .../gcc.target/riscv/sum-of-two-s12-const-2.c | 15 +++++++ .../gcc.target/riscv/sum-of-two-s12-const-3.c | 22 +++++++++ 9 files changed, 161 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/sum-of-two-s12-const-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/sum-of-two-s12-const-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/sum-of-two-s12-const-3.c diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md index a590df545d7d..a9ee346af6f0 100644 --- a/gcc/config/riscv/constraints.md +++ b/gcc/config/riscv/constraints.md @@ -80,6 +80,12 @@ (and (match_code "const_int") (match_test "LUI_OPERAND (ival)"))) +(define_constraint "MiG" + "const can be represented as sum of any S12 values." + (and (match_code "const_int") + (ior (match_test "IN_RANGE (ival, 2048, 4094)") + (match_test "IN_RANGE (ival, -4096, -2049)")))) + (define_constraint "Ds3" "@internal 1, 2 or 3 immediate" diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index e7d797d4dbf0..8948fbfc3631 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -428,6 +428,12 @@ return true; }) +(define_predicate "const_two_s12" + (match_code "const_int") +{ + return SUM_OF_TWO_S12 (INTVAL (op)); +}) + ;; CORE-V Predicates: (define_predicate "immediate_register_operand" (ior (match_operand 0 "register_operand") diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index e5aebf3fc3d5..706dc204e643 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -165,6 +165,7 @@ extern bool riscv_shamt_matches_mask_p (int, HOST_WIDE_INT); extern void riscv_subword_address (rtx, rtx *, rtx *, rtx *, rtx *); extern void riscv_lshift_subword (machine_mode, rtx, rtx, rtx *); extern enum memmodel riscv_union_memmodels (enum memmodel, enum memmodel); +extern bool riscv_reg_frame_related (rtx); /* Routines implemented in riscv-c.cc. */ void riscv_cpu_cpp_builtins (cpp_reader *); diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index a1e5a014bedf..4067505270e1 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -7145,6 +7145,17 @@ riscv_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to) return (to == HARD_FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM); } +/* Helper to determine if reg X pertains to stack. */ +bool +riscv_reg_frame_related (rtx x) +{ + return REG_P (x) + && (REGNO (x) == FRAME_POINTER_REGNUM + || REGNO (x) == HARD_FRAME_POINTER_REGNUM + || REGNO (x) == ARG_POINTER_REGNUM + || REGNO (x) == VIRTUAL_STACK_VARS_REGNUM); +} + /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer or argument pointer. TO is either the stack pointer or hard frame pointer. */ diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index 58d0b09bf7d9..0d27c0d378df 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -626,6 +626,21 @@ enum reg_class (((VALUE) | ((1UL<<31) - IMM_REACH)) == ((1UL<<31) - IMM_REACH) \ || ((VALUE) | ((1UL<<31) - IMM_REACH)) + IMM_REACH == 0) +/* True if a VALUE (constant) can be expressed as sum of two S12 constants + (in range -2048 to 2047). + Range check logic: + from: min S12 + 1 (or -1 depending on what side of zero) + to: two times the min S12 value (to max out S12 bits). */ + +#define SUM_OF_TWO_S12_N(VALUE) \ + (((VALUE) >= (-2048 * 2)) && ((VALUE) <= (-2048 - 1))) + +#define SUM_OF_TWO_S12_P(VALUE) \ + (((VALUE) >= (2047 + 1)) && ((VALUE) <= (2047 * 2))) + +#define SUM_OF_TWO_S12(VALUE) \ + (SUM_OF_TWO_S12_N (VALUE) || SUM_OF_TWO_S12_P (VALUE)) + /* If this is a single bit mask, then we can load it with bseti. Special handling of SImode 0x80000000 on RV64 is done in riscv_build_integer_1. */ #define SINGLE_BIT_MASK_OPERAND(VALUE) \ diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 4d6de9925572..f5dac342033e 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -703,6 +703,46 @@ [(set_attr "type" "arith") (set_attr "mode" "DI")]) +;; Special case of adding a reg and constant if latter is sum of two S12 +;; values (in range -2048 to 2047). Avoid materialized the const and fuse +;; into the add (with an additional add for 2nd value). Makes a 3 insn +;; sequence into 2 insn. + +(define_insn_and_split "*add3_const_sum_of_two_s12" + [(set (match_operand:P 0 "register_operand" "=r,r") + (plus:P (match_operand:P 1 "register_operand" " r,r") + (match_operand:P 2 "const_two_s12" " MiG,r")))] + "!riscv_reg_frame_related (operands[0])" +{ + /* operand matching MiG constraint is always meant to be split. */ + if (which_alternative == 0) + return "#"; + else + return "add %0,%1,%2"; +} + "" + [(set (match_dup 0) + (plus:P (match_dup 1) (match_dup 3))) + (set (match_dup 0) + (plus:P (match_dup 0) (match_dup 4)))] +{ + int val = INTVAL (operands[2]); + if (SUM_OF_TWO_S12_P (val)) + { + operands[3] = GEN_INT (2047); + operands[4] = GEN_INT (val - 2047); + } + else if (SUM_OF_TWO_S12_N (val)) + { + operands[3] = GEN_INT (-2048); + operands[4] = GEN_INT (val + 2048); + } + else + gcc_unreachable (); +} + [(set_attr "type" "arith") + (set_attr "mode" "")]) + (define_expand "addv4" [(set (match_operand:GPR 0 "register_operand" "=r,r") (plus:GPR (match_operand:GPR 1 "register_operand" " r,r") diff --git a/gcc/testsuite/gcc.target/riscv/sum-of-two-s12-const-1.c b/gcc/testsuite/gcc.target/riscv/sum-of-two-s12-const-1.c new file mode 100644 index 000000000000..4d6d135de5f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sum-of-two-s12-const-1.c @@ -0,0 +1,45 @@ +// TBD: This doesn't quite work for rv32 yet +/* { dg-do compile } */ +/* { dg-options { -march=rv64gcv -mabi=lp64d } } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ + +/* Ensure that gcc doesn't generate standlone li reg, 4096. */ +long +plus1(unsigned long i) +{ + return i + 2048; +} + +long +plus2(unsigned long i) +{ + return i + 4094; +} + +long +plus3(unsigned long i) +{ + return i + 2064; +} + +/* Ensure that gcc doesn't generate standlone li reg, -4096. */ +long +minus1(unsigned long i) +{ + return i - 4096; +} + +long +minus2(unsigned long i) +{ + return i - 2049; +} + +long +minus3(unsigned long i) +{ + return i - 2064; +} + +/* { dg-final { scan-assembler-not {li\t[a-x0-9]+,-4096} } } */ +/* { dg-final { scan-assembler-not {li\t[a-x0-9]+,4096} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sum-of-two-s12-const-2.c b/gcc/testsuite/gcc.target/riscv/sum-of-two-s12-const-2.c new file mode 100644 index 000000000000..9343b43c3106 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sum-of-two-s12-const-2.c @@ -0,0 +1,15 @@ +/* Reduced from glibc/stdio-common/tempnam.c. + Can't have invalid insn in final output: + add s0, sp, 2048 */ + +/* { dg-do compile } */ +/* { dg-options { -march=rv64gcv -mabi=lp64d -O2 } } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "O1" "-Og" "-Os" "-Oz" } } */ + +int a() { + char b[4096]; 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Mon, 13 May 2024 11:49:38 -0700 (PDT) From: Vineet Gupta To: gcc-patches@gcc.gnu.org Cc: Jeff Law , kito.cheng@gmail.com, Palmer Dabbelt , =?utf-8?q?Christoph_M=C3=BCllner?= , Robin Dapp , gnu-toolchain@rivosinc.com, Vineet Gupta Subject: [PATCH v2 2/2] RISC-V: avoid LUI based const mat in prologue/epilogue expansion [PR/105733] Date: Mon, 13 May 2024 11:49:32 -0700 Message-Id: <20240513184932.662109-3-vineetg@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513184932.662109-1-vineetg@rivosinc.com> References: <20240513184932.662109-1-vineetg@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-9.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_ASCII_DIVIDERS, KAM_SHORT, LIKELY_SPAM_BODY, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org If the constant used for stack offset can be expressed as sum of two S12 values, the constant need not be materialized (in a reg) and instead the two S12 bits can be added to instructions involved with frame pointer. This avoids burning a register and more importantly can often get down to be 2 insn vs. 3. The prev patches to generally avoid LUI based const materialization didn't fix this PR and need this directed fix in funcion prologue/epilogue expansion. This fix doesn't move the neddle for SPEC, at all, but it is still a win considering gcc generates one insn fewer than llvm for the test ;-) gcc-13.1 release | gcc 230823 | | | g6619b3d4c15c | This patch | clang/llvm --------------------------------------------------------------------------------- li t0,-4096 | li t0,-4096 | addi sp,sp,-2048 | addi sp,sp,-2048 addi t0,t0,2016 | addi t0,t0,2032 | add sp,sp,-16 | addi sp,sp,-32 li a4,4096 | add sp,sp,t0 | add a5,sp,a0 | add a1,sp,16 add sp,sp,t0 | addi a5,sp,-2032 | sb zero,0(a5) | add a0,a0,a1 li a5,-4096 | add a0,a5,a0 | addi sp,sp,2032 | sb zero,0(a0) addi a4,a4,-2032 | li t0, 4096 | addi sp,sp,32 | addi sp,sp,2032 add a4,a4,a5 | sb zero,2032(a0) | ret | addi sp,sp,48 addi a5,sp,16 | addi t0,t0,-2032 | | ret add a5,a4,a5 | add sp,sp,t0 | add a0,a5,a0 | ret | li t0,4096 | sd a5,8(sp) | sb zero,2032(a0)| addi t0,t0,-2016 | add sp,sp,t0 | ret | gcc/ChangeLog: PR target/105733 * config/riscv/riscv.h: New macros for with aligned offsets. * config/riscv/riscv.cc (riscv_split_sum_of_two_s12): New function to split a sum of two s12 values into constituents. (riscv_expand_prologue): Handle offset being sum of two S12. (riscv_expand_epilogue): Ditto. * config/riscv/riscv-protos.h (riscv_split_sum_of_two_s12): New. gcc/testsuite/ChangeLog: * gcc.target/riscv/pr105733.c: New Test. * gcc.target/riscv/rvv/autovec/vls/spill-1.c: Adjust to not expect LUI 4096. * gcc.target/riscv/rvv/autovec/vls/spill-2.c: Ditto. * gcc.target/riscv/rvv/autovec/vls/spill-3.c: Ditto. * gcc.target/riscv/rvv/autovec/vls/spill-4.c: Ditto. * gcc.target/riscv/rvv/autovec/vls/spill-5.c: Ditto. * gcc.target/riscv/rvv/autovec/vls/spill-6.c: Ditto. * gcc.target/riscv/rvv/autovec/vls/spill-7.c: Ditto. Signed-off-by: Vineet Gupta --- gcc/config/riscv/riscv-protos.h | 2 + gcc/config/riscv/riscv.cc | 74 +++++++++++++++++-- gcc/config/riscv/riscv.h | 7 ++ gcc/testsuite/gcc.target/riscv/pr105733.c | 15 ++++ .../riscv/rvv/autovec/vls/spill-1.c | 4 +- .../riscv/rvv/autovec/vls/spill-2.c | 4 +- .../riscv/rvv/autovec/vls/spill-3.c | 4 +- .../riscv/rvv/autovec/vls/spill-4.c | 4 +- .../riscv/rvv/autovec/vls/spill-5.c | 4 +- .../riscv/rvv/autovec/vls/spill-6.c | 4 +- .../riscv/rvv/autovec/vls/spill-7.c | 4 +- 11 files changed, 105 insertions(+), 21 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/pr105733.c diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 706dc204e643..6da6ae4d041f 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -166,6 +166,8 @@ extern void riscv_subword_address (rtx, rtx *, rtx *, rtx *, rtx *); extern void riscv_lshift_subword (machine_mode, rtx, rtx, rtx *); extern enum memmodel riscv_union_memmodels (enum memmodel, enum memmodel); extern bool riscv_reg_frame_related (rtx); +extern void riscv_split_sum_of_two_s12 (HOST_WIDE_INT, HOST_WIDE_INT *, + HOST_WIDE_INT *); /* Routines implemented in riscv-c.cc. */ void riscv_cpu_cpp_builtins (cpp_reader *); diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 4067505270e1..4b742489b272 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -4063,6 +4063,32 @@ riscv_split_doubleword_move (rtx dest, rtx src) riscv_emit_move (riscv_subword (dest, true), riscv_subword (src, true)); } } + +/* Constant VAL is known to be sum of two S12 constants. Break it into + comprising BASE and OFF. + Numerically S12 is -2048 to 2047, however it uses the more conservative + range -2048 to 2032 as offsets pertain to stack related registers. */ + +void +riscv_split_sum_of_two_s12 (HOST_WIDE_INT val, HOST_WIDE_INT *base, + HOST_WIDE_INT *off) +{ + if (SUM_OF_TWO_S12_N (val)) + { + *base = -2048; + *off = val - (-2048); + } + else if (SUM_OF_TWO_S12_P_ALGN (val)) + { + *base = 2032; + *off = val - 2032; + } + else + { + gcc_unreachable (); + } +} + /* Return the appropriate instructions to move SRC into DEST. Assume that SRC is operand 1 and DEST is operand 0. */ @@ -7852,6 +7878,17 @@ riscv_expand_prologue (void) GEN_INT (-constant_frame)); RTX_FRAME_RELATED_P (emit_insn (insn)) = 1; } + else if (SUM_OF_TWO_S12_ALGN (-constant_frame)) + { + HOST_WIDE_INT base, off; + riscv_split_sum_of_two_s12 (-constant_frame, &base, &off); + insn = gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx, + GEN_INT (base)); + RTX_FRAME_RELATED_P (emit_insn (insn)) = 1; + insn = gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx, + GEN_INT (off)); + RTX_FRAME_RELATED_P (emit_insn (insn)) = 1; + } else { riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode), GEN_INT (-constant_frame)); @@ -8074,14 +8111,26 @@ riscv_expand_epilogue (int style) } else { - if (!SMALL_OPERAND (adjust_offset.to_constant ())) + HOST_WIDE_INT adj_off_value = adjust_offset.to_constant (); + if (SMALL_OPERAND (adj_off_value)) + { + adjust = GEN_INT (adj_off_value); + } + else if (SUM_OF_TWO_S12_ALGN (adj_off_value)) + { + HOST_WIDE_INT base, off; + riscv_split_sum_of_two_s12 (adj_off_value, &base, &off); + insn = gen_add3_insn (stack_pointer_rtx, hard_frame_pointer_rtx, + GEN_INT (base)); + RTX_FRAME_RELATED_P (insn) = 1; + adjust = GEN_INT (off); + } + else { riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode), - GEN_INT (adjust_offset.to_constant ())); + GEN_INT (adj_off_value)); adjust = RISCV_PROLOGUE_TEMP (Pmode); } - else - adjust = GEN_INT (adjust_offset.to_constant ()); } insn = emit_insn ( @@ -8148,10 +8197,21 @@ riscv_expand_epilogue (int style) /* Get an rtx for STEP1 that we can add to BASE. Skip if adjust equal to zero. */ - if (step1.to_constant () != 0) + HOST_WIDE_INT step1_value = step1.to_constant (); + if (step1_value != 0) { - rtx adjust = GEN_INT (step1.to_constant ()); - if (!SMALL_OPERAND (step1.to_constant ())) + rtx adjust = GEN_INT (step1_value); + if (SUM_OF_TWO_S12_ALGN (step1_value)) + { + HOST_WIDE_INT base, off; + riscv_split_sum_of_two_s12 (step1_value, &base, &off); + insn = emit_insn (gen_add3_insn (stack_pointer_rtx, + stack_pointer_rtx, + GEN_INT (base))); + RTX_FRAME_RELATED_P (insn) = 1; + adjust = GEN_INT (off); + } + else if (!SMALL_OPERAND (step1_value)) { riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode), adjust); adjust = RISCV_PROLOGUE_TEMP (Pmode); diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index 0d27c0d378df..d6b14c4d6205 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -641,6 +641,13 @@ enum reg_class #define SUM_OF_TWO_S12(VALUE) \ (SUM_OF_TWO_S12_N (VALUE) || SUM_OF_TWO_S12_P (VALUE)) +/* Variant with first value 8 byte aligned if involving stack regs. */ +#define SUM_OF_TWO_S12_P_ALGN(VALUE) \ + (((VALUE) >= (2032 + 1)) && ((VALUE) <= (2032 * 2))) + +#define SUM_OF_TWO_S12_ALGN(VALUE) \ + (SUM_OF_TWO_S12_N (VALUE) || SUM_OF_TWO_S12_P_ALGN (VALUE)) + /* If this is a single bit mask, then we can load it with bseti. Special handling of SImode 0x80000000 on RV64 is done in riscv_build_integer_1. */ #define SINGLE_BIT_MASK_OPERAND(VALUE) \ diff --git a/gcc/testsuite/gcc.target/riscv/pr105733.c b/gcc/testsuite/gcc.target/riscv/pr105733.c new file mode 100644 index 000000000000..6156c36dc7ef --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr105733.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options { -march=rv64gcv -mabi=lp64d } } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ + +#define BUF_SIZE 2064 + +void +foo(unsigned long i) +{ + volatile char buf[BUF_SIZE]; + + buf[i] = 0; +} + +/* { dg-final { scan-assembler-not {li\t[a-x0-9]+,4096} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-1.c index b64c73f34f13..6afcf1db593b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-1.c @@ -129,5 +129,5 @@ spill_12 (int8_t *in, int8_t *out) /* { dg-final { scan-assembler-times {addi\tsp,sp,-256} 1 } } */ /* { dg-final { scan-assembler-times {addi\tsp,sp,-512} 1 } } */ /* { dg-final { scan-assembler-times {addi\tsp,sp,-1024} 1 } } */ -/* { dg-final { scan-assembler-times {addi\tsp,sp,-2048} 1 } } */ -/* { dg-final { scan-assembler-times {li\t[a-x0-9]+,-4096\s+add\tsp,sp,[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {addi\tsp,sp,-2048} 3 } } */ +/* { dg-final { scan-assembler-times {addi\tsp,sp,2032} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-2.c index 8fcdca705384..544e8628a27b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-2.c @@ -120,5 +120,5 @@ spill_11 (int16_t *in, int16_t *out) /* { dg-final { scan-assembler-times {addi\tsp,sp,-256} 1 } } */ /* { dg-final { scan-assembler-times {addi\tsp,sp,-512} 1 } } */ /* { dg-final { scan-assembler-times {addi\tsp,sp,-1024} 1 } } */ -/* { dg-final { scan-assembler-times {addi\tsp,sp,-2048} 1 } } */ -/* { dg-final { scan-assembler-times {li\t[a-x0-9]+,-4096\s+add\tsp,sp,[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {addi\tsp,sp,-2048} 3 } } */ +/* { dg-final { scan-assembler-times {addi\tsp,sp,2032} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-3.c index ca296ce02d66..4bfeb07e9aca 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-3.c @@ -111,5 +111,5 @@ spill_10 (int32_t *in, int32_t *out) /* { dg-final { scan-assembler-times {addi\tsp,sp,-256} 1 } } */ /* { dg-final { scan-assembler-times {addi\tsp,sp,-512} 1 } } */ /* { dg-final { scan-assembler-times {addi\tsp,sp,-1024} 1 } } */ -/* { dg-final { scan-assembler-times {addi\tsp,sp,-2048} 1 } } */ -/* { dg-final { scan-assembler-times {li\t[a-x0-9]+,-4096\s+add\tsp,sp,[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {addi\tsp,sp,-2048} 3 } } */ +/* { dg-final { scan-assembler-times {addi\tsp,sp,2032} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-4.c index ef61d9a2c0c3..1faf31ffd8e0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-4.c @@ -102,5 +102,5 @@ spill_9 (int64_t *in, int64_t *out) /* { dg-final { scan-assembler-times {addi\tsp,sp,-256} 1 } } */ /* { dg-final { scan-assembler-times {addi\tsp,sp,-512} 1 } } */ /* { dg-final { scan-assembler-times {addi\tsp,sp,-1024} 1 } } */ -/* { dg-final { scan-assembler-times {addi\tsp,sp,-2048} 1 } } */ -/* { dg-final { scan-assembler-times {li\t[a-x0-9]+,-4096\s+add\tsp,sp,[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {addi\tsp,sp,-2048} 3 } } */ +/* { dg-final { scan-assembler-times {addi\tsp,sp,2032} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-5.c index 150135a91103..0c8dccc518e3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-5.c @@ -120,5 +120,5 @@ spill_11 (_Float16 *in, _Float16 *out) /* { dg-final { scan-assembler-times {addi\tsp,sp,-256} 1 } } */ /* { dg-final { scan-assembler-times {addi\tsp,sp,-512} 1 } } */ /* { dg-final { scan-assembler-times {addi\tsp,sp,-1024} 1 } } */ -/* { dg-final { scan-assembler-times {addi\tsp,sp,-2048} 1 } } */ -/* { dg-final { scan-assembler-times {li\t[a-x0-9]+,-4096\s+add\tsp,sp,[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {addi\tsp,sp,-2048} 3 } } */ +/* { dg-final { scan-assembler-times {addi\tsp,sp,2032} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-6.c index c5d2d0194348..8bf53b84d1cd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-6.c @@ -111,5 +111,5 @@ spill_10 (float *in, float *out) /* { dg-final { scan-assembler-times {addi\tsp,sp,-256} 1 } } */ /* { dg-final { scan-assembler-times {addi\tsp,sp,-512} 1 } } */ /* { dg-final { scan-assembler-times {addi\tsp,sp,-1024} 1 } } */ -/* { dg-final { scan-assembler-times {addi\tsp,sp,-2048} 1 } } */ -/* { dg-final { scan-assembler-times {li\t[a-x0-9]+,-4096\s+add\tsp,sp,[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {addi\tsp,sp,-2048} 3 } } */ +/* { dg-final { scan-assembler-times {addi\tsp,sp,2032} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-7.c index 70ca683908db..e3980a295406 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-7.c @@ -102,5 +102,5 @@ spill_9 (int64_t *in, int64_t *out) /* { dg-final { scan-assembler-times {addi\tsp,sp,-256} 1 } } */ /* { dg-final { scan-assembler-times {addi\tsp,sp,-512} 1 } } */ /* { dg-final { scan-assembler-times {addi\tsp,sp,-1024} 1 } } */ -/* { dg-final { scan-assembler-times {addi\tsp,sp,-2048} 1 } } */ -/* { dg-final { scan-assembler-times {li\t[a-x0-9]+,-4096\s+add\tsp,sp,[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {addi\tsp,sp,-2048} 3 } } */ +/* { dg-final { scan-assembler-times {addi\tsp,sp,2032} 1 } } */