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X-CSE-ConnectionGUID: YKbdCszYTJaLqGZh0rJTBg== X-CSE-MsgGUID: ZjpPqBjBRF2pxu+AImqn0Q== X-IronPort-AV: E=McAfee;i="6600,9927,11069"; a="11632100" X-IronPort-AV: E=Sophos;i="6.08,153,1712646000"; d="scan'208";a="11632100" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2024 00:54:56 -0700 X-CSE-ConnectionGUID: raxkXquTSBGrokBAbDhS4A== X-CSE-MsgGUID: JRzREZXLR9aoEg1pIXqFEg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,153,1712646000"; d="scan'208";a="34723360" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orviesa004.jf.intel.com with ESMTP; 11 May 2024 00:54:54 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 59CEC1009162; Sat, 11 May 2024 15:54:53 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, Pan Li Subject: [PATCH v1] RISC-V: Bugfix ICE for RVV intrinisc vfw on _Float16 scalar Date: Sat, 11 May 2024 15:54:50 +0800 Message-Id: <20240511075450.2245947-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li For the vfw vx format RVV intrinsic, the scalar type _Float16 also requires the zvfh extension. Unfortunately, we only check the vector tree type and miss the scalar _Float16 type checking. For example: vfloat32mf2_t test_vfwsub_wf_f32mf2(vfloat32mf2_t vs2, _Float16 rs1, size_t vl) { return __riscv_vfwsub_wf_f32mf2(vs2, rs1, vl); } It should report some error message like zvfh extension is required instead of ICE for unreg insn. This patch would like to make up such kind of validation for _Float16 in the RVV intrinsic API. It will report some error like below when there is no zvfh enabled. error: built-in function '__riscv_vfwsub_wf_f32mf2(vs2, rs1, vl)' requires the zvfhmin or zvfh ISA extension PR target/114988 Passed the rv64gcv fully regression tests, included c/c++/fortran. gcc/ChangeLog: * config/riscv/riscv-vector-builtins.cc (validate_instance_type_required_extensions): New func impl to validate the intrinisc func type ops. (expand_builtin): Validate instance type before expand. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr114988-1.c: New test. * gcc.target/riscv/rvv/base/pr114988-2.c: New test. Signed-off-by: Pan Li Signed-off-by: Pan Li --- gcc/config/riscv/riscv-vector-builtins.cc | 51 +++++++++++++++++++ .../gcc.target/riscv/rvv/base/pr114988-1.c | 9 ++++ .../gcc.target/riscv/rvv/base/pr114988-2.c | 9 ++++ 3 files changed, 69 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr114988-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr114988-2.c diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc index 192a6c230d1..3fdb4400d70 100644 --- a/gcc/config/riscv/riscv-vector-builtins.cc +++ b/gcc/config/riscv/riscv-vector-builtins.cc @@ -4632,6 +4632,54 @@ gimple_fold_builtin (unsigned int code, gimple_stmt_iterator *gsi, gcall *stmt) return gimple_folder (rfn.instance, rfn.decl, gsi, stmt).fold (); } +static bool +validate_instance_type_required_extensions (const rvv_type_info type, + tree exp) +{ + uint64_t exts = type.required_extensions; + + if ((exts & RVV_REQUIRE_ELEN_FP_16) && + !TARGET_VECTOR_ELEN_FP_16_P (riscv_vector_elen_flags)) + { + error_at (EXPR_LOCATION (exp), + "built-in function %qE requires the " + "zvfhmin or zvfh ISA extension", + exp); + return false; + } + + if ((exts & RVV_REQUIRE_ELEN_FP_32) && + !TARGET_VECTOR_ELEN_FP_32_P (riscv_vector_elen_flags)) + { + error_at (EXPR_LOCATION (exp), + "built-in function %qE requires the " + "zve32f, zve64f, zve64d or v ISA extension", + exp); + return false; + } + + if ((exts & RVV_REQUIRE_ELEN_FP_64) && + !TARGET_VECTOR_ELEN_FP_64_P (riscv_vector_elen_flags)) + { + error_at (EXPR_LOCATION (exp), + "built-in function %qE requires the zve64d or v ISA extension", + exp); + return false; + } + + if ((exts & RVV_REQUIRE_ELEN_64) && + !TARGET_VECTOR_ELEN_64_P (riscv_vector_elen_flags)) + { + error_at (EXPR_LOCATION (exp), + "built-in function %qE requires the " + "zve64x, zve64f, zve64d or v ISA extension", + exp); + return false; + } + + return true; +} + /* Expand a call to the RVV function with subcode CODE. EXP is the call expression and TARGET is the preferred location for the result. Return the value of the lhs. */ @@ -4649,6 +4697,9 @@ expand_builtin (unsigned int code, tree exp, rtx target) return target; } + if (!validate_instance_type_required_extensions (rfn.instance.type, exp)) + return target; + return function_expander (rfn.instance, rfn.decl, exp, target).expand (); } diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114988-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114988-1.c new file mode 100644 index 00000000000..b8474804c88 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114988-1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ + +#include "riscv_vector.h" + +vfloat32mf2_t test_vfwsub_wf_f32mf2(vfloat32mf2_t vs2, _Float16 rs1, size_t vl) +{ + return __riscv_vfwsub_wf_f32mf2(vs2, rs1, vl); /* { dg-error {built-in function '__riscv_vfwsub_wf_f32mf2\(vs2, rs1, vl\)' requires the zvfhmin or zvfh ISA extension} } */ +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114988-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114988-2.c new file mode 100644 index 00000000000..49aa3141af3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114988-2.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ + +#include "riscv_vector.h" + +vfloat32mf2_t test_vfwadd_wf_f32mf2(vfloat32mf2_t vs2, _Float16 rs1, size_t vl) +{ + return __riscv_vfwadd_wf_f32mf2(vs2, rs1, vl); /* { dg-error {built-in function '__riscv_vfwadd_wf_f32mf2\(vs2, rs1, vl\)' requires the zvfhmin or zvfh ISA extension} } */ +}