From patchwork Wed May 1 08:16:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Hoyes X-Patchwork-Id: 1930081 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4VTqgG3p1yz1ymc for ; Wed, 1 May 2024 18:17:30 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id A7BA388B28; Wed, 1 May 2024 10:17:18 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 6180688B22; Wed, 1 May 2024 10:17:18 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.2 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id 6150B88B33 for ; Wed, 1 May 2024 10:16:58 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=peter.hoyes@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AF0502F4; Wed, 1 May 2024 01:17:23 -0700 (PDT) Received: from e133390.cambridge.arm.com (unknown [10.1.198.41]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C02B13F793; Wed, 1 May 2024 01:16:55 -0700 (PDT) From: Peter Hoyes To: u-boot@lists.denx.de Cc: trini@konsulko.com, andre.przywara@arm.com, mk7.kang@samsung.com, ilias.apalodimas@linaro.org, wqu@suse.com, neil.armstrong@linaro.org, sr@denx.de, michal.simek@amd.com, patrick.delaunay@foss.st.com, sjg@chromium.org, patrice.chotard@foss.st.com, quentin.schulz@theobroma-systems.com, Peter Hoyes Subject: [PATCH v2 1/2] arm: Move sev() and wfe() definitions to common Arm header file Date: Wed, 1 May 2024 09:16:32 +0100 Message-Id: <20240501081633.120913-2-peter.hoyes@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240501081633.120913-1-peter.hoyes@arm.com> References: <20240501081633.120913-1-peter.hoyes@arm.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Peter Hoyes The sev() and wfe() asm macros are currently defined only for mach-exynos. As these are common Arm instructions, move them to the common asm/system.h header file, for both Armv7 and Armv8, so they can be used by other machines. wfe may theoretically trigger a context switch if an interrupt occurs so add a memory barrier to this call. Signed-off-by: Peter Hoyes Reviewed-by: Andre Przywara --- arch/arm/include/asm/system.h | 9 +++++++++ arch/arm/mach-exynos/include/mach/system.h | 19 ------------------- 2 files changed, 9 insertions(+), 19 deletions(-) diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 43f7503571..51123c2968 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -154,6 +154,13 @@ enum dcache_option { "wfi" : : : "memory"); \ }) +#define wfe() \ + ({asm volatile( \ + "wfe" : : : "memory"); \ + }) + +#define sev() asm volatile("sev") + static inline unsigned int current_el(void) { unsigned long el; @@ -369,6 +376,8 @@ void switch_to_hypervisor_ret(void); #ifdef __ARM_ARCH_7A__ #define wfi() __asm__ __volatile__ ("wfi" : : : "memory") +#define wfe() __asm__ __volatile__ ("wfe" : : : "memory") +#define sev() __asm__ __volatile__ ("sev") #else #define wfi() #endif diff --git a/arch/arm/mach-exynos/include/mach/system.h b/arch/arm/mach-exynos/include/mach/system.h index 5d0bebac57..0aed4c3e2b 100644 --- a/arch/arm/mach-exynos/include/mach/system.h +++ b/arch/arm/mach-exynos/include/mach/system.h @@ -36,25 +36,6 @@ struct exynos5_sysreg { #define USB20_PHY_CFG_HOST_LINK_EN (1 << 0) -/* - * This instruction causes an event to be signaled to all cores - * within a multiprocessor system. If SEV is implemented, - * WFE must also be implemented. - */ -#define sev() __asm__ __volatile__ ("sev\n\t" : : ); -/* - * If the Event Register is not set, WFE suspends execution until - * one of the following events occurs: - * - an IRQ interrupt, unless masked by the CPSR I-bit - * - an FIQ interrupt, unless masked by the CPSR F-bit - * - an Imprecise Data abort, unless masked by the CPSR A-bit - * - a Debug Entry request, if Debug is enabled - * - an Event signaled by another processor using the SEV instruction. - * If the Event Register is set, WFE clears it and returns immediately. - * If WFE is implemented, SEV must also be implemented. - */ -#define wfe() __asm__ __volatile__ ("wfe\n\t" : : ); - /* Move 0xd3 value to CPSR register to enable SVC mode */ #define svc32_mode_en() __asm__ __volatile__ \ ("@ I&F disable, Mode: 0x13 - SVC\n\t" \ From patchwork Wed May 1 08:16:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Hoyes X-Patchwork-Id: 1930080 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4VTqg51r0Jz1ymc for ; Wed, 1 May 2024 18:17:21 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 4626D88B21; Wed, 1 May 2024 10:17:18 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 3258A88B22; Wed, 1 May 2024 10:17:17 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.2 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id 00AFF88B2E for ; Wed, 1 May 2024 10:17:01 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=peter.hoyes@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 89C8C339; Wed, 1 May 2024 01:17:26 -0700 (PDT) Received: from e133390.cambridge.arm.com (unknown [10.1.198.41]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 9B6D73F793; Wed, 1 May 2024 01:16:58 -0700 (PDT) From: Peter Hoyes To: u-boot@lists.denx.de Cc: trini@konsulko.com, andre.przywara@arm.com, mk7.kang@samsung.com, ilias.apalodimas@linaro.org, wqu@suse.com, neil.armstrong@linaro.org, sr@denx.de, michal.simek@amd.com, patrick.delaunay@foss.st.com, sjg@chromium.org, patrice.chotard@foss.st.com, quentin.schulz@theobroma-systems.com, Peter Hoyes Subject: [PATCH v2 2/2] armv8: generic_timer: Use event stream for udelay Date: Wed, 1 May 2024 09:16:33 +0100 Message-Id: <20240501081633.120913-3-peter.hoyes@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240501081633.120913-1-peter.hoyes@arm.com> References: <20240501081633.120913-1-peter.hoyes@arm.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Peter Hoyes Polling cntpct_el0 in a tight loop for delays is inefficient. This is particularly apparent on Arm FVPs, which do not simulate real time, meaning that a 1s sleep can take a couple of orders of magnitude longer to execute in wall time. If running at EL2 or above (where CNTHCTL_EL2 is available), enable the cntpct_el0 event stream temporarily and use wfe to implement the delay more efficiently. The event period is chosen as a trade-off between efficiency and the fact that Arm FVPs do not typically simulate real time. This is only implemented for Armv8 boards, where an architectural timer exists, and only enabled by default for the ARCH_VEXPRESS64 board family. Signed-off-by: Peter Hoyes Reviewed-by: Andre Przywara --- arch/arm/cpu/armv8/Kconfig | 8 ++++++++ arch/arm/cpu/armv8/generic_timer.c | 27 +++++++++++++++++++++++++++ arch/arm/include/asm/system.h | 6 ++++-- 3 files changed, 39 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index 9f0fb369f7..199335cd60 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -191,6 +191,14 @@ config ARMV8_EA_EL3_FIRST Exception handling at all exception levels for External Abort and SError interrupt exception are taken in EL3. +config ARMV8_UDELAY_EVENT_STREAM + bool "Use the event stream for udelay" + default y if ARCH_VEXPRESS64 + help + Use the event stream provided by the AArch64 architectural timer for + delays. This is more efficient than the default polling + implementation. + menuconfig ARMV8_CRYPTO bool "ARM64 Accelerated Cryptographic Algorithms" diff --git a/arch/arm/cpu/armv8/generic_timer.c b/arch/arm/cpu/armv8/generic_timer.c index 8f83372cbc..e18b5c8187 100644 --- a/arch/arm/cpu/armv8/generic_timer.c +++ b/arch/arm/cpu/armv8/generic_timer.c @@ -115,3 +115,30 @@ ulong timer_get_boot_us(void) return val / get_tbclk(); } + +#if CONFIG_IS_ENABLED(ARMV8_UDELAY_EVENT_STREAM) +void __udelay(unsigned long usec) +{ + u64 target = get_ticks() + usec_to_tick(usec); + + /* At EL2 or above, use the event stream to avoid polling CNTPCT_EL0 so often */ + if (current_el() >= 2) { + u32 cnthctl_val; + const u8 event_period = 0x7; + + asm volatile("mrs %0, cnthctl_el2" : "=r" (cnthctl_val)); + asm volatile("msr cnthctl_el2, %0" : : "r" + (cnthctl_val | CNTHCTL_EL2_EVNT_EN | CNTHCTL_EL2_EVNT_I(event_period))); + + while (get_ticks() + (1ULL << event_period) <= target) + wfe(); + + /* Reset the event stream */ + asm volatile("msr cnthctl_el2, %0" : : "r" (cnthctl_val)); + } + + /* Fall back to polling CNTPCT_EL0 */ + while (get_ticks() <= target) + ; +} +#endif diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 51123c2968..7e30cac32a 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -69,8 +69,10 @@ /* * CNTHCTL_EL2 bits definitions */ -#define CNTHCTL_EL2_EL1PCEN_EN (1 << 1) /* Physical timer regs accessible */ -#define CNTHCTL_EL2_EL1PCTEN_EN (1 << 0) /* Physical counter accessible */ +#define CNTHCTL_EL2_EVNT_EN BIT(2) /* Enable the event stream */ +#define CNTHCTL_EL2_EVNT_I(val) ((val) << 4) /* Event stream trigger bits */ +#define CNTHCTL_EL2_EL1PCEN_EN (1 << 1) /* Physical timer regs accessible */ +#define CNTHCTL_EL2_EL1PCTEN_EN (1 << 0) /* Physical counter accessible */ /* * HCR_EL2 bits definitions