From patchwork Tue Apr 30 12:00:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 1929443 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20201202 header.b=EosXEdTe; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=147.75.80.249; helo=am.mirrors.kernel.org; envelope-from=devicetree+bounces-63972-incoming-dt=patchwork.ozlabs.org@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from am.mirrors.kernel.org (am.mirrors.kernel.org [147.75.80.249]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4VTJj40SG9z20fY for ; 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a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1714478521; bh=2auuQGe9uHpx39X2DRGeyL4wn09dTQhuOpMdAqllMYs=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=EosXEdTek2E40smXhuEIGDxUvmmW9wEsWePza5cW+B9qJbPla0yG6LphRr07y/ypt YP5BI19dzXKR4VzkA2sqkEghrbFNEHcgYAjVJ9PGmTPjdRPRz58mrgtv5D775EeEVT KCCpirt/XxvDnp3Uvv5tQF2FFMJtJz7/SZ35wW6jd85pSEyWJz0iu7JKucmUCkhutM mPCVXt8m0+ZnIU+Maeh2otyBzLX6AW5LcZOMEPi3IISrST12b0MDZe8tVfSdWjh7XD yqs+jlMKUb4Zk2wkgOmPmWa92HuyxqqRDCqDx2KIWo/rhbYwpTyNJ5OG9NZQqnYN/7 yiYZajI2Befkw== From: Niklas Cassel Date: Tue, 30 Apr 2024 14:00:58 +0200 Subject: [PATCH v2 01/14] dt-bindings: PCI: snps,dw-pcie-ep: Add vendor specific reg-name Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240430-rockchip-pcie-ep-v1-v2-1-a0f5ee2a77b6@kernel.org> References: <20240430-rockchip-pcie-ep-v1-v2-0-a0f5ee2a77b6@kernel.org> In-Reply-To: <20240430-rockchip-pcie-ep-v1-v2-0-a0f5ee2a77b6@kernel.org> To: Jingoo Han , Manivannan Sadhasivam , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Niklas Cassel , Kishon Vijay Abraham I , Arnd Bergmann , Damien Le Moal , Jon Lin , Shawn Lin , Simon Xue Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1296; i=cassel@kernel.org; h=from:subject:message-id; bh=2auuQGe9uHpx39X2DRGeyL4wn09dTQhuOpMdAqllMYs=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNIM7m54EhHDfYpZSPL3KQkrk0aO9Vm8vs+1ea82a8kG5 8+emHqlo5SFQYyLQVZMkcX3h8v+4m73KccV79jAzGFlAhnCwMUpABPJV2D4X7T+/puP6Y6remsl 3aVC1mbc7vhpNVP50OS+y3WSgfzP/BkZuluDGAVWfLg2d9fvRZEBbgdcjbZN3pR+8VViy5Rzs04 94QIA X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA Considering that some drivers (e.g. pcie-dw-rockchip.c) already use the reg-name "apb" for the device tree binding in Root Complex mode (snps,dw-pcie.yaml), it doesn't make sense that those drivers should use a different reg-name when running in Endpoint mode (snps,dw-pcie-ep.yaml). Therefore, since "apb" is already defined in snps,dw-pcie.yaml, add it also for snps,dw-pcie-ep.yaml. Signed-off-by: Niklas Cassel Reviewed-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml index bbdb01d22848..00dec01f1f73 100644 --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml @@ -100,7 +100,7 @@ properties: for new bindings. oneOf: - description: See native 'elbi/app' CSR region for details. - enum: [ link, appl ] + enum: [ apb, link, appl ] - description: See native 'atu' CSR region for details. enum: [ atu_dma ] allOf: From patchwork Tue Apr 30 12:00:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 1929442 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714478526; c=relaxed/simple; bh=dazCN/iT/MHdY+ckymlAcfBjUpa3OmMTl+4+NDKJR2A=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=aAy5yonV2Qx1pWL9asCBn1x9oHmsijpDbu0pmJ64O2yrjsA0fqlHULVgvaQxDpyn3/uxpwpMo7/QKJcH9YYBkgRoRhkbMxREN0frZ05oTojfsUVYvSu82lKJHDM8eGQfgL/uxdd6UU3vlCsu9FfWKa3fWT3ruVLC8OuFmjbiERw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=GmLBbkco; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id B9693C4AF1B; Tue, 30 Apr 2024 12:02:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1714478525; bh=dazCN/iT/MHdY+ckymlAcfBjUpa3OmMTl+4+NDKJR2A=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=GmLBbkco7H+9TF70s3xCJzzCfE+wdzetILLrSRfKajcLXOUyneNVwNAo2N0wW/2Qu JVs/Y6Zk1mr5uKcN1+7av/t5pKjBiAGS+brI7STdhgcZS/XTDp2OJLEiMwMRHcWmQV itYQP8UD5ZA/mI7VxSN6Wc3ekS5uXsvw68IsM31imleh37XZzmyORiXqbxZlEOBQ7B jEtwHGzrjebJBmyCAcJpV8WeIOZm1n8sHSB9iX230DK7X9H7V9qHWjBeTMVlsXLjnS ptfChZylMwPiEjKjertC235sJDxMHxsiaE+ChLcxr9nEgMdJaKPdsemMK+36b6yVeB cvISqnHavpxtA== From: Niklas Cassel Date: Tue, 30 Apr 2024 14:00:59 +0200 Subject: [PATCH v2 02/14] dt-bindings: PCI: snps,dw-pcie-ep: Add vendor specific interrupt-names Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240430-rockchip-pcie-ep-v1-v2-2-a0f5ee2a77b6@kernel.org> References: <20240430-rockchip-pcie-ep-v1-v2-0-a0f5ee2a77b6@kernel.org> In-Reply-To: <20240430-rockchip-pcie-ep-v1-v2-0-a0f5ee2a77b6@kernel.org> To: Jingoo Han , Manivannan Sadhasivam , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Niklas Cassel , Kishon Vijay Abraham I , Arnd Bergmann , Damien Le Moal , Jon Lin , Shawn Lin , Simon Xue Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1267; i=cassel@kernel.org; h=from:subject:message-id; bh=dazCN/iT/MHdY+ckymlAcfBjUpa3OmMTl+4+NDKJR2A=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNIM7m5wV9fa+ca2plhz546ct3//n9v0lXNZ8tKMOcf2h /1s2zxjQkcpC4MYF4OsmCKL7w+X/cXd7lOOK96xgZnDygQyhIGLUwAmYjmFkeHQvPVe1rsP/PMS bLy9+FVcTWhc8HJ1/d7c+1ueJzRus2hh+Gd1jdEjKMfuqtt3B50n1vb6QedjFq6Uf2W3ZFWKDWd WFRsA X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA Considering that some drivers (e.g. pcie-dw-rockchip.c) already use the interrupt-names "sys", "pmc", "msg", "err" for the device tree binding in Root Complex mode (snps,dw-pcie.yaml), it doesn't make sense that those drivers should use different interrupt-names when running in Endpoint mode (snps,dw-pcie-ep.yaml). Therefore, since "sys", "pmc", "msg", "err" are already defined in snps,dw-pcie.yaml, add them also for snps,dw-pcie-ep.yaml. Signed-off-by: Niklas Cassel Reviewed-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml index 00dec01f1f73..f5f12cbc2cb3 100644 --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml @@ -156,7 +156,7 @@ properties: for new bindings. oneOf: - description: See native "app" IRQ for details - enum: [ intr ] + enum: [ intr, sys, pmc, msg, err ] max-functions: maximum: 32 From patchwork Tue Apr 30 12:01:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 1929445 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714478530; c=relaxed/simple; bh=MgvdOL0gkl34L22gpJGsJpktQEWaY6MRdjg4t+pKTZ4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=N9a7SjB3yuPHWzvmKi956lb9iTfTLBv329WpVxOzg+F7oZad+iBg6dN9E4LbUTgVbFi/P83ijYXXBGAnjA0xzs+XJ6W3k3XtpgNkUZZ4++4nSiKZXTqYp4omxVaJy02I9bbJxyKxbRvT/Vn0XpwCCTL+sUOjPnTsfjZiluTXCCY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=cI1UUdyJ; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id F1CF0C4AF19; Tue, 30 Apr 2024 12:02:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1714478529; bh=MgvdOL0gkl34L22gpJGsJpktQEWaY6MRdjg4t+pKTZ4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=cI1UUdyJQ6nyysGSO+1CFiMo62exm3q0sFo04KTrjpmYiOW67SwkDuj9cRNXEN11s wSnF0O7y79kXJwkUWHGrELr5bH+QlrU5yMipuuudfpGgSb3vA7GpSV9rzrzVBDAluN VmdlApL/NjvYILsWii/g6Eye6VHZAoAeV0PeYnH1sQOLQdnag8tbSPXgpp3INP8QX+ PIRR2tYDbGz+bGoavGTRKAeEUj+Fq1PtCMjKfxdM4iE4ZORcpGVLyhaIqQtIRsd56I 77Bbcn4BowgktzugL1IPpW+k0v+9ZglQVHXFROw/sBoGUQoHvyNPhYq2OC8BeQU3Ok ogZ7mR+B9cDIQ== From: Niklas Cassel Date: Tue, 30 Apr 2024 14:01:00 +0200 Subject: [PATCH v2 03/14] dt-bindings: PCI: snps,dw-pcie-ep: Add tx_int{a,b,c,d} legacy irqs Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240430-rockchip-pcie-ep-v1-v2-3-a0f5ee2a77b6@kernel.org> References: <20240430-rockchip-pcie-ep-v1-v2-0-a0f5ee2a77b6@kernel.org> In-Reply-To: <20240430-rockchip-pcie-ep-v1-v2-0-a0f5ee2a77b6@kernel.org> To: Jingoo Han , Manivannan Sadhasivam , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Niklas Cassel , Kishon Vijay Abraham I , Arnd Bergmann , Damien Le Moal , Jon Lin , Shawn Lin , Simon Xue Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1672; i=cassel@kernel.org; h=from:subject:message-id; bh=MgvdOL0gkl34L22gpJGsJpktQEWaY6MRdjg4t+pKTZ4=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNIM7m74LT61fuHJ1GeOp0xSvxu7LDd9d7BFXTVe+2UK6 42p3lLGHaUsDGJcDLJiiiy+P1z2F3e7TzmueMcGZg4rE8gQBi5OAZjIp80M/x3+/Im7ezlCNc/5 x4Hi/z/zby/I6tylEpLMzsH59UMq11OGP/zr778T9bgTftz889UJtwrNwlkSfU4FMEx4raB5fAJ rGxsA X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA The DWC core has four interrupt signals: tx_inta, tx_intb, tx_intc, tx_intd that are triggered when the PCIe controller (when running in Endpoint mode) has sent an Assert_INTA Message to the upstream device. Some DWC controllers have these interrupt in a combined interrupt signal. Add the description of these interrupts to the device tree binding. Signed-off-by: Niklas Cassel Reviewed-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml index f5f12cbc2cb3..f474b9e3fc7e 100644 --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml @@ -151,6 +151,15 @@ properties: Application-specific IRQ raised depending on the vendor-specific events basis. const: app + - description: + Interrupts triggered when the controller itself (in Endpoint mode) + has sent an Assert_INT{A,B,C,D}/Desassert_INT{A,B,C,D} message to + the upstream device. + pattern: "^tx_int(a|b|c|d)$" + - description: + Combined interrupt signal raised when the controller has sent an + Assert_INT{A,B,C,D} message. See "^tx_int(a|b|c|d)$" for details. + const: legacy - description: Vendor-specific IRQ names. Consider using the generic names above for new bindings. From patchwork Tue Apr 30 12:01:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 1929447 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20201202 header.b=pJWb5KQF; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=147.75.80.249; helo=am.mirrors.kernel.org; envelope-from=devicetree+bounces-63975-incoming-dt=patchwork.ozlabs.org@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from am.mirrors.kernel.org (am.mirrors.kernel.org [147.75.80.249]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4VTJjD3FZYz20fY for ; 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a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1714478534; bh=FN05hy9jvB+E6GTH6BA3O2fKOPPC2nQRvjx6DsGtqeY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=pJWb5KQFQVbxuxIhHSuHiCd8i/KXkK06fvflLzA+2p1+o/7qpvTaoogdiazefxPpV 0AK4lMA3vNDC9Mt7cmW3Vq+gszJ0u4Sou+jRAVYeW7WMjz4le4L/s2iCzrxQ6oHphx hFj+42lvSLYkAsOKajB2c8hLwiMfjef6eusdM7GZEfsJS+TbDNAJsfZDZuxJjI6IZp uqKOLQKUgvHL+yBQgQTv/W1EFo0u+U312/IN/FoGsi44NXTRUe3It9d0XSGxg2Usia JN3nudu8KkSEpnabqcNhObPYuYz2/8LZrUvlmJOyftHXcP85g8uRlfb2K3ng1kAR4L Z+ImHV1aAqWhQ== From: Niklas Cassel Date: Tue, 30 Apr 2024 14:01:01 +0200 Subject: [PATCH v2 04/14] dt-bindings: PCI: rockchip-dw-pcie: Prepare for Endpoint mode support Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240430-rockchip-pcie-ep-v1-v2-4-a0f5ee2a77b6@kernel.org> References: <20240430-rockchip-pcie-ep-v1-v2-0-a0f5ee2a77b6@kernel.org> In-Reply-To: <20240430-rockchip-pcie-ep-v1-v2-0-a0f5ee2a77b6@kernel.org> To: Jingoo Han , Manivannan Sadhasivam , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Niklas Cassel , Kishon Vijay Abraham I , Arnd Bergmann , Damien Le Moal , Jon Lin , Shawn Lin , Simon Xue Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=8019; i=cassel@kernel.org; h=from:subject:message-id; bh=FN05hy9jvB+E6GTH6BA3O2fKOPPC2nQRvjx6DsGtqeY=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNIM7m44vtpKIPD/esaFfBnTbjuF7Du9IvNRyLGYBeXGV b3TlnRc7ChlYRDjYpAVU2Tx/eGyv7jbfcpxxTs2MHNYmUCGMHBxCsBE7oUwMpxle2t6e7Wq3Z6w o/rNj7XSrhdJBX+dpOFV6RLvxpTDepGR4YXC9HMn4nRMzdJ7Unfw9tvOFvyiWzwrz//ryz1ZDZx hDAA= X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA Refactor the rockchip-dw-pcie binding to move generic properties to a new rockchip-dw-pcie-common binding that can be shared by both RC and EP mode. No functional change intended. Signed-off-by: Niklas Cassel Reviewed-by: Rob Herring (Arm) --- .../bindings/pci/rockchip-dw-pcie-common.yaml | 111 +++++++++++++++++++++ .../devicetree/bindings/pci/rockchip-dw-pcie.yaml | 93 +---------------- 2 files changed, 114 insertions(+), 90 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml new file mode 100644 index 000000000000..60d190a77580 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml @@ -0,0 +1,111 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: DesignWare based PCIe RC/EP controller on Rockchip SoCs + +maintainers: + - Shawn Lin + - Simon Xue + - Heiko Stuebner + +description: |+ + Generic properties for the DesignWare based PCIe RC/EP controller on Rockchip + SoCs. + +properties: + clocks: + minItems: 5 + items: + - description: AHB clock for PCIe master + - description: AHB clock for PCIe slave + - description: AHB clock for PCIe dbi + - description: APB clock for PCIe + - description: Auxiliary clock for PCIe + - description: PIPE clock + - description: Reference clock for PCIe + + clock-names: + minItems: 5 + items: + - const: aclk_mst + - const: aclk_slv + - const: aclk_dbi + - const: pclk + - const: aux + - const: pipe + - const: ref + + interrupts: + items: + - description: + Combined system interrupt, which is used to signal the following + interrupts - phy_link_up, dll_link_up, link_req_rst_not, hp_pme, + hp, hp_msi, link_auto_bw, link_auto_bw_msi, bw_mgt, bw_mgt_msi, + edma_wr, edma_rd, dpa_sub_upd, rbar_update, link_eq_req, ep_elbi_app + - description: + Combined PM interrupt, which is used to signal the following + interrupts - linkst_in_l1sub, linkst_in_l1, linkst_in_l2, + linkst_in_l0s, linkst_out_l1sub, linkst_out_l1, linkst_out_l2, + linkst_out_l0s, pm_dstate_update + - description: + Combined message interrupt, which is used to signal the following + interrupts - ven_msg, unlock_msg, ltr_msg, cfg_pme, cfg_pme_msi, + pm_pme, pm_to_ack, pm_turnoff, obff_idle, obff_obff, obff_cpu_active + - description: + Combined legacy interrupt, which is used to signal the following + interrupts - inta, intb, intc, intd + - description: + Combined error interrupt, which is used to signal the following + interrupts - aer_rc_err, aer_rc_err_msi, rx_cpl_timeout, + tx_cpl_timeout, cor_err_sent, nf_err_sent, f_err_sent, cor_err_rx, + nf_err_rx, f_err_rx, radm_qoverflow + + interrupt-names: + items: + - const: sys + - const: pmc + - const: msg + - const: legacy + - const: err + + num-lanes: true + + phys: + maxItems: 1 + + phy-names: + const: pcie-phy + + power-domains: + maxItems: 1 + + resets: + minItems: 1 + maxItems: 2 + + reset-names: + oneOf: + - const: pipe + - items: + - const: pwr + - const: pipe + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - num-lanes + - phys + - phy-names + - power-domains + - resets + - reset-names + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml index 5f719218c472..550d8a684af3 100644 --- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: DesignWare based PCIe controller on Rockchip SoCs +title: DesignWare based PCIe Root Complex controller on Rockchip SoCs maintainers: - Shawn Lin @@ -12,12 +12,13 @@ maintainers: - Heiko Stuebner description: |+ - RK3568 SoC PCIe host controller is based on the Synopsys DesignWare + RK3568 SoC PCIe Root Complex controller is based on the Synopsys DesignWare PCIe IP and thus inherits all the common properties defined in snps,dw-pcie.yaml. allOf: - $ref: /schemas/pci/snps,dw-pcie.yaml# + - $ref: /schemas/pci/rockchip-dw-pcie-common.yaml# properties: compatible: @@ -40,61 +41,6 @@ properties: - const: apb - const: config - clocks: - minItems: 5 - items: - - description: AHB clock for PCIe master - - description: AHB clock for PCIe slave - - description: AHB clock for PCIe dbi - - description: APB clock for PCIe - - description: Auxiliary clock for PCIe - - description: PIPE clock - - description: Reference clock for PCIe - - clock-names: - minItems: 5 - items: - - const: aclk_mst - - const: aclk_slv - - const: aclk_dbi - - const: pclk - - const: aux - - const: pipe - - const: ref - - interrupts: - items: - - description: - Combined system interrupt, which is used to signal the following - interrupts - phy_link_up, dll_link_up, link_req_rst_not, hp_pme, - hp, hp_msi, link_auto_bw, link_auto_bw_msi, bw_mgt, bw_mgt_msi, - edma_wr, edma_rd, dpa_sub_upd, rbar_update, link_eq_req, ep_elbi_app - - description: - Combined PM interrupt, which is used to signal the following - interrupts - linkst_in_l1sub, linkst_in_l1, linkst_in_l2, - linkst_in_l0s, linkst_out_l1sub, linkst_out_l1, linkst_out_l2, - linkst_out_l0s, pm_dstate_update - - description: - Combined message interrupt, which is used to signal the following - interrupts - ven_msg, unlock_msg, ltr_msg, cfg_pme, cfg_pme_msi, - pm_pme, pm_to_ack, pm_turnoff, obff_idle, obff_obff, obff_cpu_active - - description: - Combined legacy interrupt, which is used to signal the following - interrupts - inta, intb, intc, intd - - description: - Combined error interrupt, which is used to signal the following - interrupts - aer_rc_err, aer_rc_err_msi, rx_cpl_timeout, - tx_cpl_timeout, cor_err_sent, nf_err_sent, f_err_sent, cor_err_rx, - nf_err_rx, f_err_rx, radm_qoverflow - - interrupt-names: - items: - - const: sys - - const: pmc - - const: msg - - const: legacy - - const: err - legacy-interrupt-controller: description: Interrupt controller node for handling legacy PCI interrupts. type: object @@ -119,47 +65,14 @@ properties: msi-map: true - num-lanes: true - - phys: - maxItems: 1 - - phy-names: - const: pcie-phy - - power-domains: - maxItems: 1 - ranges: minItems: 2 maxItems: 3 - resets: - minItems: 1 - maxItems: 2 - - reset-names: - oneOf: - - const: pipe - - items: - - const: pwr - - const: pipe - vpcie3v3-supply: true required: - - compatible - - reg - - reg-names - - clocks - - clock-names - msi-map - - num-lanes - - phys - - phy-names - - power-domains - - resets - - reset-names unevaluatedProperties: false From patchwork Tue Apr 30 12:01:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 1929449 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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bh=SXHxPE8zdJjZdXXAcX4rmqThuC0XgqJgg4dqgMQmx28=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=jcfFiRxp5K7LfbIMniYp++vMuQbnDaFXF0YR0h5thqTf9lraoZA1Y/Eyv0yNcpQ4B ZyjF0pW6E6uCtmuUmRSmUxQv4yhNP2VHl8MMsaIHzUhwruFscnYx5SIeRw2MHvUEdX iQE5rGBZR7fWh8eMo05TmvrEaAr+7zYDWF0pnKBFBQjTAel+GbLy2eDpKcCTDCAGez 6qhUIM2lgG0PsERpLlibUovx99bOmrmPv6wY2cp/MoCyw9UVzLIayHN3QzLUBf1ud8 GTs6/5es9P/Y3VL1ibb9DXXgjYVdqVTuEpxAFcgGQ+RwK/0NZ+E4OQuuqXN7pyTR6l jKcOcqEI2Rq2A== From: Niklas Cassel Date: Tue, 30 Apr 2024 14:01:02 +0200 Subject: [PATCH v2 05/14] dt-bindings: PCI: rockchip-dw-pcie: Fix description of legacy irq Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240430-rockchip-pcie-ep-v1-v2-5-a0f5ee2a77b6@kernel.org> References: <20240430-rockchip-pcie-ep-v1-v2-0-a0f5ee2a77b6@kernel.org> In-Reply-To: <20240430-rockchip-pcie-ep-v1-v2-0-a0f5ee2a77b6@kernel.org> To: Jingoo Han , Manivannan Sadhasivam , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Niklas Cassel , Kishon Vijay Abraham I , Arnd Bergmann , Damien Le Moal , Jon Lin , Shawn Lin , Simon Xue Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1900; i=cassel@kernel.org; h=from:subject:message-id; bh=SXHxPE8zdJjZdXXAcX4rmqThuC0XgqJgg4dqgMQmx28=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNIM7m441tzTf77xz82K1Zr9X+013sfoxBo0de7ceEPkz wSnu2fLOkpZGMS4GGTFFFl8f7jsL+52n3Jc8Y4NzBxWJpAhDFycAjARXmdGhiUMygeTJisba9x3 neDwdPECtyONrOd2Hrsja2hoU7VAxILhn33z8w+HQvlCzOxsZ5XzPqipX5bNc6h8TZrXHPv9GY6 CHAA= X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA The descriptions of the combined interrupt signals (level1) mention all the lower interrupt signals (level2) for each combined interrupt, regardless if the lower (level2) signal is RC or EP specific. E.g. the description of "Combined system interrupt" includes rbar_update, which is EP specific, and the description of "Combined message interrupt" includes obff_idle, obff_obff, obff_cpu_active, which are all EP specific. The only exception is the "Combined legacy interrupt", which for some reason does not provide an exhaustive list of the lower (level2) signals. Add the missing lower interrupt signals: tx_inta, tx_intb, tx_intc, and tx_intd for the "Combined legacy interrupt", as per the rk3568 and rk3588 Technical Reference Manuals, such that the descriptions of the combined interrupt signals are consistent. Signed-off-by: Niklas Cassel Reviewed-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml index 60d190a77580..ec5e6a3d048e 100644 --- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml @@ -56,7 +56,8 @@ properties: pm_pme, pm_to_ack, pm_turnoff, obff_idle, obff_obff, obff_cpu_active - description: Combined legacy interrupt, which is used to signal the following - interrupts - inta, intb, intc, intd + interrupts - inta, intb, intc, intd, tx_inta, tx_intb, tx_intc, + tx_intd - description: Combined error interrupt, which is used to signal the following interrupts - aer_rc_err, aer_rc_err_msi, rx_cpl_timeout, From patchwork Tue Apr 30 12:01:03 2024 Content-Type: text/plain; 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a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1714478542; bh=lzYyTB2OvdhD5k4zG4pbiEVMIEt2tbp4NUdYxqaO9x8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=Ec2nS7ABva/cSfofJiBnJSh0tLqY6xNang2HofW9orU8v9x//svVgR2kN7lPY/f5s zcLkdCR37VaVk3Jz1uR771McTUui7beQdRQ4zmxPKfNq5+xfClYngKAvmVec9RwgHx nV5sPWE9JSurmAE32vBpdvZP26/v2e+xxH27f6hIKtyIWjbL05GfYUsUcIMN1xn7vV lRO4uqTynYLRQW5bQrzxsqUy+LMKsUiQXM/FjYIL8jlnpPaH1vuG2c3/dhOnoSLJA7 YgVfNggpEIUXB1vWY6TbUie70SrUPdph8UKPWGZIAMneXBiFNY2xCQHne9LbQesHvT DT6dTQD2DVuDQ== From: Niklas Cassel Date: Tue, 30 Apr 2024 14:01:03 +0200 Subject: [PATCH v2 06/14] dt-bindings: rockchip: Add DesignWare based PCIe Endpoint controller Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240430-rockchip-pcie-ep-v1-v2-6-a0f5ee2a77b6@kernel.org> References: <20240430-rockchip-pcie-ep-v1-v2-0-a0f5ee2a77b6@kernel.org> In-Reply-To: <20240430-rockchip-pcie-ep-v1-v2-0-a0f5ee2a77b6@kernel.org> To: Jingoo Han , Manivannan Sadhasivam , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Niklas Cassel , Kishon Vijay Abraham I , Arnd Bergmann , Damien Le Moal , Jon Lin , Shawn Lin , Simon Xue Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=5484; i=cassel@kernel.org; h=from:subject:message-id; bh=lzYyTB2OvdhD5k4zG4pbiEVMIEt2tbp4NUdYxqaO9x8=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNIM7m4IbJ+tf/LKHblq80Mct4o0Zs1uy1TdvvmDUWBAw P6t1upMHaUsDGJcDLJiiiy+P1z2F3e7TzmueMcGZg4rE8gQBi5OAZjI8XaG//WXWhdLROk8nr1l g/vu2+/2Zh60OODUaVcsmNxn8rt8YhzD/1zXqhIlweTUxNvzfJzm2s6VEz596s1sHj0NQYU7Pmn 1vAA= X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA Document DT bindings for PCIe Endpoint controller found in Rockchip SoCs. Signed-off-by: Niklas Cassel Reviewed-by: Rob Herring (Arm) --- .../bindings/pci/rockchip-dw-pcie-common.yaml | 14 ++++ .../bindings/pci/rockchip-dw-pcie-ep.yaml | 95 ++++++++++++++++++++++ 2 files changed, 109 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml index ec5e6a3d048e..cc9adfc7611c 100644 --- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml @@ -39,6 +39,7 @@ properties: - const: ref interrupts: + minItems: 5 items: - description: Combined system interrupt, which is used to signal the following @@ -63,14 +64,27 @@ properties: interrupts - aer_rc_err, aer_rc_err_msi, rx_cpl_timeout, tx_cpl_timeout, cor_err_sent, nf_err_sent, f_err_sent, cor_err_rx, nf_err_rx, f_err_rx, radm_qoverflow + - description: + eDMA write channel 0 interrupt + - description: + eDMA write channel 1 interrupt + - description: + eDMA read channel 0 interrupt + - description: + eDMA read channel 1 interrupt interrupt-names: + minItems: 5 items: - const: sys - const: pmc - const: msg - const: legacy - const: err + - const: dma0 + - const: dma1 + - const: dma2 + - const: dma3 num-lanes: true diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-ep.yaml new file mode 100644 index 000000000000..e0c8668afc01 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-ep.yaml @@ -0,0 +1,95 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie-ep.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: DesignWare based PCIe Endpoint controller on Rockchip SoCs + +maintainers: + - Niklas Cassel + +description: |+ + RK3588 SoC PCIe Endpoint controller is based on the Synopsys DesignWare + PCIe IP and thus inherits all the common properties defined in + snps,dw-pcie-ep.yaml. + +allOf: + - $ref: /schemas/pci/snps,dw-pcie-ep.yaml# + - $ref: /schemas/pci/rockchip-dw-pcie-common.yaml# + +properties: + compatible: + enum: + - rockchip,rk3568-pcie-ep + - rockchip,rk3588-pcie-ep + + reg: + items: + - description: Data Bus Interface (DBI) registers + - description: Data Bus Interface (DBI) shadow registers + - description: Rockchip designed configuration registers + - description: Memory region used to map remote RC address space + - description: Address Translation Unit (ATU) registers + + reg-names: + items: + - const: dbi + - const: dbi2 + - const: apb + - const: addr_space + - const: atu + +required: + - interrupts + - interrupt-names + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + bus { + #address-cells = <2>; + #size-cells = <2>; + + pcie3x4_ep: pcie-ep@fe150000 { + compatible = "rockchip,rk3588-pcie-ep"; + clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, + <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, + <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "sys", "pmc", "msg", "legacy", "err", + "dma0", "dma1", "dma2", "dma3"; + max-link-speed = <3>; + num-lanes = <4>; + phys = <&pcie30phy>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + reg = <0xa 0x40000000 0x0 0x00100000>, + <0xa 0x40100000 0x0 0x00100000>, + <0x0 0xfe150000 0x0 0x00010000>, + <0x9 0x00000000 0x0 0x40000000>, + <0xa 0x40300000 0x0 0x00100000>; + reg-names = "dbi", "dbi2", "apb", "addr_space", "atu"; + resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; + reset-names = "pwr", "pipe"; + }; + }; +...