From patchwork Wed Apr 24 15:16:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 1927208 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20201202 header.b=eIShaqMp; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=147.75.80.249; helo=am.mirrors.kernel.org; envelope-from=devicetree+bounces-62346-incoming-dt=patchwork.ozlabs.org@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from am.mirrors.kernel.org (am.mirrors.kernel.org [147.75.80.249]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4VPjJT1Cncz1yP2 for ; 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arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713971803; cv=none; b=p1q/30pEGpQZR7Bq6zEvGSRiyB+QMo3YmZ6KO0EZqV0G/lrK3PGP/ZLBi/JukCPvY8CRj2J6cgjgPI0TkPq3W3gZIcJpM7YPRMgAZb3RZ4YqYrrObe8MPIgkcaRv3nyARHP+f4LGh5sALPMMscRbzvpE1fHXduMckfhe+3hKZJo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713971803; c=relaxed/simple; bh=Dz2zX6pvYQupG08wzkCHyigvD513tXaWstBbBs/KqqQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=s/9FJrP355BT2sUae4yrnHdu50xSfkPyyUUSkCqUIs6gnzY40vkX4HW6Y9yuBtmcAXXcHaq5nSRcJx/AEBLqzauJrPZlPiWu7RYHI7NPej5qk816ZlpY26lU4HZrGoFV2QbADD3+cIf1EMJqoWvKsif7mt9xNHbOusHcbuP5LPc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=eIShaqMp; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 65DB2C2BD10; Wed, 24 Apr 2024 15:16:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1713971803; bh=Dz2zX6pvYQupG08wzkCHyigvD513tXaWstBbBs/KqqQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=eIShaqMpHgxz5fHgGPYgEqGa2swx/yz3eQ5CYt3YtNbmk3Crdi1qOfhTjyKufIhzI mNF792Jlm5MBmm7o0d/rlvZvP6+65vCyKm0fAag+e3CuIE3fVlDUA6tC2Gw8bNxzG1 pD3iFBFnVXnvzBvF3aEA1akLsaCBP3+/RFN5JdlDmXugJCYpLADJeS6ZTYQHiBkMnw temPzfuPS5Qlmm3nT8JGtrTzqht8XmKTaSTCGkVuLztIo/9D/+uX85+O4Si0Aiu+jK jOGHJ3oARrnJvuZLgvEH4MjwTsINVL2MeyAB/ynei7w0J/wNe0P70ARrp4XvfvMUd8 mQZjouSlSdauA== From: Niklas Cassel Date: Wed, 24 Apr 2024 17:16:19 +0200 Subject: [PATCH 01/12] dt-bindings: PCI: snps,dw-pcie-ep: Add vendor specific reg-name Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240424-rockchip-pcie-ep-v1-v1-1-b1a02ddad650@kernel.org> References: <20240424-rockchip-pcie-ep-v1-v1-0-b1a02ddad650@kernel.org> In-Reply-To: <20240424-rockchip-pcie-ep-v1-v1-0-b1a02ddad650@kernel.org> To: Jingoo Han , Manivannan Sadhasivam , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Niklas Cassel , Kishon Vijay Abraham I , Arnd Bergmann , Damien Le Moal , Jon Lin , Shawn Lin , Simon Xue Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1246; i=cassel@kernel.org; h=from:subject:message-id; bh=Dz2zX6pvYQupG08wzkCHyigvD513tXaWstBbBs/KqqQ=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNI0lYJKTk/dfPLXWvWGRvZ6boVS0xKf9/nOP2pMF33Qa FGcqS7cUcrCIMbFICumyOL7w2V/cbf7lOOKd2xg5rAygQxh4OIUgInMEmBk+DP3RV3ibnGuFqX1 Rsfzdh8KUP5x+kPs4Z8n0i69TInJXcjI0KGwy6NyRn9Bmt3hi1N0lzqlNnjbH89eNmHWy+sTrE8 95gYA X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA Considering that some drivers (e.g. pcie-dw-rockchip.c) already use the reg-name "apb" for the device tree binding in Root Complex mode (snps,dw-pcie.yaml), it doesn't make sense that those drivers should use a different reg-name when running in Endpoint mode (snps,dw-pcie-ep.yaml). Therefore, since "apb" is already defined in snps,dw-pcie.yaml, add it also for snps,dw-pcie-ep.yaml. Signed-off-by: Niklas Cassel Reviewed-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml index bbdb01d22848..00dec01f1f73 100644 --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml @@ -100,7 +100,7 @@ properties: for new bindings. oneOf: - description: See native 'elbi/app' CSR region for details. - enum: [ link, appl ] + enum: [ apb, link, appl ] - description: See native 'atu' CSR region for details. enum: [ atu_dma ] allOf: From patchwork Wed Apr 24 15:16:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 1927209 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713971807; c=relaxed/simple; bh=RS5e+C8n99mUSp3drovm0VWPXXUTCxKx8PPtgdI2hJI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=bWRUElWtc5v9Np0uxO5S5ud36dcNVi/lh2Z9P/U7YOJWfwzkp9b6KuQJXRZq7kKFYfqPfwyvoS7oVQV1uCb0OczU1YBWcqAhLXokbS1iVxqeHZwlpHmVW44W7LRa8pJVa3ZH6efn0A838Pa/+a/0TyFiO4elNuoAbZHEiANerAc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=GxXeL0MY; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9AE17C32783; Wed, 24 Apr 2024 15:16:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1713971807; bh=RS5e+C8n99mUSp3drovm0VWPXXUTCxKx8PPtgdI2hJI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=GxXeL0MYUsc+BA+H9o4ID0yqOlTwHXserXcofLg02Zpe2DY0/cwiBhgQWLcnnjD63 QdYGqk4jUbezqGkpdXFRM20bqiLo2QWSi5BKDaNkkoGlfGPyjaFCG9Q8V9ZnOITjv8 VVQ0+eqaIQp/o9u2PSzJrVNv8W01FHvxEuRtRxIFgDl0Z5Cq7PEEIjcOC0/KeAK0fz ExfKIbhA0fqrnO/3uc/V7xARu83dpZu1efSgfEaSpy8b0Ks0BZviy7F8/p7y1rRvm1 MaRpPT/RZOWjAc6aos5tNdwRMdZTIJh1ki5QuDjCOrdxJEOv5jWWF5pR/3Xgjrum1b cYLZcxfHZcI8g== From: Niklas Cassel Date: Wed, 24 Apr 2024 17:16:20 +0200 Subject: [PATCH 02/12] dt-bindings: PCI: snps,dw-pcie-ep: Add vendor specific interrupt-names Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240424-rockchip-pcie-ep-v1-v1-2-b1a02ddad650@kernel.org> References: <20240424-rockchip-pcie-ep-v1-v1-0-b1a02ddad650@kernel.org> In-Reply-To: <20240424-rockchip-pcie-ep-v1-v1-0-b1a02ddad650@kernel.org> To: Jingoo Han , Manivannan Sadhasivam , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Niklas Cassel , Kishon Vijay Abraham I , Arnd Bergmann , Damien Le Moal , Jon Lin , Shawn Lin , Simon Xue Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1217; i=cassel@kernel.org; h=from:subject:message-id; bh=RS5e+C8n99mUSp3drovm0VWPXXUTCxKx8PPtgdI2hJI=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNI0lYJ857GzxhdJpmeJvTWOqijc7PRXKSJb5MLcMt3j/ sxzHn/sKGVhEONikBVTZPH94bK/uNt9ynHFOzYwc1iZQIYwcHEKwES0xBj+p0mVrTDr2GAwpaLs 0twac/UDiWIbMiJExJYdNewV1Ob5xciweEalc3PFl/LuDaw+t302y84XOLPcvERRxOboFK4vH+7 xAgA= X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA Considering that some drivers (e.g. pcie-dw-rockchip.c) already use the interrupt-names "sys", "pmc", "msg", "err" for the device tree binding in Root Complex mode (snps,dw-pcie.yaml), it doesn't make sense that those drivers should use different interrupt-names when running in Endpoint mode (snps,dw-pcie-ep.yaml). Therefore, since "sys", "pmc", "msg", "err" are already defined in snps,dw-pcie.yaml, add them also for snps,dw-pcie-ep.yaml. Signed-off-by: Niklas Cassel Reviewed-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml index 00dec01f1f73..f5f12cbc2cb3 100644 --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml @@ -156,7 +156,7 @@ properties: for new bindings. oneOf: - description: See native "app" IRQ for details - enum: [ intr ] + enum: [ intr, sys, pmc, msg, err ] max-functions: maximum: 32 From patchwork Wed Apr 24 15:16:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 1927213 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713971811; c=relaxed/simple; bh=h8lnjPbesIZKEXHuDY56KI4CbN9QDflC/gTeCl9JudA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=lKVv+YIMZdhsz62NKgblbjT9uminopzaZ92MDNvIdIemJP7QN9lP6J3Ba269sjMhru3xVOTmNfAF5EsLBVUwGGKBNUKCA7APVbh/IogoOIzf7OwHTa0DpD4eOFCJNwwqZwAxusG9X9Jjo1t9DXXTI2UES4p/afw1CXlFnFXHDd4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=XHA53oSZ; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id CE887C32781; Wed, 24 Apr 2024 15:16:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1713971811; bh=h8lnjPbesIZKEXHuDY56KI4CbN9QDflC/gTeCl9JudA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=XHA53oSZ7HyiUp4IAUWEw8wRCx+ZM0y3zs0Aq4CKgm+ETKtBdkuB2N7ce5+FAmY6J gM+qCM1ye1y1JHOr4sFciA73zR1xoqKVoud9jcIvlGcsAho+5Qx3oJYiuDSUT3dlnP cJTkdwmsX0sV6zYMsgoa+wTm+/r0ha6lbTwvVbG3JkMRBeZ9an+dqoVqLXeeI0LyDA CxtFUKXeEnlr8fG5yiWSy+9U4Skyb+CcVMpp4v17McnWzgioqPqiWimMWiYhvpOE+v XvhzeLEZqIihXRNbzU/6U7v0e6FOBpjPX6rQ1FBJpOFOk4PGHO9Fn6YCuZ4WELK93j JLDn4sotDNnEQ== From: Niklas Cassel Date: Wed, 24 Apr 2024 17:16:21 +0200 Subject: [PATCH 03/12] dt-bindings: PCI: snps,dw-pcie-ep: Add tx_int{a,b,c,d} legacy irqs Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240424-rockchip-pcie-ep-v1-v1-3-b1a02ddad650@kernel.org> References: <20240424-rockchip-pcie-ep-v1-v1-0-b1a02ddad650@kernel.org> In-Reply-To: <20240424-rockchip-pcie-ep-v1-v1-0-b1a02ddad650@kernel.org> To: Jingoo Han , Manivannan Sadhasivam , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Niklas Cassel , Kishon Vijay Abraham I , Arnd Bergmann , Damien Le Moal , Jon Lin , Shawn Lin , Simon Xue Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1622; i=cassel@kernel.org; h=from:subject:message-id; bh=h8lnjPbesIZKEXHuDY56KI4CbN9QDflC/gTeCl9JudA=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNI0lYIyuX1M4iyl5kbPlyyRFG6csmCyVPqcrEyVz0+KZ LeryZR1lLIwiHExyIopsvj+cNlf3O0+5bjiHRuYOaxMIEMYuDgFYCJKNxgZ3qyvzDBjrqlh2BRh p3hjh4Cy+mXbift6BFv3uiwqtDLYzfDPIOLpNPVvLR52NUKhFx8sPZygb52tt+LHI+dHjMLNC5K 5AA== X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA The DWC core has four interrupt signals: tx_inta, tx_intb, tx_intc, tx_intd that are triggered when the PCIe controller (when running in Endpoint mode) has sent an Assert_INTA Message to the upstream device. Some DWC controllers have these interrupt in a combined interrupt signal. Add the description of these interrupts to the device tree binding. Signed-off-by: Niklas Cassel Reviewed-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml index f5f12cbc2cb3..f474b9e3fc7e 100644 --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml @@ -151,6 +151,15 @@ properties: Application-specific IRQ raised depending on the vendor-specific events basis. const: app + - description: + Interrupts triggered when the controller itself (in Endpoint mode) + has sent an Assert_INT{A,B,C,D}/Desassert_INT{A,B,C,D} message to + the upstream device. + pattern: "^tx_int(a|b|c|d)$" + - description: + Combined interrupt signal raised when the controller has sent an + Assert_INT{A,B,C,D} message. See "^tx_int(a|b|c|d)$" for details. + const: legacy - description: Vendor-specific IRQ names. Consider using the generic names above for new bindings. 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a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1713971815; bh=W5lkVQPb+eICdXIRorh9nge2BdMRIRVwedcZfqMZ7t0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=SqTO6HcDCupRkVmfvHYj/2vZpFJu0ljqCXrJLlwjwiCu4cYOf/wNcaMKpr2WgqEtS BWf5xc26z6yodbg7kg1xVn6wP6wW/LelNv3sNNbcqNUWmfxTC+ofawEHYx2HYQOxEq LGP/DSdIxZT8wJPAmIbFmTHSvxHVw2o1JrOYcaLJ5O4Bq0uI7YC9vVrEvo9I+go9aw jqhyyIHfcYDsptAdswYE8Wwe/cYo12QJN/sFzOnLdlrjeszQEElG9vnUFpYibzize6 hTJPVYxArOLBg9n1jvL7wVJPxarHmb2yESNqx+PumhrNl2RZrfHotp3ly6RF4ZJpIF nxl4goQv2Xzcg== From: Niklas Cassel Date: Wed, 24 Apr 2024 17:16:22 +0200 Subject: [PATCH 04/12] dt-bindings: rockchip: Add DesignWare based PCIe Endpoint controller Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240424-rockchip-pcie-ep-v1-v1-4-b1a02ddad650@kernel.org> References: <20240424-rockchip-pcie-ep-v1-v1-0-b1a02ddad650@kernel.org> In-Reply-To: <20240424-rockchip-pcie-ep-v1-v1-0-b1a02ddad650@kernel.org> To: Jingoo Han , Manivannan Sadhasivam , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Niklas Cassel , Kishon Vijay Abraham I , Arnd Bergmann , Damien Le Moal , Jon Lin , Shawn Lin , Simon Xue Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=6908; i=cassel@kernel.org; h=from:subject:message-id; bh=W5lkVQPb+eICdXIRorh9nge2BdMRIRVwedcZfqMZ7t0=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNI0lYI+zc9b3KNhlaXB/Ybl3r9nTvo5Wye9iip5OoNPT PiR4S/tjlIWBjEuBlkxRRbfHy77i7vdpxxXvGMDM4eVCWQIAxenAExkyl9GhofqiYqBzuqC97Yd niH/9f6nZI/PNgdaqp5wOLy+3tmTt4rhf1zJUq4js57e+9UvKbJ3/rmzM9cYrvYMUU69c0R4le2 dSUwA X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA Document DT bindings for PCIe Endpoint controller found in Rockchip SoCs. Signed-off-by: Niklas Cassel --- .../bindings/pci/rockchip-dw-pcie-ep.yaml | 192 +++++++++++++++++++++ 1 file changed, 192 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-ep.yaml new file mode 100644 index 000000000000..57a6c542058f --- /dev/null +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-ep.yaml @@ -0,0 +1,192 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie-ep.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: DesignWare based PCIe Endpoint controller on Rockchip SoCs + +maintainers: + - Niklas Cassel + +description: |+ + RK3588 SoC PCIe Endpoint controller is based on the Synopsys DesignWare + PCIe IP and thus inherits all the common properties defined in + snps,dw-pcie-ep.yaml. + +allOf: + - $ref: /schemas/pci/snps,dw-pcie-ep.yaml# + +properties: + compatible: + items: + - const: rockchip,rk3588-pcie-ep + + reg: + items: + - description: Data Bus Interface (DBI) registers + - description: Data Bus Interface (DBI) shadow registers + - description: Rockchip designed configuration registers + - description: Memory region used to map remote RC address space + - description: Address Translation Unit (ATU) registers + + reg-names: + items: + - const: dbi + - const: dbi2 + - const: apb + - const: addr_space + - const: atu + + clocks: + minItems: 6 + items: + - description: AHB clock for PCIe master + - description: AHB clock for PCIe slave + - description: AHB clock for PCIe dbi + - description: APB clock for PCIe + - description: Auxiliary clock for PCIe + - description: PIPE clock + - description: Reference clock for PCIe + + clock-names: + minItems: 6 + items: + - const: aclk_mst + - const: aclk_slv + - const: aclk_dbi + - const: pclk + - const: aux + - const: pipe + - const: ref + + interrupts: + items: + - description: + Combined system interrupt, which is used to signal the following + interrupts - phy_link_up, dll_link_up, link_req_rst_not, hp_pme, + hp, hp_msi, link_auto_bw, link_auto_bw_msi, bw_mgt, bw_mgt_msi, + edma_wr, edma_rd, dpa_sub_upd, rbar_update, link_eq_req, ep_elbi_app + - description: + Combined PM interrupt, which is used to signal the following + interrupts - linkst_in_l1sub, linkst_in_l1, linkst_in_l2, + linkst_in_l0s, linkst_out_l1sub, linkst_out_l1, linkst_out_l2, + linkst_out_l0s, pm_dstate_update + - description: + Combined message interrupt, which is used to signal the following + interrupts - ven_msg, unlock_msg, ltr_msg, cfg_pme, cfg_pme_msi, + pm_pme, pm_to_ack, pm_turnoff, obff_idle, obff_obff, obff_cpu_active + - description: + Combined legacy interrupt, which is used to signal the following + interrupts - tx_inta, tx_intb, tx_intc, tx_intd + - description: + Combined error interrupt, which is used to signal the following + interrupts - aer_rc_err, aer_rc_err_msi, rx_cpl_timeout, + tx_cpl_timeout, cor_err_sent, nf_err_sent, f_err_sent, cor_err_rx, + nf_err_rx, f_err_rx, radm_qoverflow + - description: + eDMA write channel 0 interrupt + - description: + eDMA write channel 1 interrupt + - description: + eDMA read channel 0 interrupt + - description: + eDMA read channel 1 interrupt + + interrupt-names: + items: + - const: sys + - const: pmc + - const: msg + - const: legacy + - const: err + - const: dma0 + - const: dma1 + - const: dma2 + - const: dma3 + + num-lanes: true + + phys: + maxItems: 1 + + phy-names: + const: pcie-phy + + power-domains: + maxItems: 1 + + resets: + maxItems: 2 + + reset-names: + items: + - const: pwr + - const: pipe + + vpcie3v3-supply: true + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - interrupts + - interrupt-names + - num-lanes + - phys + - phy-names + - power-domains + - resets + - reset-names + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + bus { + #address-cells = <2>; + #size-cells = <2>; + + pcie3x4_ep: pcie-ep@fe150000 { + compatible = "rockchip,rk3588-pcie-ep"; + clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, + <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, + <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "sys", "pmc", "msg", "legacy", "err", + "dma0", "dma1", "dma2", "dma3"; + max-link-speed = <3>; + num-lanes = <4>; + phys = <&pcie30phy>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + reg = <0xa 0x40000000 0x0 0x00100000>, + <0xa 0x40100000 0x0 0x00100000>, + <0x0 0xfe150000 0x0 0x00010000>, + <0x9 0x00000000 0x0 0x40000000>, + <0xa 0x40300000 0x0 0x00100000>; + reg-names = "dbi", "dbi2", "apb", "addr_space", "atu"; + resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; + reset-names = "pwr", "pipe"; + }; + }; +...