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Mon, 22 Apr 2024 03:05:16 -0700 (PDT) Received: from free.home ([2804:7f1:218b:5e2:c43b:e0c4:71a:241b]) by smtp.gmail.com with ESMTPSA id lb3-20020a056a004f0300b006e4432027d1sm7707360pfb.142.2024.04.22.03.05.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Apr 2024 03:05:15 -0700 (PDT) Received: from livre (livre.home [172.31.160.2]) by free.home (8.15.2/8.15.2) with ESMTPS id 43MA52Rp020704 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NOT); Mon, 22 Apr 2024 07:05:02 -0300 From: Alexandre Oliva To: Richard Biener Cc: GCC Patches , Rainer Orth , Mike Stump , David Edelsohn , Segher Boessenkool , Kewen Lin Subject: [PATCH] decay vect tests from run to link for pr95401 Organization: Free thinker, does not speak for AdaCore References: Date: Mon, 22 Apr 2024 07:05:02 -0300 In-Reply-To: (Richard Biener's message of "Thu, 11 Mar 2021 10:48:09 +0100") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/27.1 (gnu/linux) MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_NUMSUBJECT, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, WEIRD_QUOTING autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Ping?-ish for the full version of the RFC posted at https://gcc.gnu.org/pipermail/gcc-patches/2021-March/566588.html On Mar 11, 2021, Richard Biener wrote: > On Thu, Mar 11, 2021 at 9:03 AM Alexandre Oliva wrote: >> So I'm leaning towards this proposed change, just extended to other >> platforms that also decay from run to compile rather than link, and thus >> run into this problem in g++.dg/vect/pr95401.cc. Would this be >> acceptable? > I think that's OK. It's probably difficult to make the test UNSUPPORTED > when dg-additional-sources is discovered with a dg-do compile test? Thanks, here's a completed version. When vect.exp finds our configuration disables altivec by default, it disables the execution of vectorization tests, assuming the test hardware doesn't support it. Tests become just compile tests, but compile tests won't work correctly when additional sources are named, e.g. pr95401.cc, because GCC refuses to compile multiple files into the same asm output. With this patch, the default for when execution is not possible becomes link. Regstrapped on x86_64-linux-gnu and ppc64el-linux-gnu. Also tested with gcc-13 on ppc64-vx7r2 and ppc-vx7r2. Ok to install? for gcc/testsuite/ChangeLog * lib/target-supports.exp (check_vect_support_and_set_flags): Decay to link rather than compile. --- gcc/testsuite/lib/target-supports.exp | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 3a5713d98691f..54a55585371b0 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -11625,7 +11625,7 @@ proc check_vect_support_and_set_flags { } { if [check_750cl_hw_available] { set dg-do-what-default run } else { - set dg-do-what-default compile + set dg-do-what-default link } } elseif [istarget powerpc*-*-*] { # Skip targets not supporting -maltivec. @@ -11655,14 +11655,14 @@ proc check_vect_support_and_set_flags { } { # some other cpu type specified above. set DEFAULT_VECTCFLAGS [linsert $DEFAULT_VECTCFLAGS 0 "-mcpu=970"] } - set dg-do-what-default compile + set dg-do-what-default link } } elseif { [istarget i?86-*-*] || [istarget x86_64-*-*] } { lappend DEFAULT_VECTCFLAGS "-msse2" if { [check_effective_target_sse2_runtime] } { set dg-do-what-default run } else { - set dg-do-what-default compile + set dg-do-what-default link } } elseif { [istarget mips*-*-*] && [check_effective_target_nomips16] } { @@ -11681,7 +11681,7 @@ proc check_vect_support_and_set_flags { } { if [check_effective_target_ultrasparc_hw] { set dg-do-what-default run } else { - set dg-do-what-default compile + set dg-do-what-default link } } elseif [istarget alpha*-*-*] { # Alpha's vectorization capabilities are extremely limited. @@ -11694,7 +11694,7 @@ proc check_vect_support_and_set_flags { } { if [check_alpha_max_hw_available] { set dg-do-what-default run } else { - set dg-do-what-default compile + set dg-do-what-default link } } elseif [istarget ia64-*-*] { set dg-do-what-default run @@ -11707,7 +11707,7 @@ proc check_vect_support_and_set_flags { } { if [is-effective-target arm_neon_hw] { set dg-do-what-default run } else { - set dg-do-what-default compile + set dg-do-what-default link } } elseif [istarget aarch64*-*-*] { set dg-do-what-default run @@ -11731,7 +11731,7 @@ proc check_vect_support_and_set_flags { } { set dg-do-what-default run } else { lappend DEFAULT_VECTCFLAGS "-march=z14" "-mzarch" - set dg-do-what-default compile + set dg-do-what-default link } } elseif [istarget amdgcn-*-*] { set dg-do-what-default run @@ -11742,7 +11742,7 @@ proc check_vect_support_and_set_flags { } { foreach item [add_options_for_riscv_v ""] { lappend DEFAULT_VECTCFLAGS $item } - set dg-do-what-default compile + set dg-do-what-default link } } elseif [istarget loongarch*-*-*] { # Set the default vectorization option to "-mlsx" due to the problem @@ -11751,7 +11751,7 @@ proc check_vect_support_and_set_flags { } { if [check_effective_target_loongarch_sx_hw] { set dg-do-what-default run } else { - set dg-do-what-default compile + set dg-do-what-default link } } else { return 0