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18 Apr 2024 05:58:48 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 18 Apr 2024 05:58:29 -0700 Received: from CHE-LT-I17164LX.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Thu, 18 Apr 2024 05:58:21 -0700 From: Parthiban Veerasooran To: , , , , , , , , , , , , , , , , , , , CC: , , , , , , Parthiban Veerasooran Subject: [PATCH net-next v4 12/12] dt-bindings: net: add Microchip's LAN865X 10BASE-T1S MACPHY Date: Thu, 18 Apr 2024 18:26:48 +0530 Message-ID: <20240418125648.372526-13-Parthiban.Veerasooran@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240418125648.372526-1-Parthiban.Veerasooran@microchip.com> References: <20240418125648.372526-1-Parthiban.Veerasooran@microchip.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The LAN8650/1 combines a Media Access Controller (MAC) and an Ethernet PHY to enable 10BASE-T1S networks. The Ethernet Media Access Controller (MAC) module implements a 10 Mbps half duplex Ethernet MAC, compatible with the IEEE 802.3 standard and a 10BASE-T1S physical layer transceiver integrated into the LAN8650/1. The communication between the Host and the MAC-PHY is specified in the OPEN Alliance 10BASE-T1x MACPHY Serial Interface (TC6). Signed-off-by: Parthiban Veerasooran Reviewed-by: Conor Dooley --- .../bindings/net/microchip,lan865x.yaml | 80 +++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 81 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/microchip,lan865x.yaml diff --git a/Documentation/devicetree/bindings/net/microchip,lan865x.yaml b/Documentation/devicetree/bindings/net/microchip,lan865x.yaml new file mode 100644 index 000000000000..4fdec0ba3532 --- /dev/null +++ b/Documentation/devicetree/bindings/net/microchip,lan865x.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/microchip,lan865x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip LAN8650/1 10BASE-T1S MACPHY Ethernet Controllers + +maintainers: + - Parthiban Veerasooran + +description: + The LAN8650/1 combines a Media Access Controller (MAC) and an Ethernet + PHY to enable 10BASE‑T1S networks. The Ethernet Media Access Controller + (MAC) module implements a 10 Mbps half duplex Ethernet MAC, compatible + with the IEEE 802.3 standard and a 10BASE-T1S physical layer transceiver + integrated into the LAN8650/1. The communication between the Host and + the MAC-PHY is specified in the OPEN Alliance 10BASE-T1x MACPHY Serial + Interface (TC6). + +allOf: + - $ref: ethernet-controller.yaml# + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + oneOf: + - const: microchip,lan8650 + - items: + - const: microchip,lan8651 + - const: microchip,lan8650 + + reg: + maxItems: 1 + + interrupts: + description: + Interrupt from MAC-PHY asserted in the event of Receive Chunks + Available, Transmit Chunk Credits Available and Extended Status + Event. + maxItems: 1 + + spi-max-frequency: + minimum: 15000000 + maximum: 25000000 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +required: + - compatible + - reg + - interrupts + - spi-max-frequency + +unevaluatedProperties: false + +examples: + - | + #include + #include + + spi { + #address-cells = <1>; + #size-cells = <0>; + + ethernet@0 { + compatible = "microchip,lan8651", "microchip,lan8650"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <ð0_pins>; + interrupt-parent = <&gpio>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; + local-mac-address = [04 05 06 01 02 03]; + spi-max-frequency = <15000000>; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index f41b7f2257d2..2172431a1935 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14378,6 +14378,7 @@ MICROCHIP LAN8650/1 10BASE-T1S MACPHY ETHERNET DRIVER M: Parthiban Veerasooran L: netdev@vger.kernel.org S: Maintained +F: Documentation/devicetree/bindings/net/microchip,lan865x.yaml F: drivers/net/ethernet/microchip/lan865x/lan865x.c MICROCHIP LAN87xx/LAN937x T1 PHY DRIVER From patchwork Sun Apr 28 21:16:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Ram=C3=B3n_Nordin_Rodriguez?= X-Patchwork-Id: 1928699 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; 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[188.149.135.220]) by smtp.gmail.com with ESMTPSA id g28-20020a0565123b9c00b00518be964835sm3873408lfv.53.2024.04.28.14.16.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Apr 2024 14:16:33 -0700 (PDT) Date: Sun, 28 Apr 2024 23:16:32 +0200 From: =?iso-8859-1?q?Ram=F3n?= Nordin Rodriguez To: Parthiban Veerasooran Cc: davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, horms@kernel.org, saeedm@nvidia.com, anthony.l.nguyen@intel.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, andrew@lunn.ch, corbet@lwn.net, linux-doc@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, devicetree@vger.kernel.org, horatiu.vultur@microchip.com, ruanjinjie@huawei.com, steen.hegelund@microchip.com, vladimir.oltean@nxp.com, UNGLinuxDriver@microchip.com, Thorsten.Kummermehr@microchip.com, Pier.Beruto@onsemi.com, Selvamani.Rajagopal@onsemi.com, Nicolas.Ferre@microchip.com, benjamin.bigler@bernformulastudent.ch Subject: [PATCH net-next v4 13/12] net: lan865x: optional hardware reset Message-ID: References: <20240418125648.372526-1-Parthiban.Veerasooran@microchip.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240418125648.372526-1-Parthiban.Veerasooran@microchip.com> From c65e42982684d5fd8b2294eb6acf755aa0fcab83 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ram=C3=B3n=20Nordin=20Rodriguez?= Date: Sun, 28 Apr 2024 22:25:12 +0200 Subject: [PATCH net-next v4 13/12] net: lan865x: optional hardware reset MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This commit optionally enables a hardware reset of the lan8650/1 mac-phy. These chips have a software reset that is discourage from use in the manual since it only resets the internal phy. Signed-off-by: Ramón Nordin Rodriguez --- .../bindings/net/microchip,lan865x.yaml | 4 +++ .../net/ethernet/microchip/lan865x/lan865x.c | 28 +++++++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/Documentation/devicetree/bindings/net/microchip,lan865x.yaml b/Documentation/devicetree/bindings/net/microchip,lan865x.yaml index 4fdec0ba3532..0f11f431df06 100644 --- a/Documentation/devicetree/bindings/net/microchip,lan865x.yaml +++ b/Documentation/devicetree/bindings/net/microchip,lan865x.yaml @@ -44,6 +44,9 @@ properties: minimum: 15000000 maximum: 25000000 + reset-gpios: + maxItems: 1 + "#address-cells": const: 1 @@ -76,5 +79,6 @@ examples: interrupts = <6 IRQ_TYPE_EDGE_FALLING>; local-mac-address = [04 05 06 01 02 03]; spi-max-frequency = <15000000>; + reset-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; }; }; diff --git a/drivers/net/ethernet/microchip/lan865x/lan865x.c b/drivers/net/ethernet/microchip/lan865x/lan865x.c index 9abefa8b9d9f..bed9033574b2 100644 --- a/drivers/net/ethernet/microchip/lan865x/lan865x.c +++ b/drivers/net/ethernet/microchip/lan865x/lan865x.c @@ -9,6 +9,7 @@ #include #include #include +#include #define DRV_NAME "lan865x" @@ -33,6 +34,7 @@ struct lan865x_priv { struct work_struct multicast_work; + struct gpio_desc *reset_gpio; struct net_device *netdev; struct spi_device *spi; struct oa_tc6 *tc6; @@ -283,6 +285,24 @@ static int lan865x_set_zarfe(struct lan865x_priv *priv) return oa_tc6_write_register(priv->tc6, OA_TC6_REG_CONFIG0, regval); } +static int lan865x_probe_reset_gpio(struct lan865x_priv *priv) +{ + priv->reset_gpio = devm_gpiod_get_optional(&priv->spi->dev, "reset", + GPIOD_OUT_HIGH); + if (IS_ERR(priv->reset_gpio)) + return PTR_ERR(priv->reset_gpio); + + return 0; +} + +static void lan865x_hw_reset(struct lan865x_priv *priv) +{ + gpiod_set_value_cansleep(priv->reset_gpio, 1); + // section 9.6.3 RESET_N Timing specifies a minimum hold of 5us + usleep_range(5, 10); + gpiod_set_value_cansleep(priv->reset_gpio, 0); +} + static int lan865x_probe(struct spi_device *spi) { struct net_device *netdev; @@ -297,6 +317,14 @@ static int lan865x_probe(struct spi_device *spi) priv->netdev = netdev; priv->spi = spi; spi_set_drvdata(spi, priv); + if (lan865x_probe_reset_gpio(priv)) { + dev_err(&spi->dev, "failed to probe reset pin"); + ret = -ENODEV; + goto free_netdev; + } + + if (priv->reset_gpio) + lan865x_hw_reset(priv); INIT_WORK(&priv->multicast_work, lan865x_multicast_work_handler); priv->tc6 = oa_tc6_init(spi, netdev);