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(localhost [IPv6:::1]) by gnu-cfl-3.localdomain (Postfix) with ESMTP id E3D097403D1; Fri, 12 Apr 2024 15:42:12 -0700 (PDT) From: "H.J. Lu" To: gcc-patches@gcc.gnu.org Cc: hongtao.liu@intel.com Subject: [PATCH] x86: Allow TImode offsettable memory only with 8-bit constant Date: Fri, 12 Apr 2024 15:42:12 -0700 Message-ID: <20240412224212.940737-1-hjl.tools@gmail.com> X-Mailer: git-send-email 2.44.0 MIME-Version: 1.0 X-Spam-Status: No, score=-3020.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_SBL_CSS, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org The x86 instruction size limit is 15 bytes. If a NDD instruction has a segment prefix byte, a 4-byte opcode prefix, a MODRM byte, a SIB byte, a 4-byte displacement and a 4-byte immediate, adding an address size prefix will exceed the size limit. Change TImode ADD, AND, OR and XOR to allow offsettable memory only with 8-bit signed integer constant, which is encoded with a 1-byte immediate, if the address size prefix is used. gcc/ PR target/114696 * config/i386/i386.md (isa): Add apx_ndd_64. (enabled): Likewise. (*add3_doubleword): Change rjO to r,ro,jO with 8-bit signed integer constant and enable jO only for apx_ndd_64. (*add3_doubleword_cc_overflow_1): Likewise. (*and3_doubleword): Likewise. (*3_doubleword): Likewise. gcc/testsuite/ PR target/114696 * gcc.target/i386/apx-ndd-x32-2a.c: New test. * gcc.target/i386/apx-ndd-x32-2b.c: Likewise. * gcc.target/i386/apx-ndd-x32-2c.c: Likewise. * gcc.target/i386/apx-ndd-x32-2d.c: Likewise. --- gcc/config/i386/i386.md | 36 ++++++++++--------- .../gcc.target/i386/apx-ndd-x32-2a.c | 13 +++++++ .../gcc.target/i386/apx-ndd-x32-2b.c | 6 ++++ .../gcc.target/i386/apx-ndd-x32-2c.c | 6 ++++ .../gcc.target/i386/apx-ndd-x32-2d.c | 6 ++++ 5 files changed, 50 insertions(+), 17 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/apx-ndd-x32-2a.c create mode 100644 gcc/testsuite/gcc.target/i386/apx-ndd-x32-2b.c create mode 100644 gcc/testsuite/gcc.target/i386/apx-ndd-x32-2c.c create mode 100644 gcc/testsuite/gcc.target/i386/apx-ndd-x32-2d.c diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index d4ce3809e6d..adab1ef9e04 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -568,7 +568,7 @@ (define_attr "unit" "integer,i387,sse,mmx,unknown" ;; Used to control the "enabled" attribute on a per-instruction basis. (define_attr "isa" "base,x64,nox64,x64_sse2,x64_sse4,x64_sse4_noavx, - x64_avx,x64_avx512bw,x64_avx512dq,apx_ndd, + x64_avx,x64_avx512bw,x64_avx512dq,apx_ndd,apx_ndd_64, sse_noavx,sse2,sse2_noavx,sse3,sse3_noavx,sse4,sse4_noavx, avx,noavx,avx2,noavx2,bmi,bmi2,fma4,fma,avx512f,avx512f_512, noavx512f,avx512bw,avx512bw_512,noavx512bw,avx512dq, @@ -968,6 +968,8 @@ (define_attr "enabled" "" (symbol_ref "TARGET_VPCLMULQDQ && TARGET_AVX512VL") (eq_attr "isa" "apx_ndd") (symbol_ref "TARGET_APX_NDD") + (eq_attr "isa" "apx_ndd_64") + (symbol_ref "TARGET_APX_NDD && Pmode == DImode") (eq_attr "isa" "vaes_avx512vl") (symbol_ref "TARGET_VAES && TARGET_AVX512VL") @@ -6302,10 +6304,10 @@ (define_expand "add3" }) (define_insn_and_split "*add3_doubleword" - [(set (match_operand: 0 "nonimmediate_operand" "=ro,r,&r,&r,&r") + [(set (match_operand: 0 "nonimmediate_operand" "=ro,r,&r,&r,&r,&r,&r") (plus: - (match_operand: 1 "nonimmediate_operand" "%0,0,ro,rjO,r") - (match_operand: 2 "x86_64_hilo_general_operand" "r,o,r,,r"))) + (match_operand: 1 "nonimmediate_operand" "%0,0,ro,r,ro,jO,r") + (match_operand: 2 "x86_64_hilo_general_operand" "r,o,r,,K,,r"))) (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (PLUS, mode, operands, TARGET_APX_NDD)" "#" @@ -6344,7 +6346,7 @@ (define_insn_and_split "*add3_doubleword" DONE; } } -[(set_attr "isa" "*,*,apx_ndd,apx_ndd,apx_ndd")]) +[(set_attr "isa" "*,*,apx_ndd,apx_ndd,apx_ndd,apx_ndd_64,apx_ndd")]) (define_insn_and_split "*add3_doubleword_zext" [(set (match_operand: 0 "nonimmediate_operand" "=r,o,&r,&r") @@ -9515,10 +9517,10 @@ (define_insn_and_split "*add3_doubleword_cc_overflow_1" [(set (reg:CCC FLAGS_REG) (compare:CCC (plus: - (match_operand: 1 "nonimmediate_operand" "%0,0,ro,rjO,r") - (match_operand: 2 "x86_64_hilo_general_operand" "r,o,r,,o")) + (match_operand: 1 "nonimmediate_operand" "%0,0,ro,r,ro,jO,r") + (match_operand: 2 "x86_64_hilo_general_operand" "r,o,r,,K,,o")) (match_dup 1))) - (set (match_operand: 0 "nonimmediate_operand" "=ro,r,&r,&r,&r") + (set (match_operand: 0 "nonimmediate_operand" "=ro,r,&r,&r,&r,&r,&r") (plus: (match_dup 1) (match_dup 2)))] "ix86_binary_operator_ok (PLUS, mode, operands, TARGET_APX_NDD)" "#" @@ -9560,7 +9562,7 @@ (define_insn_and_split "*add3_doubleword_cc_overflow_1" else operands[6] = gen_rtx_ZERO_EXTEND (mode, operands[5]); } -[(set_attr "isa" "*,*,apx_ndd,apx_ndd,apx_ndd")]) +[(set_attr "isa" "*,*,apx_ndd,apx_ndd,apx_ndd,apx_ndd_64,apx_ndd")]) ;; x == 0 with zero flag test can be done also as x < 1U with carry flag ;; test, where the latter is preferrable if we have some carry consuming @@ -11704,10 +11706,10 @@ (define_expand "and3" }) (define_insn_and_split "*and3_doubleword" - [(set (match_operand: 0 "nonimmediate_operand" "=ro,r,&r,&r,&r") + [(set (match_operand: 0 "nonimmediate_operand" "=ro,r,&r,&r,&r,&r,&r") (and: - (match_operand: 1 "nonimmediate_operand" "%0,0,ro,rjO,r") - (match_operand: 2 "x86_64_hilo_general_operand" "r,o,r,,o"))) + (match_operand: 1 "nonimmediate_operand" "%0,0,ro,r,ro,jO,r") + (match_operand: 2 "x86_64_hilo_general_operand" "r,o,r,,K,,o"))) (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (AND, mode, operands, TARGET_APX_NDD)" "#" @@ -11744,7 +11746,7 @@ (define_insn_and_split "*and3_doubleword" DONE; } -[(set_attr "isa" "*,*,apx_ndd,apx_ndd,apx_ndd")]) +[(set_attr "isa" "*,*,apx_ndd,apx_ndd,apx_ndd,apx_ndd_64,apx_ndd")]) (define_insn "*anddi_1" [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,rm,r,r,r,r,r,?k") @@ -12694,10 +12696,10 @@ (define_expand "3" }) (define_insn_and_split "*3_doubleword" - [(set (match_operand: 0 "nonimmediate_operand" "=ro,r,&r,&r,&r") + [(set (match_operand: 0 "nonimmediate_operand" "=ro,r,&r,&r,&r,&r,&r") (any_or: - (match_operand: 1 "nonimmediate_operand" "%0,0,ro,rjO,r") - (match_operand: 2 "x86_64_hilo_general_operand" "r,o,r,,o"))) + (match_operand: 1 "nonimmediate_operand" "%0,0,ro,r,ro,jO,r") + (match_operand: 2 "x86_64_hilo_general_operand" "r,o,r,,K,,o"))) (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (, mode, operands, TARGET_APX_NDD)" "#" @@ -12750,7 +12752,7 @@ (define_insn_and_split "*3_doubleword" DONE; } -[(set_attr "isa" "*,*,apx_ndd,apx_ndd,apx_ndd")]) +[(set_attr "isa" "*,*,apx_ndd,apx_ndd,apx_ndd,apx_ndd_64,apx_ndd")]) (define_insn "*_1" [(set (match_operand:SWI248 0 "nonimmediate_operand" "=rm,r,r,r,r,?k") diff --git a/gcc/testsuite/gcc.target/i386/apx-ndd-x32-2a.c b/gcc/testsuite/gcc.target/i386/apx-ndd-x32-2a.c new file mode 100644 index 00000000000..6f7edb224a3 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/apx-ndd-x32-2a.c @@ -0,0 +1,13 @@ +/* PR target/114696 */ +/* { dg-do assemble { target { apxf && { ! ia32 } } } } */ +/* { dg-require-effective-target maybe_x32 } */ +/* { dg-options "-mapxf -O0 -mx32" } */ + +_Thread_local unsigned _BitInt(65) a; +_BitInt(129) b; + +void +foo (void) +{ + a += b; +} diff --git a/gcc/testsuite/gcc.target/i386/apx-ndd-x32-2b.c b/gcc/testsuite/gcc.target/i386/apx-ndd-x32-2b.c new file mode 100644 index 00000000000..8f53d5c10c9 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/apx-ndd-x32-2b.c @@ -0,0 +1,6 @@ +/* PR target/114696 */ +/* { dg-do assemble { target { apxf && { ! ia32 } } } } */ +/* { dg-require-effective-target maybe_x32 } */ +/* { dg-options "-mapxf -O2 -mx32" } */ + +#include "apx-ndd-x32-2a.c" diff --git a/gcc/testsuite/gcc.target/i386/apx-ndd-x32-2c.c b/gcc/testsuite/gcc.target/i386/apx-ndd-x32-2c.c new file mode 100644 index 00000000000..0485833e813 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/apx-ndd-x32-2c.c @@ -0,0 +1,6 @@ +/* PR target/114696 */ +/* { dg-do assemble { target { apxf && { ! ia32 } } } } */ +/* { dg-require-effective-target maybe_x32 } */ +/* { dg-options "-mapxf -O0 -mx32 -maddress-mode=long" } */ + +#include "apx-ndd-x32-2a.c" diff --git a/gcc/testsuite/gcc.target/i386/apx-ndd-x32-2d.c b/gcc/testsuite/gcc.target/i386/apx-ndd-x32-2d.c new file mode 100644 index 00000000000..ec62d373684 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/apx-ndd-x32-2d.c @@ -0,0 +1,6 @@ +/* PR target/114696 */ +/* { dg-do assemble { target { apxf && { ! ia32 } } } } */ +/* { dg-require-effective-target maybe_x32 } */ +/* { dg-options "-mapxf -O2 -mx32 -maddress-mode=long" } */ + +#include "apx-ndd-x32-2a.c"