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[1.34.21.66]) by smtp.gmail.com with ESMTPSA id l27-20020a635b5b000000b005dcbb855530sm7658404pgm.76.2024.03.26.08.00.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Mar 2024 08:00:38 -0700 (PDT) From: Peter Yin To: patrick@stwcx.xyz, Wim Van Sebroeck , Guenter Roeck , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 1/4] ARM: dts: aspeed: Add the AST2500 WDT with SCU register Date: Tue, 26 Mar 2024 23:00:24 +0800 Message-Id: <20240326150027.3015958-2-peteryin.openbmc@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240326150027.3015958-1-peteryin.openbmc@gmail.com> References: <20240326150027.3015958-1-peteryin.openbmc@gmail.com> MIME-Version: 1.0 X-BeenThere: linux-aspeed@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux ASPEED SoC development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linux-aspeed-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linux-aspeed" The AST2500 WDT references the System Control Unit register for its operation. Signed-off-by: Peter Yin --- arch/arm/boot/dts/aspeed/aspeed-g5.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g5.dtsi index 04f98d1dbb97..5fd12c057c31 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-g5.dtsi @@ -410,12 +410,14 @@ wdt1: watchdog@1e785000 { compatible = "aspeed,ast2500-wdt"; reg = <0x1e785000 0x20>; clocks = <&syscon ASPEED_CLK_APB>; + aspeed,scu = <&syscon>; }; wdt2: watchdog@1e785020 { compatible = "aspeed,ast2500-wdt"; reg = <0x1e785020 0x20>; clocks = <&syscon ASPEED_CLK_APB>; + aspeed,scu = <&syscon>; }; wdt3: watchdog@1e785040 { @@ -423,6 +425,7 @@ wdt3: watchdog@1e785040 { reg = <0x1e785040 0x20>; clocks = <&syscon ASPEED_CLK_APB>; status = "disabled"; + aspeed,scu = <&syscon>; }; pwm_tacho: pwm-tacho-controller@1e786000 { From patchwork Tue Mar 26 15:00:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Yin X-Patchwork-Id: 1916219 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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[1.34.21.66]) by smtp.gmail.com with ESMTPSA id l27-20020a635b5b000000b005dcbb855530sm7658404pgm.76.2024.03.26.08.00.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Mar 2024 08:00:41 -0700 (PDT) From: Peter Yin To: patrick@stwcx.xyz, Wim Van Sebroeck , Guenter Roeck , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 2/4] ARM: dts: aspeed: Add the AST2600 WDT with SCU register Date: Tue, 26 Mar 2024 23:00:25 +0800 Message-Id: <20240326150027.3015958-3-peteryin.openbmc@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240326150027.3015958-1-peteryin.openbmc@gmail.com> References: <20240326150027.3015958-1-peteryin.openbmc@gmail.com> MIME-Version: 1.0 X-BeenThere: linux-aspeed@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux ASPEED SoC development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linux-aspeed-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linux-aspeed" The AST2600 Watchdog Timer (WDT) references the System Control Unit (SCU) register for its operation. Signed-off-by: Peter Yin --- arch/arm/boot/dts/aspeed/aspeed-g6.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi index 5f640b7d6b6d..2f7788f2f153 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi @@ -558,23 +558,27 @@ uart5: serial@1e784000 { wdt1: watchdog@1e785000 { compatible = "aspeed,ast2600-wdt"; reg = <0x1e785000 0x40>; + aspeed,scu = <&syscon>; }; wdt2: watchdog@1e785040 { compatible = "aspeed,ast2600-wdt"; reg = <0x1e785040 0x40>; + aspeed,scu = <&syscon>; status = "disabled"; }; wdt3: watchdog@1e785080 { compatible = "aspeed,ast2600-wdt"; reg = <0x1e785080 0x40>; + aspeed,scu = <&syscon>; status = "disabled"; }; wdt4: watchdog@1e7850c0 { compatible = "aspeed,ast2600-wdt"; reg = <0x1e7850C0 0x40>; + aspeed,scu = <&syscon>; status = "disabled"; }; From patchwork Tue Mar 26 15:00:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Yin X-Patchwork-Id: 1916220 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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[1.34.21.66]) by smtp.gmail.com with ESMTPSA id l27-20020a635b5b000000b005dcbb855530sm7658404pgm.76.2024.03.26.08.00.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Mar 2024 08:00:44 -0700 (PDT) From: Peter Yin To: patrick@stwcx.xyz, Wim Van Sebroeck , Guenter Roeck , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 3/4] dt-bindings: watchdog: aspeed-wdt: Add aspeed,scu Date: Tue, 26 Mar 2024 23:00:26 +0800 Message-Id: <20240326150027.3015958-4-peteryin.openbmc@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240326150027.3015958-1-peteryin.openbmc@gmail.com> References: <20240326150027.3015958-1-peteryin.openbmc@gmail.com> MIME-Version: 1.0 X-BeenThere: linux-aspeed@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux ASPEED SoC development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linux-aspeed-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linux-aspeed" To use the SCU register to obtain reset flags for supporting bootstatus. Signed-off-by: Peter Yin --- Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt b/Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt index 3208adb3e52e..80a1f58b5a2e 100644 --- a/Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt +++ b/Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt @@ -8,6 +8,8 @@ Required properties: - reg: physical base address of the controller and length of memory mapped region + - aspeed,scu: a reference to the System Control Unit node of the Aspeed + SOC. Optional properties: @@ -62,6 +64,7 @@ Examples: reg = <0x1e785000 0x1c>; aspeed,reset-type = "system"; aspeed,external-signal; + aspeed,scu = <&syscon>; }; #include @@ -70,4 +73,5 @@ Examples: reg = <0x1e785040 0x40>; aspeed,reset-mask = ; + aspeed,scu = <&syscon>; }; From patchwork Tue Mar 26 15:00:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Yin X-Patchwork-Id: 1916221 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20230601 header.b=Zcf3hZbd; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=2404:9400:2:0:216:3eff:fee1:b9f1; helo=lists.ozlabs.org; envelope-from=linux-aspeed-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=patchwork.ozlabs.org) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2404:9400:2:0:216:3eff:fee1:b9f1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4V3tKc5g7sz1yWv for ; Wed, 27 Mar 2024 02:01:08 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20230601 header.b=Zcf3hZbd; dkim-atps=neutral Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4V3tKc4fWFz3vdg for ; Wed, 27 Mar 2024 02:01:08 +1100 (AEDT) X-Original-To: linux-aspeed@lists.ozlabs.org Delivered-To: linux-aspeed@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20230601 header.b=Zcf3hZbd; dkim-atps=neutral Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:4864:20::42b; helo=mail-pf1-x42b.google.com; envelope-from=peteryin.openbmc@gmail.com; receiver=lists.ozlabs.org) Received: from mail-pf1-x42b.google.com (mail-pf1-x42b.google.com [IPv6:2607:f8b0:4864:20::42b]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4V3tKG1lgRz3vcS for ; Wed, 27 Mar 2024 02:00:50 +1100 (AEDT) Received: by mail-pf1-x42b.google.com with SMTP id d2e1a72fcca58-6e74bd85f26so4453518b3a.1 for ; Tue, 26 Mar 2024 08:00:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1711465248; x=1712070048; darn=lists.ozlabs.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=fxIIBTP4rXppfPhTT/4q0S1EVkuGtE5Ah2bvfj9/Kl4=; b=Zcf3hZbd9EjN/9/GGrcLKfWNRgihIIVWsfSwRk/S+CuzLrbzRNhfUatHLQ+K+ZFkeB 8j1Z5p0pTQleOjL4EUQraZ23+2INaYY/WMvBA3TQIJ7YypUTZ40XJjf5H0J1fewPxPh3 4Vl9ZYLjm9vR7LYT/FO+/+Xeqe3lp3CUWdnLkEENfZOMxlQOirVMW9e6ohHf194Ybzvo nphe4wm1FuMX+GFmgKqVBpqTI+zQ1nUPejFRoKxkSrX7hyMGPxLq91cHpYa3N1Gplj4J kyxeGWHxEEqETQc9pKuqNl6PNA5dCz2Ylf1AgYdwxFC1DoeuAEHl/wiAgLxe5vvsi3Yh xusQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711465248; x=1712070048; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fxIIBTP4rXppfPhTT/4q0S1EVkuGtE5Ah2bvfj9/Kl4=; b=AcWafIMdOoAQTUhnlPEUu/eAFI7WietPcO5JwFMLrt5IHV1//aLZzX56xRmqPttEsd qXuc156QHUCBGW1k6wYpUBb5aT8iaJsuwHAKXfjfrwJwLcmNQCt1uVxjbAEhLotg5jDY bLSi1Gn0czOD/oXz1hS8jWu1YDsB3dliALvXaVvhVpIqyeXhxuILNfmSkfo2D5I6skYx 1orCpKD+SZumKXzW3EOyO9ZLEiFkh0IPGMtFr91p/pkwQqeWCQAmg1ZTZYpt3lLDig2Q lNDYcLffUKYLXyZ2eqjlTg91tVEIeUDQumX1Bj3mj2mTv8zqQnhDCQ8aiS3/5AZaZZtP /KxA== X-Forwarded-Encrypted: i=1; AJvYcCVE2qqiwSDCxptDnoLCPTaM4KBR+0Vl4rGQErdTyva2wFLHFZiPvdUl+828JP3ahbfVG2vGgz5s8HFwrOXXDcyt3xyKi2u4kY21vWamew== X-Gm-Message-State: AOJu0YzomMLXdQtmRF5zyGW9uB47woD3uKBaAT8nDDOn9oRRgSCFQ1IU KqEkW8TmgqvjWY/z+a1sywGXe8G/oFrA2W8sMqQ/0Cs0R7K4MERk X-Google-Smtp-Source: AGHT+IH1cX47UcVDJeEEPc3BtsiLHnch3pmt/eT/zXRUGHXwiIA0NbF5hbSlAoW8eYDLcPteprOuGw== X-Received: by 2002:a05:6a20:6a22:b0:1a3:c3e6:aef7 with SMTP id p34-20020a056a206a2200b001a3c3e6aef7mr7554771pzk.54.1711465248497; Tue, 26 Mar 2024 08:00:48 -0700 (PDT) Received: from peter-bmc.dhcpserver.bu9bmc.local (1-34-21-66.hinet-ip.hinet.net. [1.34.21.66]) by smtp.gmail.com with ESMTPSA id l27-20020a635b5b000000b005dcbb855530sm7658404pgm.76.2024.03.26.08.00.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Mar 2024 08:00:48 -0700 (PDT) From: Peter Yin To: patrick@stwcx.xyz, Wim Van Sebroeck , Guenter Roeck , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 4/4] drivers: watchdog: ast2500 and ast2600 support bootstatus Date: Tue, 26 Mar 2024 23:00:27 +0800 Message-Id: <20240326150027.3015958-5-peteryin.openbmc@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240326150027.3015958-1-peteryin.openbmc@gmail.com> References: <20240326150027.3015958-1-peteryin.openbmc@gmail.com> MIME-Version: 1.0 X-BeenThere: linux-aspeed@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux ASPEED SoC development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linux-aspeed-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linux-aspeed" Add WDIOF_EXTERN1 and WDIOF_CARDRESET bootstatus in ast2600 Regarding the AST2600 specification, the WDTn Timeout Status Register (WDT10) has bit 1 reserved. Bit 1 of the status register indicates on ast2500 if the boot was from the second boot source. It does not indicate that the most recent reset was triggered by the watchdog. The code should just be changed to set WDIOF_CARDRESET if bit 0 of the status register is set. Include SCU register to veriy WDIOF_EXTERN1 in ast2600 SCU74 or ast2500 SCU3C when bit1 is set. Signed-off-by: Peter Yin --- drivers/watchdog/aspeed_wdt.c | 53 ++++++++++++++++++++++++----------- 1 file changed, 37 insertions(+), 16 deletions(-) diff --git a/drivers/watchdog/aspeed_wdt.c b/drivers/watchdog/aspeed_wdt.c index b4773a6aaf8c..52afc5240b1c 100644 --- a/drivers/watchdog/aspeed_wdt.c +++ b/drivers/watchdog/aspeed_wdt.c @@ -11,10 +11,12 @@ #include #include #include +#include #include #include #include #include +#include #include static bool nowayout = WATCHDOG_NOWAYOUT; @@ -65,23 +67,32 @@ MODULE_DEVICE_TABLE(of, aspeed_wdt_of_table); #define WDT_RELOAD_VALUE 0x04 #define WDT_RESTART 0x08 #define WDT_CTRL 0x0C -#define WDT_CTRL_BOOT_SECONDARY BIT(7) -#define WDT_CTRL_RESET_MODE_SOC (0x00 << 5) -#define WDT_CTRL_RESET_MODE_FULL_CHIP (0x01 << 5) -#define WDT_CTRL_RESET_MODE_ARM_CPU (0x10 << 5) -#define WDT_CTRL_1MHZ_CLK BIT(4) -#define WDT_CTRL_WDT_EXT BIT(3) -#define WDT_CTRL_WDT_INTR BIT(2) -#define WDT_CTRL_RESET_SYSTEM BIT(1) -#define WDT_CTRL_ENABLE BIT(0) +#define WDT_CTRL_BOOT_SECONDARY BIT(7) +#define WDT_CTRL_RESET_MODE_SOC (0x00 << 5) +#define WDT_CTRL_RESET_MODE_FULL_CHIP (0x01 << 5) +#define WDT_CTRL_RESET_MODE_ARM_CPU (0x10 << 5) +#define WDT_CTRL_1MHZ_CLK BIT(4) +#define WDT_CTRL_WDT_EXT BIT(3) +#define WDT_CTRL_WDT_INTR BIT(2) +#define WDT_CTRL_RESET_SYSTEM BIT(1) +#define WDT_CTRL_ENABLE BIT(0) #define WDT_TIMEOUT_STATUS 0x10 -#define WDT_TIMEOUT_STATUS_IRQ BIT(2) -#define WDT_TIMEOUT_STATUS_BOOT_SECONDARY BIT(1) +#define WDT_TIMEOUT_STATUS_IRQ BIT(2) +#define WDT_TIMEOUT_STATUS_BOOT_SECONDARY BIT(1) +#define WDT_TIMEOUT_STATUS_EVENT BIT(0) #define WDT_CLEAR_TIMEOUT_STATUS 0x14 -#define WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION BIT(0) +#define WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION BIT(0) #define WDT_RESET_MASK1 0x1c #define WDT_RESET_MASK2 0x20 +/* + * Ast2600 SCU74 bit1 is External reset flag + * Ast2500 SCU3C bit1 is External reset flag + */ +#define EXTERN_RESET_FLAG BIT(1) +#define AST2500_SYSTEM_RESET_EVENT (0x3C) +#define AST2600_SYSTEM_RESET_EVENT (0x74) + /* * WDT_RESET_WIDTH controls the characteristics of the external pulse (if * enabled), specifically: @@ -458,15 +469,25 @@ static int aspeed_wdt_probe(struct platform_device *pdev) writel(duration - 1, wdt->base + WDT_RESET_WIDTH); } + struct regmap *scu_base = syscon_regmap_lookup_by_phandle(dev->of_node, + "aspeed,scu"); status = readl(wdt->base + WDT_TIMEOUT_STATUS); - if (status & WDT_TIMEOUT_STATUS_BOOT_SECONDARY) { + if (status & WDT_TIMEOUT_STATUS_EVENT) wdt->wdd.bootstatus = WDIOF_CARDRESET; - if (of_device_is_compatible(np, "aspeed,ast2400-wdt") || - of_device_is_compatible(np, "aspeed,ast2500-wdt")) - wdt->wdd.groups = bswitch_groups; + if (of_device_is_compatible(np, "aspeed,ast2600-wdt")) { + regmap_read(scu_base, AST2600_SYSTEM_RESET_EVENT, &status); + } else { + regmap_read(scu_base, AST2500_SYSTEM_RESET_EVENT, &status); + wdt->wdd.groups = bswitch_groups; } + /* + * Reset cause by Extern Reset + */ + if (status & EXTERN_RESET_FLAG) + wdt->wdd.bootstatus |= WDIOF_EXTERN1; + dev_set_drvdata(dev, wdt); return devm_watchdog_register_device(dev, &wdt->wdd);