From patchwork Sat Mar 16 22:56:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonas Karlman X-Patchwork-Id: 1912829 X-Patchwork-Delegate: ykai007@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=kwiboo.se header.i=@kwiboo.se header.a=rsa-sha256 header.s=fe-e1b5cab7be header.b=jJBpB4+f; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4TxxMp4sRSz23sC for ; Sun, 17 Mar 2024 09:57:26 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id C944487FCC; Sat, 16 Mar 2024 23:57:20 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kwiboo.se Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; secure) header.d=kwiboo.se header.i=@kwiboo.se header.b="jJBpB4+f"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 8C42C88053; Sat, 16 Mar 2024 23:57:19 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from smtp.forwardemail.net (smtp.forwardemail.net [149.28.215.223]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 3AF1787B30 for ; Sat, 16 Mar 2024 23:57:15 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kwiboo.se Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=SRS0=8b2e=KX=kwiboo.se=jonas@fe-bounces.kwiboo.se DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kwiboo.se; h=Content-Transfer-Encoding: MIME-Version: References: In-Reply-To: Message-ID: Date: Subject: Cc: To: From; q=dns/txt; s=fe-e1b5cab7be; t=1710629824; bh=/IT/Ve3RLoQVvDdsJkCN3OycCsxh8tmllZ+/fq6SxPY=; b=jJBpB4+f8QruZr2WGlg+B0fzNG+wT+u41Pp+33dL+mSqXhfQ9qWQ92pBM2cU15R5w/709tqpa BNV2b7Xc2b6DShaPC0KW7+xMk5zA2nEbYzQUi31J9XW8yE19JnLO0tK069wq50M2i1eyzLJcILi T9Waq3Cllc3vyZMNbEmYPOoIFqixgUlBq6XMsWsI5hAqpxZg0V5q+8dI+C2pF31AOXQ38dMAMJ7 YySnHsxK/oqN7fo6obbngRQYfRsuX03Hhdh+1L872hfSKKz7Jt3c8ZQKcTd2tyXuJ36xRMKyFT9 i2um5iHXYr29chfjJAzuxRG1BskxSeouhLo4GntSWZhA== From: Jonas Karlman To: Kever Yang , Simon Glass , Philipp Tomsich , Tom Rini , Andy Yan Cc: Akash Gajjar , u-boot@lists.denx.de, Jonas Karlman Subject: [PATCH 01/13] board: rockchip: rk3308: Add device tree files and myself to MAINTAINERS Date: Sat, 16 Mar 2024 22:56:27 +0000 Message-ID: <20240316225655.3244348-2-jonas@kwiboo.se> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240316225655.3244348-1-jonas@kwiboo.se> References: <20240316225655.3244348-1-jonas@kwiboo.se> MIME-Version: 1.0 X-Report-Abuse-To: abuse@forwardemail.net X-Report-Abuse: abuse@forwardemail.net X-Complaints-To: abuse@forwardemail.net X-ForwardEmail-Version: 0.4.40 X-ForwardEmail-Sender: rfc822; jonas@kwiboo.se, smtp.forwardemail.net, 149.28.215.223 X-ForwardEmail-ID: 65f623c00957eaab7babfc8d X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Update MAINTAINERS files for RK3308 boards to include related device tree files. Also add myself as a reviewer for the ROCK Pi S board. Signed-off-by: Jonas Karlman --- board/firefly/firefly-rk3308/MAINTAINERS | 1 + board/rockchip/evb_rk3308/MAINTAINERS | 5 +++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/board/firefly/firefly-rk3308/MAINTAINERS b/board/firefly/firefly-rk3308/MAINTAINERS index e584038a2033..b70ff52ea741 100644 --- a/board/firefly/firefly-rk3308/MAINTAINERS +++ b/board/firefly/firefly-rk3308/MAINTAINERS @@ -4,3 +4,4 @@ S: Maintained F: board/firefly/firefly-rk3308/ F: configs/roc-cc-rk3308_defconfig F: include/configs/firefly_rk3308.h +F: arch/arm/dts/rk3308-roc-cc* diff --git a/board/rockchip/evb_rk3308/MAINTAINERS b/board/rockchip/evb_rk3308/MAINTAINERS index fe2c5f004c34..abffbb1eb0ab 100644 --- a/board/rockchip/evb_rk3308/MAINTAINERS +++ b/board/rockchip/evb_rk3308/MAINTAINERS @@ -4,10 +4,11 @@ S: Maintained F: board/rockchip/evb_rk3308 F: include/configs/evb_rk3308.h F: configs/evb-rk3308_defconfig +F: arch/arm/dts/rk3308-evb* ROCK-PI-S M: Akash Gajjar +R: Jonas Karlman S: Maintained F: configs/rock-pi-s-rk3308_defconfig -F: arch/arm/dts/rk3308-rock-pi-s.dts -F: arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi +F: arch/arm/dts/rk3308-rock-pi-s* From patchwork Sat Mar 16 22:56:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonas Karlman X-Patchwork-Id: 1912831 X-Patchwork-Delegate: ykai007@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=kwiboo.se header.i=@kwiboo.se header.a=rsa-sha256 header.s=fe-e1b5cab7be header.b=dO/RAlJy; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4TxxNP5nH1z23sC for ; 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jonas@kwiboo.se, smtp.forwardemail.net, 167.172.40.54 X-ForwardEmail-ID: 65f623c30957eaab7babfc9f X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Sort imply statements under ROCKCHIP_RK3308 alphabetically and remove the config SPL_SERIAL statement from soc Kconfig file, it is already implyed in arch Kconfig. Signed-off-by: Jonas Karlman --- arch/arm/mach-rockchip/Kconfig | 8 ++++---- arch/arm/mach-rockchip/rk3308/Kconfig | 3 --- 2 files changed, 4 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index f68a0a48949a..2fde8655d18a 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -161,13 +161,13 @@ config ROCKCHIP_RK3308 select SPL_ATF_NO_PLATFORM_PARAM select SPL_LOAD_FIT imply ROCKCHIP_COMMON_BOARD - imply SPL_ROCKCHIP_COMMON_BOARD imply SPL_CLK - imply SPL_REGMAP - imply SPL_SYSCON imply SPL_RAM - imply SPL_SERIAL + imply SPL_REGMAP + imply SPL_ROCKCHIP_COMMON_BOARD imply SPL_SEPARATE_BSS + imply SPL_SERIAL + imply SPL_SYSCON help The Rockchip RK3308 is a ARM-based Soc which embedded with quad Cortex-A35 and highly integrated audio interfaces. diff --git a/arch/arm/mach-rockchip/rk3308/Kconfig b/arch/arm/mach-rockchip/rk3308/Kconfig index 749e9995d91f..fac966207a92 100644 --- a/arch/arm/mach-rockchip/rk3308/Kconfig +++ b/arch/arm/mach-rockchip/rk3308/Kconfig @@ -23,9 +23,6 @@ config ROCKCHIP_COMMON_STACK_ADDR config TEXT_BASE default 0x00600000 -config SPL_SERIAL - default y - source "board/rockchip/evb_rk3308/Kconfig" source "board/firefly/firefly-rk3308/Kconfig" From patchwork Sat Mar 16 22:56:29 2024 Content-Type: text/plain; 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Sat, 16 Mar 2024 23:57:25 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kwiboo.se Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=SRS0=8b2e=KX=kwiboo.se=jonas@fe-bounces.kwiboo.se DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kwiboo.se; h=Content-Transfer-Encoding: MIME-Version: References: In-Reply-To: Message-ID: Date: Subject: Cc: To: From; q=dns/txt; s=fe-e1b5cab7be; t=1710629831; bh=PlEpcaT7dQ36zmQxKpZ3JUcIpvng90JNiLQipcfhU5Y=; b=UtvLKIrZK9BBrSsoTymi/ORaV1IfuqgoMPGpNWEGEaNRzoLGImEVsYeytXGBCTx09nZoEIIW/ cPqDzGu7yRYPfdK2JZBRTwIj8z4aaCHrx5DHJLon/paDWAqIl7QH2GtlIwKT7b7c7ltnRKLVa78 89nbz6kNyZJg2NkPjiuejrvULIFOhr5dKbh6Tx4xT1639K59CtjwrWfRBukcZvzhMArbtCzagke riVDPF1uGFJq4PRwr2jE3v8sl5cfXYSpIjoUJuo7fCWrB9S3sVl9/NLQPPk5MxgxwaIPs0mOfAg 3y1IljF5/F9HqHdM59Zamu6PwB2/+exO2lDkgdnryv9g== From: Jonas Karlman To: Kever Yang , Simon Glass , Philipp Tomsich , Tom Rini , Andy Yan , Akash Gajjar , Jonas Karlman Cc: u-boot@lists.denx.de Subject: [PATCH 03/13] rockchip: rk3308: Enable ARMv8 crypto and FIT checksum validation Date: Sat, 16 Mar 2024 22:56:29 +0000 Message-ID: <20240316225655.3244348-4-jonas@kwiboo.se> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240316225655.3244348-1-jonas@kwiboo.se> References: <20240316225655.3244348-1-jonas@kwiboo.se> MIME-Version: 1.0 X-Report-Abuse-To: abuse@forwardemail.net X-Report-Abuse: abuse@forwardemail.net X-Complaints-To: abuse@forwardemail.net X-ForwardEmail-Version: 0.4.40 X-ForwardEmail-Sender: rfc822; jonas@kwiboo.se, smtp.forwardemail.net, 149.28.215.223 X-ForwardEmail-ID: 65f623c60957eaab7babfcb1 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The RK3308 SoC support ARMv8 Cryptography Extensions and use of the ARMv8 crypto extensions help speed up FIT checksum validation in SPL. Imply ARMV8_SET_SMPEN and ARMV8_CRYPTO to take advantage of the crypto extensions for SHA256 when validating checksum of FIT images. Imply SPL_FIT_SIGNATURE and LEGACY_IMAGE_FORMAT to enable FIT checksum validation on all RK3308 boards. Also disable CONFIG_SPL_RAW_IMAGE_SUPPORT in board defconfigs to ensure SPL does not try to jump to code that failed checksum validation. Signed-off-by: Jonas Karlman --- arch/arm/mach-rockchip/Kconfig | 4 ++++ configs/evb-rk3308_defconfig | 1 + configs/roc-cc-rk3308_defconfig | 1 + configs/rock-pi-s-rk3308_defconfig | 1 + 4 files changed, 7 insertions(+) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 2fde8655d18a..71c5945b5742 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -160,8 +160,12 @@ config ROCKCHIP_RK3308 select SPL_ATF select SPL_ATF_NO_PLATFORM_PARAM select SPL_LOAD_FIT + imply ARMV8_CRYPTO + imply ARMV8_SET_SMPEN + imply LEGACY_IMAGE_FORMAT imply ROCKCHIP_COMMON_BOARD imply SPL_CLK + imply SPL_FIT_SIGNATURE imply SPL_RAM imply SPL_REGMAP imply SPL_ROCKCHIP_COMMON_BOARD diff --git a/configs/evb-rk3308_defconfig b/configs/evb-rk3308_defconfig index d57b2f6b8e55..6a6d2540317d 100644 --- a/configs/evb-rk3308_defconfig +++ b/configs/evb-rk3308_defconfig @@ -20,6 +20,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_MAX_SIZE=0x20000 CONFIG_SPL_PAD_TO=0x7f8000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_ELF is not set diff --git a/configs/roc-cc-rk3308_defconfig b/configs/roc-cc-rk3308_defconfig index 5e8f51ec01e3..2f4a160acc24 100644 --- a/configs/roc-cc-rk3308_defconfig +++ b/configs/roc-cc-rk3308_defconfig @@ -20,6 +20,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_MAX_SIZE=0x20000 CONFIG_SPL_PAD_TO=0x7f8000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_ELF is not set diff --git a/configs/rock-pi-s-rk3308_defconfig b/configs/rock-pi-s-rk3308_defconfig index 1e9cd2c0fc7e..b0ad4d6ce354 100644 --- a/configs/rock-pi-s-rk3308_defconfig +++ b/configs/rock-pi-s-rk3308_defconfig @@ -21,6 +21,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_MAX_SIZE=0x20000 CONFIG_SPL_PAD_TO=0x7f8000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_ELF is not set From patchwork Sat Mar 16 22:56:30 2024 Content-Type: text/plain; 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jonas@kwiboo.se, smtp.forwardemail.net, 149.28.215.223 X-ForwardEmail-ID: 65f623c90957eaab7babfcc3 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Like other Rockchip SoCs the RK3308 has cpu id programmed into OTP memory. The rockchip_otp driver already support the RK3308 variant. However, the device tree is missing a node to enable use of OTP. Add the missing otp node to soc u-boot.dtsi, enable the rockchip_otp driver and enable use of misc_init_r() to set ethaddr based on cpu id. Signed-off-by: Jonas Karlman --- arch/arm/dts/rk3308-u-boot.dtsi | 11 +++++++++++ arch/arm/mach-rockchip/Kconfig | 3 +++ 2 files changed, 14 insertions(+) diff --git a/arch/arm/dts/rk3308-u-boot.dtsi b/arch/arm/dts/rk3308-u-boot.dtsi index db2c20a7055e..396fefb743cf 100644 --- a/arch/arm/dts/rk3308-u-boot.dtsi +++ b/arch/arm/dts/rk3308-u-boot.dtsi @@ -10,6 +10,17 @@ mmc0 = &emmc; mmc1 = &sdmmc; }; + + otp: nvmem@ff210000 { + compatible = "rockchip,rk3308-otp"; + reg = <0x0 0xff210000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + + cpu_id: id@7 { + reg = <0x07 0x10>; + }; + }; }; &cru { diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 71c5945b5742..6e07a70bf4ae 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -163,7 +163,10 @@ config ROCKCHIP_RK3308 imply ARMV8_CRYPTO imply ARMV8_SET_SMPEN imply LEGACY_IMAGE_FORMAT + imply MISC + imply MISC_INIT_R imply ROCKCHIP_COMMON_BOARD + imply ROCKCHIP_OTP imply SPL_CLK imply SPL_FIT_SIGNATURE imply SPL_RAM From patchwork Sat Mar 16 22:56:31 2024 Content-Type: text/plain; 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Sat, 16 Mar 2024 23:57:29 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kwiboo.se Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=SRS0=8b2e=KX=kwiboo.se=jonas@fe-bounces.kwiboo.se DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kwiboo.se; h=Content-Transfer-Encoding: MIME-Version: References: In-Reply-To: Message-ID: Date: Subject: Cc: To: From; q=dns/txt; s=fe-e1b5cab7be; t=1710629837; bh=6WHhb1pN9axaeXWgBwqMSAJ//8SndkGv37OheVC3NFs=; b=KdkS215fb/YH12sjNX480m+Hz7Q5hkXNlJw57FQvWrywv70EUJU1nHSKvpehePTwdHiLvQPnx l3a3OALZo1/nBH3d3+JbEE2nX+bs4YCcisRUfjlJ3bVa5kGgCK3xN2Y4z7lnPtpwaudqC2ChfQ9 9JnGb7b5CGGMJp31q3TuESFlANF6iSFlGKN/wJ+3pjYnFzUSW1/9Q9QBHvjVJqdc4xg+vIvowEz KqvM5rGMoBBl9yATzfkheAArRczSnPV97opbvEinDiYlUob2LJs55IiCELU0lCDyLLUtnYDxulA UYQ6ZYINU9ArV5W0v1lY+gBMkc9NINyV6QuVqvUt9XkQ== From: Jonas Karlman To: Kever Yang , Simon Glass , Philipp Tomsich , Tom Rini Cc: Andy Yan , Akash Gajjar , u-boot@lists.denx.de, Jonas Karlman Subject: [PATCH 05/13] rockchip: rk3308: Enable random generator Date: Sat, 16 Mar 2024 22:56:31 +0000 Message-ID: <20240316225655.3244348-6-jonas@kwiboo.se> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240316225655.3244348-1-jonas@kwiboo.se> References: <20240316225655.3244348-1-jonas@kwiboo.se> MIME-Version: 1.0 X-Report-Abuse-To: abuse@forwardemail.net X-Report-Abuse: abuse@forwardemail.net X-Complaints-To: abuse@forwardemail.net X-ForwardEmail-Version: 0.4.40 X-ForwardEmail-Sender: rfc822; jonas@kwiboo.se, smtp.forwardemail.net, 149.28.215.223 X-ForwardEmail-ID: 65f623cd0957eaab7babfcd5 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The RK3308 SoC contain a crypto engine block that can generate random numbers. Add rng node to soc u-boot.dtsi and enable Kconfig options to take advantage of the random generator. Signed-off-by: Jonas Karlman --- arch/arm/dts/rk3308-u-boot.dtsi | 5 +++++ arch/arm/mach-rockchip/Kconfig | 2 ++ 2 files changed, 7 insertions(+) diff --git a/arch/arm/dts/rk3308-u-boot.dtsi b/arch/arm/dts/rk3308-u-boot.dtsi index 396fefb743cf..d6c71f62bc93 100644 --- a/arch/arm/dts/rk3308-u-boot.dtsi +++ b/arch/arm/dts/rk3308-u-boot.dtsi @@ -21,6 +21,11 @@ reg = <0x07 0x10>; }; }; + + rng: rng@ff2f0000 { + compatible = "rockchip,cryptov2-rng"; + reg = <0x0 0xff2f0000 0x0 0x4000>; + }; }; &cru { diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 6e07a70bf4ae..fa5917236a43 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -162,9 +162,11 @@ config ROCKCHIP_RK3308 select SPL_LOAD_FIT imply ARMV8_CRYPTO imply ARMV8_SET_SMPEN + imply DM_RNG imply LEGACY_IMAGE_FORMAT imply MISC imply MISC_INIT_R + imply RNG_ROCKCHIP imply ROCKCHIP_COMMON_BOARD imply ROCKCHIP_OTP imply SPL_CLK From patchwork Sat Mar 16 22:56:32 2024 Content-Type: text/plain; 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Sat, 16 Mar 2024 23:57:36 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kwiboo.se Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=SRS0=8b2e=KX=kwiboo.se=jonas@fe-bounces.kwiboo.se DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kwiboo.se; h=Content-Transfer-Encoding: MIME-Version: References: In-Reply-To: Message-ID: Date: Subject: Cc: To: From; q=dns/txt; s=fe-e1b5cab7be; t=1710629842; bh=3JVhjyQc7IrFGo6B2ZSXqC5wbgJrxALQaNpLJ8DDuZ8=; b=mzGh6+Do2da21S0EqRRrWAjQyPRHxUh4xUNtFUWEi5mX3qWZ4lWJpCcDiyRACU88cvzFe0GOY GObUvgu74mODKJ/ClLPTa4lTYWNcO0DTaiJjSO9Tsq8aQewy2hpTnoMaIvF7/2VDmHKz8pj+RFA nWgOQp2Ik5ZkvHEhYkCLu8HIv2ytKdAg637nbQlxopeCnwmCkjkwRdWFoPideRw1CpEvEhLNG2m /9QBdSeHUFgv3Pidh8FOcGY8G2b0xZS5J/Ms+EnEdKtrVmnRjxowuci5kaXMrzYQzV7v+Rn+v5U m8pI4atRiIDyTICOs+xPlkBET3xfkLNFOUs/j5R44DsA== From: Jonas Karlman To: Kever Yang , Simon Glass , Philipp Tomsich , Tom Rini , Andy Yan , Akash Gajjar , Jonas Karlman Cc: u-boot@lists.denx.de Subject: [PATCH 06/13] rockchip: rk3308: Fix loading FIT from SD-card when booting from eMMC Date: Sat, 16 Mar 2024 22:56:32 +0000 Message-ID: <20240316225655.3244348-7-jonas@kwiboo.se> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240316225655.3244348-1-jonas@kwiboo.se> References: <20240316225655.3244348-1-jonas@kwiboo.se> MIME-Version: 1.0 X-Report-Abuse-To: abuse@forwardemail.net X-Report-Abuse: abuse@forwardemail.net X-Complaints-To: abuse@forwardemail.net X-ForwardEmail-Version: 0.4.40 X-ForwardEmail-Sender: rfc822; jonas@kwiboo.se, smtp.forwardemail.net, 167.172.40.54 X-ForwardEmail-ID: 65f623d10957eaab7babfce7 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean When RK3308 boards run SPL from eMMC and fail to load FIT from eMMC due to it being missing or checksum validation fails there can be a fallback to read FIT from SD-card. However, without proper pinctrl configuration reading FIT from SD-card may fail: U-Boot SPL 2024.04-rc4 (Mar 16 2024 - 12:36:12 +0000) Trying to boot from MMC2 mmc_load_image_raw_sector: mmc block read error Trying to boot from MMC1 Card did not respond to voltage select! : -110 mmc_init: -95, time 12 spl: mmc init failed with error: -95 Trying to boot from MMC2 mmc_load_image_raw_sector: mmc block read error SPL: failed to boot from all boot devices (err=-6) ### ERROR ### Please RESET the board ### Fix this by tagging related emmc and sdmmc pinctrl nodes with bootph props. Also sort and move common nodes shared by all boards to the SoC u-boot.dtsi. Imply SPL_PINCTRL and SPL_DM_SEQ_ALIAS to apply correct pinconf before trying to load FIT from a device. Move u-boot,spl-boot-order to soc u-boot.dtsi and define both sdmmc and emmc nodes as fallback. Also fix boot from eMMC (SD NAND) on ROCK Pi S by using correct pinctrl. Signed-off-by: Jonas Karlman --- arch/arm/dts/rk3308-evb-u-boot.dtsi | 11 ++-- arch/arm/dts/rk3308-roc-cc-u-boot.dtsi | 15 +++-- arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi | 36 ++++------- arch/arm/dts/rk3308-u-boot.dtsi | 74 +++++++++++++++++++++-- arch/arm/mach-rockchip/Kconfig | 2 + configs/evb-rk3308_defconfig | 2 +- configs/roc-cc-rk3308_defconfig | 4 +- configs/rock-pi-s-rk3308_defconfig | 2 +- 8 files changed, 103 insertions(+), 43 deletions(-) diff --git a/arch/arm/dts/rk3308-evb-u-boot.dtsi b/arch/arm/dts/rk3308-evb-u-boot.dtsi index d15ba94d37b6..007a69f9a60e 100644 --- a/arch/arm/dts/rk3308-evb-u-boot.dtsi +++ b/arch/arm/dts/rk3308-evb-u-boot.dtsi @@ -4,14 +4,11 @@ */ #include "rk3308-u-boot.dtsi" -/ { - chosen { - u-boot,spl-boot-order = "same-as-spl", &emmc; - }; -}; - &uart4 { bootph-all; clock-frequency = <24000000>; - status = "okay"; +}; + +&uart4_xfer { + bootph-all; }; diff --git a/arch/arm/dts/rk3308-roc-cc-u-boot.dtsi b/arch/arm/dts/rk3308-roc-cc-u-boot.dtsi index 97d922c435d4..d823ac00c771 100644 --- a/arch/arm/dts/rk3308-roc-cc-u-boot.dtsi +++ b/arch/arm/dts/rk3308-roc-cc-u-boot.dtsi @@ -4,14 +4,19 @@ */ #include "rk3308-u-boot.dtsi" -/ { - chosen { - u-boot,spl-boot-order = "same-as-spl", &emmc; - }; +&gpio4 { + bootph-pre-ram; }; &uart2 { bootph-all; clock-frequency = <24000000>; - status = "okay"; +}; + +&uart2m0_xfer { + bootph-all; +}; + +&vcc_sd { + bootph-pre-ram; }; diff --git a/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi b/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi index d88dee80573e..c92e1fbf1f53 100644 --- a/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi +++ b/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi @@ -4,39 +4,29 @@ */ #include "rk3308-u-boot.dtsi" -/ { - chosen { - u-boot,spl-boot-order = "same-as-spl", &emmc, &sdmmc; - }; +&emmc { + cap-sd-highspeed; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus4>; }; -&uart0 { - bootph-all; -}; - -&pinctrl { - bootph-some-ram; - - uart0 { - bootph-some-ram; - }; - rtc { - bootph-some-ram; - }; +&emmc_bus4 { + bootph-pre-ram; }; -&uart0_xfer { - bootph-some-ram; +&uart0 { + bootph-all; + clock-frequency = <24000000>; }; &uart0_cts { - bootph-some-ram; + bootph-all; }; &uart0_rts { - bootph-some-ram; + bootph-all; }; -&rtc_32k { - bootph-some-ram; +&uart0_xfer { + bootph-all; }; diff --git a/arch/arm/dts/rk3308-u-boot.dtsi b/arch/arm/dts/rk3308-u-boot.dtsi index d6c71f62bc93..ede07e1783ff 100644 --- a/arch/arm/dts/rk3308-u-boot.dtsi +++ b/arch/arm/dts/rk3308-u-boot.dtsi @@ -11,6 +11,10 @@ mmc1 = &sdmmc; }; + chosen { + u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc; + }; + otp: nvmem@ff210000 { compatible = "rockchip,rk3308-otp"; reg = <0x0 0xff210000 0x0 0x4000>; @@ -37,21 +41,81 @@ }; &emmc { + bootph-pre-ram; + bootph-some-ram; + /* mmc to sram can't do dma, prevent aborts transferring TF-A parts */ u-boot,spl-fifo-mode; +}; + +&emmc_bus8 { + bootph-pre-ram; +}; + +&emmc_clk { + bootph-pre-ram; +}; + +&emmc_cmd { + bootph-pre-ram; +}; + +&grf { bootph-all; }; -&sdmmc { +&pcfg_pull_none { bootph-all; - u-boot,spl-fifo-mode; }; -&grf { +&pcfg_pull_none_4ma { + bootph-pre-ram; +}; + +&pcfg_pull_none_8ma { + bootph-pre-ram; +}; + +&pcfg_pull_up { + bootph-all; +}; + +&pcfg_pull_up_4ma { + bootph-pre-ram; +}; + +&pcfg_pull_up_8ma { + bootph-pre-ram; +}; + +&pinctrl { bootph-all; }; -&saradc { +&rtc_32k { bootph-all; - status = "okay"; +}; + +&sdmmc { + bootph-pre-ram; + bootph-some-ram; + + /* mmc to sram can't do dma, prevent aborts transferring TF-A parts */ + u-boot,spl-fifo-mode; +}; + +&sdmmc_bus4 { + bootph-pre-ram; +}; + +&sdmmc_clk { + bootph-pre-ram; +}; + +&sdmmc_cmd { + bootph-pre-ram; +}; + +&sdmmc_det { + bootph-pre-ram; }; diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index fa5917236a43..3d6a76a793e7 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -170,7 +170,9 @@ config ROCKCHIP_RK3308 imply ROCKCHIP_COMMON_BOARD imply ROCKCHIP_OTP imply SPL_CLK + imply SPL_DM_SEQ_ALIAS imply SPL_FIT_SIGNATURE + imply SPL_PINCTRL imply SPL_RAM imply SPL_REGMAP imply SPL_ROCKCHIP_COMMON_BOARD diff --git a/configs/evb-rk3308_defconfig b/configs/evb-rk3308_defconfig index 6a6d2540317d..9dc7d9c0caea 100644 --- a/configs/evb-rk3308_defconfig +++ b/configs/evb-rk3308_defconfig @@ -40,7 +40,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64 CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_REGMAP=y CONFIG_SYSCON=y diff --git a/configs/roc-cc-rk3308_defconfig b/configs/roc-cc-rk3308_defconfig index 2f4a160acc24..041fa75b9659 100644 --- a/configs/roc-cc-rk3308_defconfig +++ b/configs/roc-cc-rk3308_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="rk3308-roc-cc" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3308=y @@ -40,7 +41,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64 CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_REGMAP=y CONFIG_SYSCON=y @@ -57,6 +58,7 @@ CONFIG_PHY=y CONFIG_PINCTRL=y CONFIG_REGULATOR_PWM=y CONFIG_DM_REGULATOR_FIXED=y +CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_BAUDRATE=1500000 diff --git a/configs/rock-pi-s-rk3308_defconfig b/configs/rock-pi-s-rk3308_defconfig index b0ad4d6ce354..27ee24a62290 100644 --- a/configs/rock-pi-s-rk3308_defconfig +++ b/configs/rock-pi-s-rk3308_defconfig @@ -41,7 +41,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64 CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_REGMAP=y CONFIG_SYSCON=y From patchwork Sat Mar 16 22:56:33 2024 Content-Type: text/plain; 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jonas@kwiboo.se, smtp.forwardemail.net, 149.28.215.223 X-ForwardEmail-ID: 65f623d40957eaab7babfcf9 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Finley Xiao Add support to get and set the SCLK_RTC32K clock rate. Signed-off-by: Finley Xiao [jonas@kwiboo.se: Update commit message] Signed-off-by: Jonas Karlman --- arch/arm/include/asm/arch-rk3308/cru_rk3308.h | 14 +++ drivers/clk/rockchip/clk_rk3308.c | 95 +++++++++++++++++++ 2 files changed, 109 insertions(+) diff --git a/arch/arm/include/asm/arch-rk3308/cru_rk3308.h b/arch/arm/include/asm/arch-rk3308/cru_rk3308.h index 84b63e4d5682..091ae82d7cc1 100644 --- a/arch/arm/include/asm/arch-rk3308/cru_rk3308.h +++ b/arch/arm/include/asm/arch-rk3308/cru_rk3308.h @@ -147,6 +147,20 @@ enum { CORE_DIV_CON_SHIFT = 0, CORE_DIV_CON_MASK = 0x0f << CORE_DIV_CON_SHIFT, + /* CRU_CLK_SEL2_CON */ + CLK_RTC32K_SEL_SHIFT = 8, + CLK_RTC32K_SEL_MASK = 3 << CLK_RTC32K_SEL_SHIFT, + CLK_RTC32K_IO = 0, + CLK_RTC32K_PVTM, + CLK_RTC32K_FRAC_DIV, + CLK_RTC32K_DIV, + + /* CRU_CLK_SEL3_CON */ + CLK_RTC32K_FRAC_NUMERATOR_SHIFT = 16, + CLK_RTC32K_FRAC_NUMERATOR_MASK = 0xffff << 16, + CLK_RTC32K_FRAC_DENOMINATOR_SHIFT = 0, + CLK_RTC32K_FRAC_DENOMINATOR_MASK = 0xffff, + /* CRU_CLK_SEL5_CON */ BUS_PLL_SEL_SHIFT = 6, BUS_PLL_SEL_MASK = 0x3 << BUS_PLL_SEL_SHIFT, diff --git a/drivers/clk/rockchip/clk_rk3308.c b/drivers/clk/rockchip/clk_rk3308.c index 7755b0161118..7515fc8bb244 100644 --- a/drivers/clk/rockchip/clk_rk3308.c +++ b/drivers/clk/rockchip/clk_rk3308.c @@ -65,6 +65,57 @@ static struct rockchip_pll_clock rk3308_pll_clks[] = { RK3308_MODE_CON, 6, 10, 0, NULL), }; +/* + * + * rational_best_approximation(31415, 10000, + * (1 << 8) - 1, (1 << 5) - 1, &n, &d); + * + * you may look at given_numerator as a fixed point number, + * with the fractional part size described in given_denominator. + * + * for theoretical background, see: + * http://en.wikipedia.org/wiki/Continued_fraction + */ +static void rational_best_approximation(unsigned long given_numerator, + unsigned long given_denominator, + unsigned long max_numerator, + unsigned long max_denominator, + unsigned long *best_numerator, + unsigned long *best_denominator) +{ + unsigned long n, d, n0, d0, n1, d1; + + n = given_numerator; + d = given_denominator; + n0 = 0; + d1 = 0; + n1 = 1; + d0 = 1; + for (;;) { + unsigned long t, a; + + if (n1 > max_numerator || d1 > max_denominator) { + n1 = n0; + d1 = d0; + break; + } + if (d == 0) + break; + t = d; + a = n / d; + d = n % d; + n = t; + t = n0 + a * n1; + n0 = n1; + n1 = t; + t = d0 + a * d1; + d0 = d1; + d1 = t; + } + *best_numerator = n1; + *best_denominator = d1; +} + static ulong rk3308_armclk_set_clk(struct rk3308_clk_priv *priv, ulong hz) { struct rk3308_cru *cru = priv->cru; @@ -832,6 +883,44 @@ static ulong rk3308_crypto_set_clk(struct rk3308_clk_priv *priv, ulong clk_id, return rk3308_crypto_get_clk(priv, clk_id); } +static ulong rk3308_rtc32k_get_clk(struct rk3308_clk_priv *priv, ulong clk_id) +{ + struct rk3308_cru *cru = priv->cru; + unsigned long m, n; + u32 con, fracdiv; + + con = readl(&cru->clksel_con[2]); + if ((con & CLK_RTC32K_SEL_MASK) >> CLK_RTC32K_SEL_SHIFT != + CLK_RTC32K_FRAC_DIV) + return -EINVAL; + + fracdiv = readl(&cru->clksel_con[3]); + m = fracdiv & CLK_RTC32K_FRAC_NUMERATOR_MASK; + m >>= CLK_RTC32K_FRAC_NUMERATOR_SHIFT; + n = fracdiv & CLK_RTC32K_FRAC_DENOMINATOR_MASK; + n >>= CLK_RTC32K_FRAC_DENOMINATOR_SHIFT; + + return OSC_HZ * m / n; +} + +static ulong rk3308_rtc32k_set_clk(struct rk3308_clk_priv *priv, ulong clk_id, + ulong hz) +{ + struct rk3308_cru *cru = priv->cru; + unsigned long m, n, val; + + rational_best_approximation(hz, OSC_HZ, + GENMASK(16 - 1, 0), + GENMASK(16 - 1, 0), + &m, &n); + val = m << CLK_RTC32K_FRAC_NUMERATOR_SHIFT | n; + writel(val, &cru->clksel_con[3]); + rk_clrsetreg(&cru->clksel_con[2], CLK_RTC32K_SEL_MASK, + CLK_RTC32K_FRAC_DIV << CLK_RTC32K_SEL_SHIFT); + + return rk3308_rtc32k_get_clk(priv, clk_id); +} + static ulong rk3308_clk_get_rate(struct clk *clk) { struct rk3308_clk_priv *priv = dev_get_priv(clk->dev); @@ -912,6 +1001,9 @@ static ulong rk3308_clk_get_rate(struct clk *clk) case SCLK_CRYPTO_APK: rate = rk3308_crypto_get_clk(priv, clk->id); break; + case SCLK_RTC32K: + rate = rk3308_rtc32k_get_clk(priv, clk->id); + break; default: return -ENOENT; } @@ -990,6 +1082,9 @@ static ulong rk3308_clk_set_rate(struct clk *clk, ulong rate) case SCLK_CRYPTO_APK: ret = rk3308_crypto_set_clk(priv, clk->id, rate); break; + case SCLK_RTC32K: + ret = rk3308_rtc32k_set_clk(priv, clk->id, rate); + break; default: return -ENOENT; } From patchwork Sat Mar 16 22:56:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonas Karlman X-Patchwork-Id: 1912838 X-Patchwork-Delegate: ykai007@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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Signed-off-by: Jonas Karlman --- drivers/clk/rockchip/clk_rk3308.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/clk/rockchip/clk_rk3308.c b/drivers/clk/rockchip/clk_rk3308.c index 7515fc8bb244..c46b58e31626 100644 --- a/drivers/clk/rockchip/clk_rk3308.c +++ b/drivers/clk/rockchip/clk_rk3308.c @@ -1085,6 +1085,8 @@ static ulong rk3308_clk_set_rate(struct clk *clk, ulong rate) case SCLK_RTC32K: ret = rk3308_rtc32k_set_clk(priv, clk->id, rate); break; + case USB480M: + return 0; default: return -ENOENT; } @@ -1117,6 +1119,8 @@ static int __maybe_unused rk3308_clk_set_parent(struct clk *clk, struct clk *par switch (clk->id) { case SCLK_MAC: return rk3308_mac_set_parent(clk, parent); + case USB480M: + return 0; default: break; } From patchwork Sat Mar 16 22:56:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonas Karlman X-Patchwork-Id: 1912837 X-Patchwork-Delegate: ykai007@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=kwiboo.se header.i=@kwiboo.se header.a=rsa-sha256 header.s=fe-e1b5cab7be header.b=u4+ixFDQ; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4TxxPR5N0Tz23sC for ; Sun, 17 Mar 2024 09:58:50 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 31C058809C; Sat, 16 Mar 2024 23:57:48 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kwiboo.se Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; secure) header.d=kwiboo.se header.i=@kwiboo.se header.b="u4+ixFDQ"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id A597D8809D; Sat, 16 Mar 2024 23:57:45 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from smtp.forwardemail.net (smtp.forwardemail.net [149.28.215.223]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 9CD42880A2 for ; Sat, 16 Mar 2024 23:57:40 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kwiboo.se Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=SRS0=8b2e=KX=kwiboo.se=jonas@fe-bounces.kwiboo.se DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kwiboo.se; h=Content-Transfer-Encoding: MIME-Version: References: In-Reply-To: Message-ID: Date: Subject: Cc: To: From; q=dns/txt; s=fe-e1b5cab7be; t=1710629851; bh=888c41V02Br7uNx/L25uHDKX2NByprdGw3F+Cm4L2ao=; b=u4+ixFDQB0vwLRZ75/ds+8pRtczc7xS6zrpy7X+WheYQ79HRWuVM7JbhSp1I99/LE1irN0GCz rDDvu4vOtwZddfI/SVak1zeNfvUitooV8iT4HTnQ+hMvZnFGCVZP14pNsjuDFXgJNY9xx4XSnsY JuU1hUhb5oOuynhD5Vqp4BsO04wYZnH74VHZ3WEqbhOguSpQP98EVsknIyydSgw+t7p9GU/s5+J BYjo+XuYPVHuDGNFXKDt/5Fne34c1y4mGmbIu4enU/D80wVjTx/PkH7QeSMY/Tbz8hGWQWQOIwX 8D1LNhspEfx0Ti+j/KtQe/6aiq1dreVX30cbOfd0JJgQ== From: Jonas Karlman To: Kever Yang , Simon Glass , Philipp Tomsich , Tom Rini Cc: Andy Yan , Akash Gajjar , u-boot@lists.denx.de, Jonas Karlman Subject: [PATCH 09/13] phy: rockchip-inno-usb2: Add support for RK3308 Date: Sat, 16 Mar 2024 22:56:35 +0000 Message-ID: <20240316225655.3244348-10-jonas@kwiboo.se> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240316225655.3244348-1-jonas@kwiboo.se> References: <20240316225655.3244348-1-jonas@kwiboo.se> MIME-Version: 1.0 X-Report-Abuse-To: abuse@forwardemail.net X-Report-Abuse: abuse@forwardemail.net X-Complaints-To: abuse@forwardemail.net X-ForwardEmail-Version: 0.4.40 X-ForwardEmail-Sender: rfc822; jonas@kwiboo.se, smtp.forwardemail.net, 149.28.215.223 X-ForwardEmail-ID: 65f623db0957eaab7babfd1d X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Add clkout_ctl and phy_sus regs to support USB2PHY for RK3308. Based on linux commit 31f840e7ff3e ("phy: phy-rockchip-inno-usb2: add support for RK3308 USB phy"). Signed-off-by: Jonas Karlman --- drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c index d392aed2d4de..43f6e020a6a0 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c @@ -329,6 +329,22 @@ bind_fail: return ret; } +static const struct rockchip_usb2phy_cfg rk3308_phy_cfgs[] = { + { + .reg = 0x100, + .clkout_ctl = { 0x0108, 4, 4, 1, 0 }, + .port_cfgs = { + [USB2PHY_PORT_OTG] = { + .phy_sus = { 0x0100, 1, 0, 2, 1 }, + }, + [USB2PHY_PORT_HOST] = { + .phy_sus = { 0x0104, 1, 0, 2, 1 }, + } + }, + }, + { /* sentinel */ } +}; + static const struct rockchip_usb2phy_cfg rk3328_usb2phy_cfgs[] = { { .reg = 0x100, @@ -442,6 +458,10 @@ static const struct rockchip_usb2phy_cfg rk3588_phy_cfgs[] = { }; static const struct udevice_id rockchip_usb2phy_ids[] = { + { + .compatible = "rockchip,rk3308-usb2phy", + .data = (ulong)&rk3308_phy_cfgs, + }, { .compatible = "rockchip,rk3328-usb2phy", .data = (ulong)&rk3328_usb2phy_cfgs, From patchwork Sat Mar 16 22:56:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonas Karlman X-Patchwork-Id: 1912840 X-Patchwork-Delegate: ykai007@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=kwiboo.se header.i=@kwiboo.se header.a=rsa-sha256 header.s=fe-e1b5cab7be header.b=keRO9Y1E; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4TxxQ14JfWz23sC for ; Sun, 17 Mar 2024 09:59:21 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id D4FC888091; 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Sat, 16 Mar 2024 23:57:50 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kwiboo.se Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=SRS0=8b2e=KX=kwiboo.se=jonas@fe-bounces.kwiboo.se DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kwiboo.se; h=Content-Transfer-Encoding: MIME-Version: References: In-Reply-To: Message-ID: Date: Subject: Cc: To: From; q=dns/txt; s=fe-e1b5cab7be; t=1710629855; bh=fYECuAaKOb44j/qhESOjKS9ISz/Fogd3x/aHhXkDF2o=; b=keRO9Y1EL5lr+z/7J8oFGSPuJY2CHN5nh9zqiwuymSKNv3SM4MQKBSTSNXC/gmUPzsXXkWaVi juNsAHA+ABNRMx6p3szynHqLzN6HlVJBnAmnlQDrjAlL7BpfJN9xgW9gkOLSfccZSsuGqcGuHjI +VHgrJYx8lgWWdKWJclErPIl5rrgftM4TGQX6Rz894a6xs0gWh2cR8KkrupTQ+Qu/84Rnjx6Pxk B84Vm3fnXDcdcMC1YqgQY7CDEdVwt+zz0TGn5pdwtQvNXu3FPvdjqAt3RjNkarB9Z+q5DDBeHw7 soJGMnu6yCf92Rd/oGP8lRdMrk4ahrXbvxPeS7kFzp6w== From: Jonas Karlman To: Kever Yang , Simon Glass , Philipp Tomsich , Tom Rini , Andy Yan , Akash Gajjar , Jonas Karlman , Joe Hershberger , Ramon Fried Cc: u-boot@lists.denx.de Subject: [PATCH 10/13] rockchip: rk3308: Sync device tree from linux v6.8 Date: Sat, 16 Mar 2024 22:56:36 +0000 Message-ID: <20240316225655.3244348-11-jonas@kwiboo.se> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240316225655.3244348-1-jonas@kwiboo.se> References: <20240316225655.3244348-1-jonas@kwiboo.se> MIME-Version: 1.0 X-Report-Abuse-To: abuse@forwardemail.net X-Report-Abuse: abuse@forwardemail.net X-Complaints-To: abuse@forwardemail.net X-ForwardEmail-Version: 0.4.40 X-ForwardEmail-Sender: rfc822; jonas@kwiboo.se, smtp.forwardemail.net, 149.28.215.223 X-ForwardEmail-ID: 65f623df0957eaab7babfd2f X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Sync device tree from linux v6.8 and rename the rockchip,rk3308-mac compatible in gmac_rockchip driver to match upstream linux. Also move rk3308-roc-cc gmac node to u-boot.dtsi to not break features not enabled in upstream device tree. Signed-off-by: Jonas Karlman --- arch/arm/dts/rk3308-evb.dts | 104 +- arch/arm/dts/rk3308-roc-cc-u-boot.dtsi | 19 + arch/arm/dts/rk3308-roc-cc.dts | 83 +- arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi | 4 + arch/arm/dts/rk3308-rock-pi-s.dts | 100 +- arch/arm/dts/rk3308-u-boot.dtsi | 14 +- arch/arm/dts/rk3308.dtsi | 1205 +++++++++++---------- drivers/net/gmac_rockchip.c | 2 +- 8 files changed, 837 insertions(+), 694 deletions(-) diff --git a/arch/arm/dts/rk3308-evb.dts b/arch/arm/dts/rk3308-evb.dts index 124a24086684..184b84fdde07 100644 --- a/arch/arm/dts/rk3308-evb.dts +++ b/arch/arm/dts/rk3308-evb.dts @@ -23,7 +23,7 @@ poll-interval = <100>; keyup-threshold-microvolt = <1800000>; - func-key { + button-func { linux,code = ; label = "function"; press-threshold-microvolt = <18000>; @@ -37,31 +37,31 @@ poll-interval = <100>; keyup-threshold-microvolt = <1800000>; - esc-key { + button-esc { linux,code = ; label = "micmute"; press-threshold-microvolt = <1130000>; }; - home-key { + button-home { linux,code = ; label = "mode"; press-threshold-microvolt = <901000>; }; - menu-key { + button-menu { linux,code = ; label = "play"; press-threshold-microvolt = <624000>; }; - vol-down-key { + button-down { linux,code = ; label = "volume down"; press-threshold-microvolt = <300000>; }; - vol-up-key { + button-up { linux,code = ; label = "volume up"; press-threshold-microvolt = <18000>; @@ -75,115 +75,115 @@ pinctrl-names = "default"; pinctrl-0 = <&pwr_key>; - power { + key-power { gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; linux,code = ; label = "GPIO Key Power"; - wakeup-source; debounce-interval = <100>; + wakeup-source; }; }; vcc12v_dcin: vcc12v-dcin { compatible = "regulator-fixed"; regulator-name = "vcc12v_dcin"; - regulator-always-on; - regulator-boot-on; regulator-min-microvolt = <12000000>; regulator-max-microvolt = <12000000>; + regulator-always-on; + regulator-boot-on; }; vcc5v0_sys: vcc5v0-sys { compatible = "regulator-fixed"; regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vdd_core: vdd-core { - compatible = "pwm-regulator"; - pwms = <&pwm0 0 5000 1>; - regulator-name = "vdd_core"; - regulator-min-microvolt = <827000>; - regulator-max-microvolt = <1340000>; regulator-always-on; regulator-boot-on; - regulator-settling-time-up-us = <250>; - pwm-supply = <&vcc5v0_sys>; - }; - - vdd_log: vdd-log { - compatible = "regulator-fixed"; - regulator-name = "vdd_log"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - vin-supply = <&vcc5v0_sys>; - }; - - vdd_1v0: vdd-1v0 { - compatible = "regulator-fixed"; - regulator-name = "vdd_1v0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - vin-supply = <&vcc5v0_sys>; + vin-supply = <&vcc12v_dcin>; }; vccio_sdio: vcc_1v8: vcc-1v8 { compatible = "regulator-fixed"; regulator-name = "vcc_1v8"; - regulator-always-on; - regulator-boot-on; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; vin-supply = <&vcc_io>; }; vcc_ddr: vcc-ddr { compatible = "regulator-fixed"; regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; regulator-min-microvolt = <1500000>; regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; vin-supply = <&vcc5v0_sys>; }; vcc_io: vcc-io { compatible = "regulator-fixed"; regulator-name = "vcc_io"; - regulator-always-on; - regulator-boot-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; vin-supply = <&vcc5v0_sys>; }; vccio_flash: vccio-flash { compatible = "regulator-fixed"; regulator-name = "vccio_flash"; - regulator-always-on; - regulator-boot-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; vin-supply = <&vcc_io>; }; vcc5v0_host: vcc5v0-host { compatible = "regulator-fixed"; - enable-active-high; gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + enable-active-high; pinctrl-names = "default"; pinctrl-0 = <&usb_drv>; regulator-name = "vbus_host"; vin-supply = <&vcc5v0_sys>; }; + + vdd_core: vdd-core { + compatible = "pwm-regulator"; + pwms = <&pwm0 0 5000 1>; + regulator-name = "vdd_core"; + regulator-min-microvolt = <827000>; + regulator-max-microvolt = <1340000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + pwm-supply = <&vcc5v0_sys>; + }; + + vdd_log: vdd-log { + compatible = "regulator-fixed"; + regulator-name = "vdd_log"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + }; + + vdd_1v0: vdd-1v0 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + }; }; &cpu0 { diff --git a/arch/arm/dts/rk3308-roc-cc-u-boot.dtsi b/arch/arm/dts/rk3308-roc-cc-u-boot.dtsi index d823ac00c771..3e01e7af6113 100644 --- a/arch/arm/dts/rk3308-roc-cc-u-boot.dtsi +++ b/arch/arm/dts/rk3308-roc-cc-u-boot.dtsi @@ -4,6 +4,21 @@ */ #include "rk3308-u-boot.dtsi" +/ { + aliases { + ethernet0 = &gmac; + }; +}; + +&gmac { + assigned-clocks = <&cru SCLK_MAC>; + assigned-clock-parents = <&mac_clkin>; + clock_in_out = "input"; + pinctrl-names = "default"; + pinctrl-0 = <&rmiim1_pins &macm1_refclk>; + status = "okay"; +}; + &gpio4 { bootph-pre-ram; }; @@ -20,3 +35,7 @@ &vcc_sd { bootph-pre-ram; }; + +&vdd_core { + regulator-init-microvolt = <1015000>; +}; diff --git a/arch/arm/dts/rk3308-roc-cc.dts b/arch/arm/dts/rk3308-roc-cc.dts index b4a54a852ce2..9232357f4fec 100644 --- a/arch/arm/dts/rk3308-roc-cc.dts +++ b/arch/arm/dts/rk3308-roc-cc.dts @@ -9,11 +9,17 @@ / { model = "Firefly ROC-RK3308-CC board"; compatible = "firefly,roc-rk3308-cc", "rockchip,rk3308"; + + aliases { + mmc0 = &sdmmc; + mmc1 = &emmc; + }; + chosen { stdout-path = "serial2:1500000n8"; }; - ir_rx { + ir-receiver { compatible = "gpio-ir-receiver"; gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; @@ -27,14 +33,15 @@ leds { compatible = "gpio-leds"; - power { + + power_led: led-0 { label = "firefly:red:power"; linux,default-trigger = "ir-power-click"; default-state = "on"; gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; }; - user { + user_led: led-1 { label = "firefly:blue:user"; linux,default-trigger = "ir-user-click"; default-state = "off"; @@ -45,10 +52,10 @@ typec_vcc5v: typec-vcc5v { compatible = "regulator-fixed"; regulator-name = "typec_vcc5v"; - regulator-always-on; - regulator-boot-on; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; }; vcc5v0_sys: vcc5v0-sys { @@ -61,29 +68,6 @@ vin-supply = <&typec_vcc5v>; }; - vdd_core: vdd-core { - compatible = "pwm-regulator"; - pwms = <&pwm0 0 5000 1>; - regulator-name = "vdd_core"; - regulator-min-microvolt = <827000>; - regulator-max-microvolt = <1340000>; - regulator-init-microvolt = <1015000>; - regulator-always-on; - regulator-boot-on; - regulator-settling-time-up-us = <250>; - pwm-supply = <&vcc5v0_sys>; - }; - - vdd_log: vdd-log { - compatible = "regulator-fixed"; - regulator-name = "vdd_log"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - vin-supply = <&vcc5v0_sys>; - }; - vcc_io: vcc-io { compatible = "regulator-fixed"; regulator-name = "vcc_io"; @@ -100,8 +84,8 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_HIGH>; - states = <1800000 0x0 - 3300000 0x1>; + states = <1800000 0x0>, + <3300000 0x1>; vin-supply = <&vcc5v0_sys>; }; @@ -113,9 +97,30 @@ regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; - vim-supply = <&vcc_io>; + vin-supply = <&vcc_io>; + }; + + vdd_core: vdd-core { + compatible = "pwm-regulator"; + pwms = <&pwm0 0 5000 1>; + regulator-name = "vdd_core"; + regulator-min-microvolt = <827000>; + regulator-max-microvolt = <1340000>; + regulator-settling-time-up-us = <250>; + regulator-always-on; + regulator-boot-on; + pwm-supply = <&vcc5v0_sys>; }; + vdd_log: vdd-log { + compatible = "regulator-fixed"; + regulator-name = "vdd_log"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + }; }; &cpu0 { @@ -123,12 +128,9 @@ }; &emmc { - bus-width = <8>; cap-mmc-highspeed; - supports-emmc; - disable-wp; + mmc-hs200-1_8v; non-removable; - num-slots = <1>; status = "okay"; }; @@ -143,15 +145,6 @@ }; }; -&mac { - assigned-clocks = <&cru SCLK_MAC>; - assigned-clock-parents = <&mac_clkin>; - clock_in_out = "input"; - pinctrl-names = "default"; - pinctrl-0 = <&rmiim1_pins &macm1_refclk>; - status = "okay"; -}; - &pwm5 { status = "okay"; pinctrl-names = "active"; @@ -181,10 +174,8 @@ }; &sdmmc { - bus-width = <4>; cap-mmc-highspeed; cap-sd-highspeed; - supports-sd; card-detect-delay = <300>; sd-uhs-sdr25; sd-uhs-sdr50; diff --git a/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi b/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi index c92e1fbf1f53..45ab5c7781e5 100644 --- a/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi +++ b/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi @@ -30,3 +30,7 @@ &uart0_xfer { bootph-all; }; + +&vdd_core { + regulator-init-microvolt = <1015000>; +}; diff --git a/arch/arm/dts/rk3308-rock-pi-s.dts b/arch/arm/dts/rk3308-rock-pi-s.dts index b5a8691b3fe9..b47fe02c33fb 100644 --- a/arch/arm/dts/rk3308-rock-pi-s.dts +++ b/arch/arm/dts/rk3308-rock-pi-s.dts @@ -1,12 +1,10 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd - * Copyright (C) 2023 Akash Gajjar - * Copyright (c) 2023 Jagan Teki + * Copyright (c) 2019 Akash Gajjar + * Copyright (c) 2019 Jagan Teki */ /dts-v1/; -#include #include "rk3308.dtsi" / { @@ -14,7 +12,7 @@ compatible = "radxa,rockpis", "rockchip,rk3308"; aliases { - ethernet0 = &mac; + ethernet0 = &gmac; mmc0 = &emmc; mmc1 = &sdmmc; }; @@ -107,7 +105,6 @@ regulator-name = "vdd_core"; regulator-min-microvolt = <827000>; regulator-max-microvolt = <1340000>; - regulator-init-microvolt = <1015000>; regulator-settling-time-up-us = <250>; regulator-always-on; regulator-boot-on; @@ -137,7 +134,7 @@ status = "okay"; }; -&mac { +&gmac { clock_in_out = "output"; phy-supply = <&vcc_io>; snps,reset-gpio = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; @@ -146,6 +143,68 @@ status = "okay"; }; +&gpio0 { + gpio-line-names = + /* GPIO0_A0 - A7 */ + "", "", "", "", "", "", "", "", + /* GPIO0_B0 - B7 */ + "", "", "", "header1-pin3 [GPIO0_B3]", + "header1-pin5 [GPIO0_B4]", "", "", + "header1-pin11 [GPIO0_B7]", + /* GPIO0_C0 - C7 */ + "header1-pin13 [GPIO0_C0]", + "header1-pin15 [GPIO0_C1]", "", "", "", + "", "", "", + /* GPIO0_D0 - D7 */ + "", "", "", "", "", "", "", ""; +}; + +&gpio1 { + gpio-line-names = + /* GPIO1_A0 - A7 */ + "", "", "", "", "", "", "", "", + /* GPIO1_B0 - B7 */ + "", "", "", "", "", "", "", "", + /* GPIO1_C0 - C7 */ + "", "", "", "", "", "", "header1-pin21 [GPIO1_C6]", + "header1-pin19 [GPIO1_C7]", + /* GPIO1_D0 - D7 */ + "header1-pin23 [GPIO1_D0]", "header1-pin24 [GPIO1_D1]", + "", "", "", "", "", ""; +}; + +&gpio2 { + gpio-line-names = + /* GPIO2_A0 - A7 */ + "header1-pin10 [GPIO2_A0]", "header1-pin8 [GPIO2_A1]", + "", "", + "header1-pin7 [GPIO2_A4]", "header1-pin12 [GPIO2_A5]", + "header2-pin46 [GPIO2_A6]", "header1-pin22 [GPIO1_A7]", + /* GPIO2_B0 - B7 */ + "header2-pin45 [GPIO2_B0]", "header1-pin18 [GPIO2_B1]", + "header1-pin16 [GPIO2_B2]", "header2-pin44 [GPIO2_B3]", + "header2-pin43 [GPIO2_B4]", "header2-pin28 [GPIO2_B5]", + "header2-pin30 [GPIO2_B6]", "header2-pin32 [GPIO2_B7]", + /* GPIO2_C0 - C7 */ + "header2-pin34 [GPIO2_C0]", "", "", "", "", "", "", "", + /* GPIO2_D0 - D7 */ + "", "", "", "", "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + /* GPIO3_A0 - A7 */ + "", "", "", "", "", "", "", "", + /* GPIO3_B0 - B7 */ + "", "", "header2-pin42 [GPIO3_B2]", + "header2-pin41 [GPIO3_B3]", "header2-pin40 [GPIO3_B4]", + "header2-pin39 [GPIO3_B5]", "", "", + /* GPIO3_C0 - C7 */ + "", "", "", "", "", "", "", "", + /* GPIO3_D0 - D7 */ + "", "", "", "", "", "", "", ""; +}; + &i2c1 { status = "okay"; }; @@ -209,6 +268,20 @@ status = "okay"; }; +&u2phy { + status = "okay"; + + u2phy_host: host-port { + phy-supply = <&vcc5v0_otg>; + status = "okay"; + }; + + u2phy_otg: otg-port { + phy-supply = <&vcc5v0_otg>; + status = "okay"; + }; +}; + &uart0 { status = "okay"; }; @@ -223,6 +296,19 @@ }; }; +&usb_host_ehci { + status = "okay"; +}; + +&usb_host_ohci { + status = "okay"; +}; + +&usb20_otg { + dr_mode = "peripheral"; + status = "okay"; +}; + &wdt { status = "okay"; }; diff --git a/arch/arm/dts/rk3308-u-boot.dtsi b/arch/arm/dts/rk3308-u-boot.dtsi index ede07e1783ff..ea0839240a93 100644 --- a/arch/arm/dts/rk3308-u-boot.dtsi +++ b/arch/arm/dts/rk3308-u-boot.dtsi @@ -15,6 +15,12 @@ u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc; }; + dmc: dmc@ff010000 { + bootph-all; + compatible = "rockchip,rk3308-dmc"; + reg = <0x0 0xff010000 0x0 0x10000>; + }; + otp: nvmem@ff210000 { compatible = "rockchip,rk3308-otp"; reg = <0x0 0xff210000 0x0 0x4000>; @@ -36,10 +42,6 @@ bootph-all; }; -&dmc { - bootph-all; -}; - &emmc { bootph-pre-ram; bootph-some-ram; @@ -119,3 +121,7 @@ &sdmmc_det { bootph-pre-ram; }; + +&xin24m { + bootph-all; +}; diff --git a/arch/arm/dts/rk3308.dtsi b/arch/arm/dts/rk3308.dtsi index 9a152a8a9072..cfc0a87b5195 100644 --- a/arch/arm/dts/rk3308.dtsi +++ b/arch/arm/dts/rk3308.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd * @@ -9,6 +9,7 @@ #include #include #include +#include #include / { @@ -19,6 +20,11 @@ #size-cells = <2>; aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; i2c0 = &i2c0; i2c1 = &i2c1; i2c2 = &i2c2; @@ -39,7 +45,7 @@ cpu0: cpu@0 { device_type = "cpu"; - compatible = "arm,cortex-a35", "arm,armv8"; + compatible = "arm,cortex-a35"; reg = <0x0 0x0>; enable-method = "psci"; clocks = <&cru ARMCLK>; @@ -52,7 +58,7 @@ cpu1: cpu@1 { device_type = "cpu"; - compatible = "arm,cortex-a35", "arm,armv8"; + compatible = "arm,cortex-a35"; reg = <0x0 0x1>; enable-method = "psci"; operating-points-v2 = <&cpu0_opp_table>; @@ -62,7 +68,7 @@ cpu2: cpu@2 { device_type = "cpu"; - compatible = "arm,cortex-a35", "arm,armv8"; + compatible = "arm,cortex-a35"; reg = <0x0 0x2>; enable-method = "psci"; operating-points-v2 = <&cpu0_opp_table>; @@ -72,7 +78,7 @@ cpu3: cpu@3 { device_type = "cpu"; - compatible = "arm,cortex-a35", "arm,armv8"; + compatible = "arm,cortex-a35"; reg = <0x0 0x3>; enable-method = "psci"; operating-points-v2 = <&cpu0_opp_table>; @@ -95,10 +101,12 @@ l2: l2-cache { compatible = "cache"; + cache-level = <2>; + cache-unified; }; }; - cpu0_opp_table: cpu0-opp-table { + cpu0_opp_table: opp-table-0 { compatible = "operating-points-v2"; opp-shared; @@ -126,7 +134,7 @@ }; arm-pmu { - compatible = "arm,cortex-a53-pmu"; + compatible = "arm,cortex-a35-pmu"; interrupts = , , , @@ -163,12 +171,53 @@ grf: grf@ff000000 { compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd"; - reg = <0x0 0xff000000 0x0 0x10000>; + reg = <0x0 0xff000000 0x0 0x08000>; + + reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x500>; + mode-bootloader = ; + mode-loader = ; + mode-normal = ; + mode-recovery = ; + mode-fastboot = ; + }; }; - dmc: dmc@0xff010000 { - compatible = "rockchip,rk3308-dmc"; - reg = <0x0 0xff010000 0x0 0x10000>; + usb2phy_grf: syscon@ff008000 { + compatible = "rockchip,rk3308-usb2phy-grf", "syscon", "simple-mfd"; + reg = <0x0 0xff008000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy: usb2phy@100 { + compatible = "rockchip,rk3308-usb2phy"; + reg = <0x100 0x10>; + assigned-clocks = <&cru USB480M>; + assigned-clock-parents = <&u2phy>; + clocks = <&cru SCLK_USBPHY_REF>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy"; + #clock-cells = <0>; + status = "disabled"; + + u2phy_otg: otg-port { + interrupts = , + , + ; + interrupt-names = "otg-bvalid", "otg-id", + "linestate"; + #phy-cells = <0>; + status = "disabled"; + }; + + u2phy_host: host-port { + interrupts = ; + interrupt-names = "linestate"; + #phy-cells = <0>; + status = "disabled"; + }; + }; }; detect_grf: syscon@ff00b000 { @@ -183,7 +232,6 @@ reg = <0x0 0xff00c000 0x0 0x1000>; #address-cells = <1>; #size-cells = <1>; - }; i2c0: i2c@ff040000 { @@ -239,7 +287,7 @@ }; wdt: watchdog@ff080000 { - compatible = "snps,dw-wdt"; + compatible = "rockchip,rk3308-wdt", "snps,dw-wdt"; reg = <0x0 0xff080000 0x0 0x100>; clocks = <&cru PCLK_WDT>; interrupts = ; @@ -321,9 +369,8 @@ clock-names = "spiclk", "apb_pclk"; dmas = <&dmac0 0>, <&dmac0 1>; dma-names = "tx", "rx"; - pinctrl-names = "default", "high_speed"; + pinctrl-names = "default"; pinctrl-0 = <&spi0_clk &spi0_csn0 &spi0_miso &spi0_mosi>; - pinctrl-1 = <&spi0_clk_hs &spi0_csn0 &spi0_miso_hs &spi0_mosi_hs>; status = "disabled"; }; @@ -337,9 +384,8 @@ clock-names = "spiclk", "apb_pclk"; dmas = <&dmac0 2>, <&dmac0 3>; dma-names = "tx", "rx"; - pinctrl-names = "default", "high_speed"; + pinctrl-names = "default"; pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_miso &spi1_mosi>; - pinctrl-1 = <&spi1_clk_hs &spi1_csn0 &spi1_miso_hs &spi1_mosi_hs>; status = "disabled"; }; @@ -353,141 +399,140 @@ clock-names = "spiclk", "apb_pclk"; dmas = <&dmac1 16>, <&dmac1 17>; dma-names = "tx", "rx"; - pinctrl-names = "default", "high_speed"; + pinctrl-names = "default"; pinctrl-0 = <&spi2_clk &spi2_csn0 &spi2_miso &spi2_mosi>; - pinctrl-1 = <&spi2_clk_hs &spi2_csn0 &spi2_miso_hs &spi2_mosi_hs>; status = "disabled"; }; pwm8: pwm@ff160000 { compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; reg = <0x0 0xff160000 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm8_pin>; clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; clock-names = "pwm", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm8_pin>; + #pwm-cells = <3>; status = "disabled"; }; pwm9: pwm@ff160010 { compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; reg = <0x0 0xff160010 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm9_pin>; clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; clock-names = "pwm", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm9_pin>; + #pwm-cells = <3>; status = "disabled"; }; pwm10: pwm@ff160020 { compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; reg = <0x0 0xff160020 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm10_pin>; clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; clock-names = "pwm", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm10_pin>; + #pwm-cells = <3>; status = "disabled"; }; pwm11: pwm@ff160030 { compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; reg = <0x0 0xff160030 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm11_pin>; clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; clock-names = "pwm", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm11_pin>; + #pwm-cells = <3>; status = "disabled"; }; pwm4: pwm@ff170000 { compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; reg = <0x0 0xff170000 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm4_pin>; clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; clock-names = "pwm", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm4_pin>; + #pwm-cells = <3>; status = "disabled"; }; pwm5: pwm@ff170010 { compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; reg = <0x0 0xff170010 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm5_pin>; clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; clock-names = "pwm", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm5_pin>; + #pwm-cells = <3>; status = "disabled"; }; pwm6: pwm@ff170020 { compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; reg = <0x0 0xff170020 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm6_pin>; clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; clock-names = "pwm", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm6_pin>; + #pwm-cells = <3>; status = "disabled"; }; pwm7: pwm@ff170030 { compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; reg = <0x0 0xff170030 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm7_pin>; clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; clock-names = "pwm", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm7_pin>; + #pwm-cells = <3>; status = "disabled"; }; pwm0: pwm@ff180000 { compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; reg = <0x0 0xff180000 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; clock-names = "pwm", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pin>; + #pwm-cells = <3>; status = "disabled"; }; pwm1: pwm@ff180010 { compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; reg = <0x0 0xff180010 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm1_pin>; clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; clock-names = "pwm", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm1_pin>; + #pwm-cells = <3>; status = "disabled"; }; pwm2: pwm@ff180020 { compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; reg = <0x0 0xff180020 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_pin>; clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; clock-names = "pwm", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm2_pin>; + #pwm-cells = <3>; status = "disabled"; }; pwm3: pwm@ff180030 { compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; reg = <0x0 0xff180030 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_pin>; clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; clock-names = "pwm", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_pin>; + #pwm-cells = <3>; status = "disabled"; }; @@ -503,41 +548,34 @@ compatible = "rockchip,rk3308-saradc", "rockchip,rk3399-saradc"; reg = <0x0 0xff1e0000 0x0 0x100>; interrupts = ; - #io-channel-cells = <1>; clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; clock-names = "saradc", "apb_pclk"; + #io-channel-cells = <1>; resets = <&cru SRST_SARADC_P>; reset-names = "saradc-apb"; status = "disabled"; }; - amba { - compatible = "arm,amba-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; + dmac0: dma-controller@ff2c0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xff2c0000 0x0 0x4000>; + interrupts = , + ; + arm,pl330-periph-burst; + clocks = <&cru ACLK_DMAC0>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; - dmac0: dma-controller@ff2c0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xff2c0000 0x0 0x4000>; - interrupts = , - ; - #dma-cells = <1>; - clocks = <&cru ACLK_DMAC0>; - clock-names = "apb_pclk"; - peripherals-req-type-burst; - }; - - dmac1: dma-controller@ff2d0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xff2d0000 0x0 0x4000>; - interrupts = , - ; - #dma-cells = <1>; - clocks = <&cru ACLK_DMAC1>; - clock-names = "apb_pclk"; - peripherals-req-type-burst; - }; + dmac1: dma-controller@ff2d0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xff2d0000 0x0 0x4000>; + interrupts = , + ; + arm,pl330-periph-burst; + clocks = <&cru ACLK_DMAC1>; + clock-names = "apb_pclk"; + #dma-cells = <1>; }; i2s_2ch_0: i2s@ff350000 { @@ -572,7 +610,7 @@ }; spdif_tx: spdif-tx@ff3a0000 { - compatible = "rockchip,rk3308-spdif", "rockchip,rk3328-spdif"; + compatible = "rockchip,rk3308-spdif", "rockchip,rk3066-spdif"; reg = <0x0 0xff3a0000 0x0 0x1000>; interrupts = ; clocks = <&cru SCLK_SPDIF_TX>, <&cru HCLK_SPDIFTX>; @@ -584,16 +622,52 @@ status = "disabled"; }; + usb20_otg: usb@ff400000 { + compatible = "rockchip,rk3308-usb", "rockchip,rk3066-usb", + "snps,dwc2"; + reg = <0x0 0xff400000 0x0 0x40000>; + interrupts = ; + clocks = <&cru HCLK_OTG>; + clock-names = "otg"; + dr_mode = "otg"; + g-np-tx-fifo-size = <16>; + g-rx-fifo-size = <280>; + g-tx-fifo-size = <256 128 128 64 32 16>; + phys = <&u2phy_otg>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + usb_host_ehci: usb@ff440000 { + compatible = "generic-ehci"; + reg = <0x0 0xff440000 0x0 0x10000>; + interrupts = ; + clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, <&u2phy>; + phys = <&u2phy_host>; + phy-names = "usb"; + status = "disabled"; + }; + + usb_host_ohci: usb@ff450000 { + compatible = "generic-ohci"; + reg = <0x0 0xff450000 0x0 0x10000>; + interrupts = ; + clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, <&u2phy>; + phys = <&u2phy_host>; + phy-names = "usb"; + status = "disabled"; + }; + sdmmc: mmc@ff480000 { compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xff480000 0x0 0x4000>; - max-frequency = <150000000>; + interrupts = ; bus-width = <4>; clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>; - interrupts = ; + max-frequency = <150000000>; pinctrl-names = "default"; pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; status = "disabled"; @@ -602,35 +676,49 @@ emmc: mmc@ff490000 { compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xff490000 0x0 0x4000>; - max-frequency = <150000000>; + interrupts = ; bus-width = <8>; clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>; - interrupts = ; + max-frequency = <150000000>; status = "disabled"; }; sdio: mmc@ff4a0000 { compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xff4a0000 0x0 0x4000>; - max-frequency = <150000000>; + interrupts = ; bus-width = <4>; clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>; - interrupts = ; + max-frequency = <150000000>; pinctrl-names = "default"; pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>; status = "disabled"; }; - mac: ethernet@ff4e0000 { - compatible = "rockchip,rk3308-mac"; + nfc: nand-controller@ff4b0000 { + compatible = "rockchip,rk3308-nfc", + "rockchip,rv1108-nfc"; + reg = <0x0 0xff4b0000 0x0 0x4000>; + interrupts = ; + clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; + clock-names = "ahb", "nfc"; + assigned-clocks = <&cru SCLK_NANDC>; + assigned-clock-rates = <150000000>; + pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0 + &flash_rdn &flash_rdy &flash_wrn>; + pinctrl-names = "default"; + status = "disabled"; + }; + + gmac: ethernet@ff4e0000 { + compatible = "rockchip,rk3308-gmac"; reg = <0x0 0xff4e0000 0x0 0x10000>; - rockchip,grf = <&grf>; interrupts = ; interrupt-names = "macirq"; clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX_TX>, @@ -646,40 +734,57 @@ pinctrl-0 = <&rmii_pins &mac_refclk_12ma>; resets = <&cru SRST_MAC_A>; reset-names = "stmmaceth"; + rockchip,grf = <&grf>; + status = "disabled"; + }; + + sfc: spi@ff4c0000 { + compatible = "rockchip,sfc"; + reg = <0x0 0xff4c0000 0x0 0x4000>; + interrupts = ; + clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; + clock-names = "clk_sfc", "hclk_sfc"; + pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>; + pinctrl-names = "default"; status = "disabled"; }; cru: clock-controller@ff500000 { compatible = "rockchip,rk3308-cru"; reg = <0x0 0xff500000 0x0 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>; + assigned-clocks = <&cru SCLK_RTC32K>; + assigned-clock-rates = <32768>; }; gic: interrupt-controller@ff580000 { compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0xff581000 0x0 0x1000>, <0x0 0xff582000 0x0 0x2000>, <0x0 0xff584000 0x0 0x2000>, <0x0 0xff586000 0x0 0x2000>; interrupts = ; + #interrupt-cells = <3>; + interrupt-controller; + #address-cells = <0>; }; sram: sram@fff80000 { compatible = "mmio-sram"; reg = <0x0 0xfff80000 0x0 0x40000>; + ranges = <0 0x0 0xfff80000 0x40000>; #address-cells = <1>; #size-cells = <1>; - ranges = <0 0x0 0xfff80000 0x40000>; + /* reserved for ddr dvfs and system suspend/resume */ ddr-sram@0 { reg = <0x0 0x8000>; }; + /* reserved for vad audio buffer */ vad_sram: vad-sram@8000 { reg = <0x8000 0x38000>; @@ -692,62 +797,58 @@ #address-cells = <2>; #size-cells = <2>; ranges; - gpio0: gpio0@ff220000 { + + gpio0: gpio@ff220000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff220000 0x0 0x100>; interrupts = ; clocks = <&cru PCLK_GPIO0>; gpio-controller; #gpio-cells = <2>; - interrupt-controller; #interrupt-cells = <2>; }; - gpio1: gpio1@ff230000 { + gpio1: gpio@ff230000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff230000 0x0 0x100>; interrupts = ; clocks = <&cru PCLK_GPIO1>; gpio-controller; #gpio-cells = <2>; - interrupt-controller; #interrupt-cells = <2>; }; - gpio2: gpio2@ff240000 { + gpio2: gpio@ff240000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff240000 0x0 0x100>; interrupts = ; clocks = <&cru PCLK_GPIO2>; gpio-controller; #gpio-cells = <2>; - interrupt-controller; #interrupt-cells = <2>; }; - gpio3: gpio3@ff250000 { + gpio3: gpio@ff250000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff250000 0x0 0x100>; interrupts = ; clocks = <&cru PCLK_GPIO3>; gpio-controller; #gpio-cells = <2>; - interrupt-controller; #interrupt-cells = <2>; }; - gpio4: gpio4@ff260000 { + gpio4: gpio@ff260000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff260000 0x0 0x100>; interrupts = ; clocks = <&cru PCLK_GPIO4>; gpio-controller; #gpio-cells = <2>; - interrupt-controller; #interrupt-cells = <2>; }; @@ -831,127 +932,312 @@ input-enable; }; - i2c0 { - i2c0_xfer: i2c0-xfer { - rockchip,pins = - <1 RK_PD0 2 &pcfg_pull_none_smt>, - <1 RK_PD1 2 &pcfg_pull_none_smt>; - }; - }; - - i2c1 { - i2c1_xfer: i2c1-xfer { + emmc { + emmc_clk: emmc-clk { rockchip,pins = - <0 RK_PB3 1 &pcfg_pull_none_smt>, - <0 RK_PB4 1 &pcfg_pull_none_smt>; + <3 RK_PB1 2 &pcfg_pull_none_8ma>; }; - }; - i2c2 { - i2c2_xfer: i2c2-xfer { + emmc_cmd: emmc-cmd { rockchip,pins = - <2 RK_PA2 3 &pcfg_pull_none_smt>, - <2 RK_PA3 3 &pcfg_pull_none_smt>; + <3 RK_PB0 2 &pcfg_pull_up_8ma>; }; - }; - i2c3-m0 { - i2c3m0_xfer: i2c3m0-xfer { + emmc_pwren: emmc-pwren { rockchip,pins = - <0 RK_PB7 2 &pcfg_pull_none_smt>, - <0 RK_PC0 2 &pcfg_pull_none_smt>; + <3 RK_PB3 2 &pcfg_pull_none>; }; - }; - i2c3-m1 { - i2c3m1_xfer: i2c3m1-xfer { + emmc_rstn: emmc-rstn { rockchip,pins = - <3 RK_PB4 2 &pcfg_pull_none_smt>, - <3 RK_PB5 2 &pcfg_pull_none_smt>; + <3 RK_PB2 2 &pcfg_pull_none>; }; - }; - i2c3-m2 { - i2c3m2_xfer: i2c3m2-xfer { + emmc_bus1: emmc-bus1 { rockchip,pins = - <2 RK_PA1 3 &pcfg_pull_none_smt>, - <2 RK_PA0 3 &pcfg_pull_none_smt>; + <3 RK_PA0 2 &pcfg_pull_up_8ma>; }; - }; - i2s_2ch_0 { - i2s_2ch_0_mclk: i2s-2ch-0-mclk { + emmc_bus4: emmc-bus4 { rockchip,pins = - <4 RK_PB4 1 &pcfg_pull_none>; + <3 RK_PA0 2 &pcfg_pull_up_8ma>, + <3 RK_PA1 2 &pcfg_pull_up_8ma>, + <3 RK_PA2 2 &pcfg_pull_up_8ma>, + <3 RK_PA3 2 &pcfg_pull_up_8ma>; }; - i2s_2ch_0_sclk: i2s-2ch-0-sclk { + emmc_bus8: emmc-bus8 { rockchip,pins = - <4 RK_PB5 1 &pcfg_pull_none>; + <3 RK_PA0 2 &pcfg_pull_up_8ma>, + <3 RK_PA1 2 &pcfg_pull_up_8ma>, + <3 RK_PA2 2 &pcfg_pull_up_8ma>, + <3 RK_PA3 2 &pcfg_pull_up_8ma>, + <3 RK_PA4 2 &pcfg_pull_up_8ma>, + <3 RK_PA5 2 &pcfg_pull_up_8ma>, + <3 RK_PA6 2 &pcfg_pull_up_8ma>, + <3 RK_PA7 2 &pcfg_pull_up_8ma>; }; + }; - i2s_2ch_0_lrck: i2s-2ch-0-lrck { + flash { + flash_csn0: flash-csn0 { rockchip,pins = - <4 RK_PB6 1 &pcfg_pull_none>; + <3 RK_PB5 1 &pcfg_pull_none>; }; - i2s_2ch_0_sdo: i2s-2ch-0-sdo { + flash_rdy: flash-rdy { rockchip,pins = - <4 RK_PB7 1 &pcfg_pull_none>; + <3 RK_PB4 1 &pcfg_pull_none>; }; - i2s_2ch_0_sdi: i2s-2ch-0-sdi { + flash_ale: flash-ale { rockchip,pins = - <4 RK_PC0 1 &pcfg_pull_none>; + <3 RK_PB3 1 &pcfg_pull_none>; }; - }; - i2s_8ch_0 { - i2s_8ch_0_mclk: i2s-8ch-0-mclk { + flash_cle: flash-cle { rockchip,pins = - <2 RK_PA4 1 &pcfg_pull_none>; + <3 RK_PB1 1 &pcfg_pull_none>; }; - i2s_8ch_0_sclktx: i2s-8ch-0-sclktx { + flash_wrn: flash-wrn { rockchip,pins = - <2 RK_PA5 1 &pcfg_pull_none>; + <3 RK_PB0 1 &pcfg_pull_none>; }; - i2s_8ch_0_sclkrx: i2s-8ch-0-sclkrx { + flash_rdn: flash-rdn { rockchip,pins = - <2 RK_PA6 1 &pcfg_pull_none>; + <3 RK_PB2 1 &pcfg_pull_none>; }; - i2s_8ch_0_lrcktx: i2s-8ch-0-lrcktx { + flash_bus8: flash-bus8 { rockchip,pins = - <2 RK_PA7 1 &pcfg_pull_none>; + <3 RK_PA0 1 &pcfg_pull_up_12ma>, + <3 RK_PA1 1 &pcfg_pull_up_12ma>, + <3 RK_PA2 1 &pcfg_pull_up_12ma>, + <3 RK_PA3 1 &pcfg_pull_up_12ma>, + <3 RK_PA4 1 &pcfg_pull_up_12ma>, + <3 RK_PA5 1 &pcfg_pull_up_12ma>, + <3 RK_PA6 1 &pcfg_pull_up_12ma>, + <3 RK_PA7 1 &pcfg_pull_up_12ma>; }; + }; - i2s_8ch_0_lrckrx: i2s-8ch-0-lrckrx { + sfc { + sfc_bus4: sfc-bus4 { rockchip,pins = - <2 RK_PB0 1 &pcfg_pull_none>; + <3 RK_PA0 3 &pcfg_pull_none>, + <3 RK_PA1 3 &pcfg_pull_none>, + <3 RK_PA2 3 &pcfg_pull_none>, + <3 RK_PA3 3 &pcfg_pull_none>; }; - i2s_8ch_0_sdo0: i2s-8ch-0-sdo0 { + sfc_bus2: sfc-bus2 { rockchip,pins = - <2 RK_PB1 1 &pcfg_pull_none>; + <3 RK_PA0 3 &pcfg_pull_none>, + <3 RK_PA1 3 &pcfg_pull_none>; }; - i2s_8ch_0_sdo1: i2s-8ch-0-sdo1 { + sfc_cs0: sfc-cs0 { rockchip,pins = - <2 RK_PB2 1 &pcfg_pull_none>; + <3 RK_PA4 3 &pcfg_pull_none>; }; - i2s_8ch_0_sdo2: i2s-8ch-0-sdo2 { + sfc_clk: sfc-clk { rockchip,pins = - <2 RK_PB3 1 &pcfg_pull_none>; + <3 RK_PA5 3 &pcfg_pull_none>; }; + }; - i2s_8ch_0_sdo3: i2s-8ch-0-sdo3 { + gmac { + rmii_pins: rmii-pins { rockchip,pins = - <2 RK_PB4 1 &pcfg_pull_none>; - }; - + /* mac_txen */ + <1 RK_PC1 3 &pcfg_pull_none_12ma>, + /* mac_txd1 */ + <1 RK_PC3 3 &pcfg_pull_none_12ma>, + /* mac_txd0 */ + <1 RK_PC2 3 &pcfg_pull_none_12ma>, + /* mac_rxd0 */ + <1 RK_PC4 3 &pcfg_pull_none>, + /* mac_rxd1 */ + <1 RK_PC5 3 &pcfg_pull_none>, + /* mac_rxer */ + <1 RK_PB7 3 &pcfg_pull_none>, + /* mac_rxdv */ + <1 RK_PC0 3 &pcfg_pull_none>, + /* mac_mdio */ + <1 RK_PB6 3 &pcfg_pull_none>, + /* mac_mdc */ + <1 RK_PB5 3 &pcfg_pull_none>; + }; + + mac_refclk_12ma: mac-refclk-12ma { + rockchip,pins = + <1 RK_PB4 3 &pcfg_pull_none_12ma>; + }; + + mac_refclk: mac-refclk { + rockchip,pins = + <1 RK_PB4 3 &pcfg_pull_none>; + }; + }; + + gmac-m1 { + rmiim1_pins: rmiim1-pins { + rockchip,pins = + /* mac_txen */ + <4 RK_PB7 2 &pcfg_pull_none_12ma>, + /* mac_txd1 */ + <4 RK_PA5 2 &pcfg_pull_none_12ma>, + /* mac_txd0 */ + <4 RK_PA4 2 &pcfg_pull_none_12ma>, + /* mac_rxd0 */ + <4 RK_PA2 2 &pcfg_pull_none>, + /* mac_rxd1 */ + <4 RK_PA3 2 &pcfg_pull_none>, + /* mac_rxer */ + <4 RK_PA0 2 &pcfg_pull_none>, + /* mac_rxdv */ + <4 RK_PA1 2 &pcfg_pull_none>, + /* mac_mdio */ + <4 RK_PB6 2 &pcfg_pull_none>, + /* mac_mdc */ + <4 RK_PB5 2 &pcfg_pull_none>; + }; + + macm1_refclk_12ma: macm1-refclk-12ma { + rockchip,pins = + <4 RK_PB4 2 &pcfg_pull_none_12ma>; + }; + + macm1_refclk: macm1-refclk { + rockchip,pins = + <4 RK_PB4 2 &pcfg_pull_none>; + }; + }; + + i2c0 { + i2c0_xfer: i2c0-xfer { + rockchip,pins = + <1 RK_PD0 2 &pcfg_pull_none_smt>, + <1 RK_PD1 2 &pcfg_pull_none_smt>; + }; + }; + + i2c1 { + i2c1_xfer: i2c1-xfer { + rockchip,pins = + <0 RK_PB3 1 &pcfg_pull_none_smt>, + <0 RK_PB4 1 &pcfg_pull_none_smt>; + }; + }; + + i2c2 { + i2c2_xfer: i2c2-xfer { + rockchip,pins = + <2 RK_PA2 3 &pcfg_pull_none_smt>, + <2 RK_PA3 3 &pcfg_pull_none_smt>; + }; + }; + + i2c3-m0 { + i2c3m0_xfer: i2c3m0-xfer { + rockchip,pins = + <0 RK_PB7 2 &pcfg_pull_none_smt>, + <0 RK_PC0 2 &pcfg_pull_none_smt>; + }; + }; + + i2c3-m1 { + i2c3m1_xfer: i2c3m1-xfer { + rockchip,pins = + <3 RK_PB4 2 &pcfg_pull_none_smt>, + <3 RK_PB5 2 &pcfg_pull_none_smt>; + }; + }; + + i2c3-m2 { + i2c3m2_xfer: i2c3m2-xfer { + rockchip,pins = + <2 RK_PA1 3 &pcfg_pull_none_smt>, + <2 RK_PA0 3 &pcfg_pull_none_smt>; + }; + }; + + i2s_2ch_0 { + i2s_2ch_0_mclk: i2s-2ch-0-mclk { + rockchip,pins = + <4 RK_PB4 1 &pcfg_pull_none>; + }; + + i2s_2ch_0_sclk: i2s-2ch-0-sclk { + rockchip,pins = + <4 RK_PB5 1 &pcfg_pull_none>; + }; + + i2s_2ch_0_lrck: i2s-2ch-0-lrck { + rockchip,pins = + <4 RK_PB6 1 &pcfg_pull_none>; + }; + + i2s_2ch_0_sdo: i2s-2ch-0-sdo { + rockchip,pins = + <4 RK_PB7 1 &pcfg_pull_none>; + }; + + i2s_2ch_0_sdi: i2s-2ch-0-sdi { + rockchip,pins = + <4 RK_PC0 1 &pcfg_pull_none>; + }; + }; + + i2s_8ch_0 { + i2s_8ch_0_mclk: i2s-8ch-0-mclk { + rockchip,pins = + <2 RK_PA4 1 &pcfg_pull_none>; + }; + + i2s_8ch_0_sclktx: i2s-8ch-0-sclktx { + rockchip,pins = + <2 RK_PA5 1 &pcfg_pull_none>; + }; + + i2s_8ch_0_sclkrx: i2s-8ch-0-sclkrx { + rockchip,pins = + <2 RK_PA6 1 &pcfg_pull_none>; + }; + + i2s_8ch_0_lrcktx: i2s-8ch-0-lrcktx { + rockchip,pins = + <2 RK_PA7 1 &pcfg_pull_none>; + }; + + i2s_8ch_0_lrckrx: i2s-8ch-0-lrckrx { + rockchip,pins = + <2 RK_PB0 1 &pcfg_pull_none>; + }; + + i2s_8ch_0_sdo0: i2s-8ch-0-sdo0 { + rockchip,pins = + <2 RK_PB1 1 &pcfg_pull_none>; + }; + + i2s_8ch_0_sdo1: i2s-8ch-0-sdo1 { + rockchip,pins = + <2 RK_PB2 1 &pcfg_pull_none>; + }; + + i2s_8ch_0_sdo2: i2s-8ch-0-sdo2 { + rockchip,pins = + <2 RK_PB3 1 &pcfg_pull_none>; + }; + + i2s_8ch_0_sdo3: i2s-8ch-0-sdo3 { + rockchip,pins = + <2 RK_PB4 1 &pcfg_pull_none>; + }; + i2s_8ch_0_sdi0: i2s-8ch-0-sdi0 { rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>; @@ -1163,281 +1449,154 @@ }; }; - spdif_in { - spdif_in: spdif-in { + pwm0 { + pwm0_pin: pwm0-pin { rockchip,pins = - <0 RK_PC2 1 &pcfg_pull_none>; + <0 RK_PB5 1 &pcfg_pull_none>; }; - }; - spdif_out { - spdif_out: spdif-out { + pwm0_pin_pull_down: pwm0-pin-pull-down { rockchip,pins = - <0 RK_PC1 1 &pcfg_pull_none>; + <0 RK_PB5 1 &pcfg_pull_down>; }; }; - tsadc { - tsadc_otp_gpio: tsadc-otp-gpio { + pwm1 { + pwm1_pin: pwm1-pin { rockchip,pins = - <0 RK_PB2 0 &pcfg_pull_none>; + <0 RK_PB6 1 &pcfg_pull_none>; }; - tsadc_otp_out: tsadc-otp-out { + pwm1_pin_pull_down: pwm1-pin-pull-down { rockchip,pins = - <0 RK_PB2 1 &pcfg_pull_none>; + <0 RK_PB6 1 &pcfg_pull_down>; }; }; - uart0 { - uart0_xfer: uart0-xfer { + pwm2 { + pwm2_pin: pwm2-pin { rockchip,pins = - <2 RK_PA1 1 &pcfg_pull_up>, - <2 RK_PA0 1 &pcfg_pull_up>; + <0 RK_PB7 1 &pcfg_pull_none>; }; - uart0_cts: uart0-cts { + pwm2_pin_pull_down: pwm2-pin-pull-down { rockchip,pins = - <2 RK_PA2 1 &pcfg_pull_none>; + <0 RK_PB7 1 &pcfg_pull_down>; }; + }; - uart0_rts: uart0-rts { + pwm3 { + pwm3_pin: pwm3-pin { rockchip,pins = - <2 RK_PA3 1 &pcfg_pull_none>; + <0 RK_PC0 1 &pcfg_pull_none>; }; - uart0_rts_gpio: uart0-rts-gpio { + pwm3_pin_pull_down: pwm3-pin-pull-down { rockchip,pins = - <2 RK_PA3 0 &pcfg_pull_none>; + <0 RK_PC0 1 &pcfg_pull_down>; }; }; - uart1 { - uart1_xfer: uart1-xfer { + pwm4 { + pwm4_pin: pwm4-pin { rockchip,pins = - <1 RK_PD1 1 &pcfg_pull_up>, - <1 RK_PD0 1 &pcfg_pull_up>; + <0 RK_PA1 2 &pcfg_pull_none>; }; - uart1_cts: uart1-cts { + pwm4_pin_pull_down: pwm4-pin-pull-down { rockchip,pins = - <1 RK_PC6 1 &pcfg_pull_none>; + <0 RK_PA1 2 &pcfg_pull_down>; }; + }; - uart1_rts: uart1-rts { + pwm5 { + pwm5_pin: pwm5-pin { rockchip,pins = - <1 RK_PC7 1 &pcfg_pull_none>; + <0 RK_PC1 2 &pcfg_pull_none>; }; - }; - uart2-m0 { - uart2m0_xfer: uart2m0-xfer { + pwm5_pin_pull_down: pwm5-pin-pull-down { rockchip,pins = - <1 RK_PC7 2 &pcfg_pull_up>, - <1 RK_PC6 2 &pcfg_pull_up>; + <0 RK_PC1 2 &pcfg_pull_down>; }; }; - uart2-m1 { - uart2m1_xfer: uart2m1-xfer { + pwm6 { + pwm6_pin: pwm6-pin { rockchip,pins = - <4 RK_PD3 2 &pcfg_pull_up>, - <4 RK_PD2 2 &pcfg_pull_up>; - }; - }; - - uart3 { - uart3_xfer: uart3-xfer { - rockchip,pins = - <3 RK_PB5 4 &pcfg_pull_up>, - <3 RK_PB4 4 &pcfg_pull_up>; + <0 RK_PC2 2 &pcfg_pull_none>; }; - }; - uart3-m1 { - uart3m1_xfer: uart3m1-xfer { + pwm6_pin_pull_down: pwm6-pin-pull-down { rockchip,pins = - <0 RK_PC2 3 &pcfg_pull_up>, - <0 RK_PC1 3 &pcfg_pull_up>; + <0 RK_PC2 2 &pcfg_pull_down>; }; }; - uart4 { - - uart4_xfer: uart4-xfer { - rockchip,pins = - <4 RK_PB1 1 &pcfg_pull_up>, - <4 RK_PB0 1 &pcfg_pull_up>; - }; - - uart4_cts: uart4-cts { - rockchip,pins = - <4 RK_PA6 1 &pcfg_pull_none>; - - }; - - uart4_rts: uart4-rts { + pwm7 { + pwm7_pin: pwm7-pin { rockchip,pins = - <4 RK_PA7 1 &pcfg_pull_none>; + <2 RK_PB0 2 &pcfg_pull_none>; }; - uart4_rts_gpio: uart4-rts-gpio { + pwm7_pin_pull_down: pwm7-pin-pull-down { rockchip,pins = - <4 RK_PA7 0 &pcfg_pull_none>; + <2 RK_PB0 2 &pcfg_pull_down>; }; }; - spi0 { - spi0_clk: spi0-clk { - rockchip,pins = - <2 RK_PA2 2 &pcfg_pull_up_4ma>; - }; - - spi0_csn0: spi0-csn0 { - rockchip,pins = - <2 RK_PA3 2 &pcfg_pull_up_4ma>; - }; - - spi0_miso: spi0-miso { - rockchip,pins = - <2 RK_PA0 2 &pcfg_pull_up_4ma>; - }; - - spi0_mosi: spi0-mosi { - rockchip,pins = - <2 RK_PA1 2 &pcfg_pull_up_4ma>; - }; - - spi0_clk_hs: spi0-clk-hs { - rockchip,pins = - <2 RK_PA2 2 &pcfg_pull_up_8ma>; - }; - - spi0_miso_hs: spi0-miso-hs { + pwm8 { + pwm8_pin: pwm8-pin { rockchip,pins = - <2 RK_PA0 2 &pcfg_pull_up_8ma>; + <2 RK_PB2 2 &pcfg_pull_none>; }; - spi0_mosi_hs: spi0-mosi-hs { + pwm8_pin_pull_down: pwm8-pin-pull-down { rockchip,pins = - <2 RK_PA1 2 &pcfg_pull_up_8ma>; + <2 RK_PB2 2 &pcfg_pull_down>; }; - }; - spi1 { - spi1_clk: spi1-clk { - rockchip,pins = - <3 RK_PB3 3 &pcfg_pull_up_4ma>; - }; - - spi1_csn0: spi1-csn0 { - rockchip,pins = - <3 RK_PB5 3 &pcfg_pull_up_4ma>; - }; - - spi1_miso: spi1-miso { - rockchip,pins = - <3 RK_PB2 3 &pcfg_pull_up_4ma>; - }; - - spi1_mosi: spi1-mosi { - rockchip,pins = - <3 RK_PB4 3 &pcfg_pull_up_4ma>; - }; - - spi1_clk_hs: spi1-clk-hs { - rockchip,pins = - <3 RK_PB3 3 &pcfg_pull_up_8ma>; - }; - - spi1_miso_hs: spi1-miso-hs { + pwm9 { + pwm9_pin: pwm9-pin { rockchip,pins = - <3 RK_PB2 3 &pcfg_pull_up_8ma>; + <2 RK_PB3 2 &pcfg_pull_none>; }; - spi1_mosi_hs: spi1-mosi-hs { + pwm9_pin_pull_down: pwm9-pin-pull-down { rockchip,pins = - <3 RK_PB4 3 &pcfg_pull_up_8ma>; + <2 RK_PB3 2 &pcfg_pull_down>; }; }; - spi1-m1 { - spi1m1_miso: spi1m1-miso { - rockchip,pins = - <2 RK_PA4 2 &pcfg_pull_up_4ma>; - }; - - spi1m1_mosi: spi1m1-mosi { - rockchip,pins = - <2 RK_PA5 2 &pcfg_pull_up_4ma>; - }; - - spi1m1_clk: spi1m1-clk { - rockchip,pins = - <2 RK_PA7 2 &pcfg_pull_up_4ma>; - }; - - spi1m1_csn0: spi1m1-csn0 { - rockchip,pins = - <2 RK_PB1 2 &pcfg_pull_up_4ma>; - }; - - spi1m1_miso_hs: spi1m1-miso-hs { - rockchip,pins = - <2 RK_PA4 2 &pcfg_pull_up_8ma>; - }; - - spi1m1_mosi_hs: spi1m1-mosi-hs { - rockchip,pins = - <2 RK_PA5 2 &pcfg_pull_up_8ma>; - }; - - spi1m1_clk_hs: spi1m1-clk-hs { + pwm10 { + pwm10_pin: pwm10-pin { rockchip,pins = - <2 RK_PA7 2 &pcfg_pull_up_8ma>; + <2 RK_PB4 2 &pcfg_pull_none>; }; - spi1m1_csn0_hs: spi1m1-csn0-hs { + pwm10_pin_pull_down: pwm10-pin-pull-down { rockchip,pins = - <2 RK_PB1 2 &pcfg_pull_up_8ma>; + <2 RK_PB4 2 &pcfg_pull_down>; }; }; - spi2 { - spi2_clk: spi2-clk { - rockchip,pins = - <1 RK_PD0 3 &pcfg_pull_up_4ma>; - }; - - spi2_csn0: spi2-csn0 { - rockchip,pins = - <1 RK_PD1 3 &pcfg_pull_up_4ma>; - }; - - spi2_miso: spi2-miso { - rockchip,pins = - <1 RK_PC6 3 &pcfg_pull_up_4ma>; - }; - - spi2_mosi: spi2-mosi { - rockchip,pins = - <1 RK_PC7 3 &pcfg_pull_up_4ma>; - }; - - spi2_clk_hs: spi2-clk-hs { + pwm11 { + pwm11_pin: pwm11-pin { rockchip,pins = - <1 RK_PD0 3 &pcfg_pull_up_8ma>; + <2 RK_PC0 4 &pcfg_pull_none>; }; - spi2_miso_hs: spi2-miso-hs { + pwm11_pin_pull_down: pwm11-pin-pull-down { rockchip,pins = - <1 RK_PC6 3 &pcfg_pull_up_8ma>; + <2 RK_PC0 4 &pcfg_pull_down>; }; + }; - spi2_mosi_hs: spi2-mosi-hs { + rtc { + rtc_32k: rtc-32k { rockchip,pins = - <1 RK_PC7 3 &pcfg_pull_up_8ma>; + <0 RK_PC3 1 &pcfg_pull_none>; }; }; @@ -1474,17 +1633,6 @@ <4 RK_PD2 1 &pcfg_pull_up_4ma>, <4 RK_PD3 1 &pcfg_pull_up_4ma>; }; - - sdmmc_gpio: sdmmc-gpio { - rockchip,pins = - <4 RK_PD0 0 &pcfg_pull_up_4ma>, - <4 RK_PD1 0 &pcfg_pull_up_4ma>, - <4 RK_PD2 0 &pcfg_pull_up_4ma>, - <4 RK_PD3 0 &pcfg_pull_up_4ma>, - <4 RK_PD4 0 &pcfg_pull_up_4ma>, - <4 RK_PD5 0 &pcfg_pull_up_4ma>, - <4 RK_PD6 0 &pcfg_pull_up_4ma>; - }; }; sdio { @@ -1525,327 +1673,216 @@ <4 RK_PA2 1 &pcfg_pull_up_8ma>, <4 RK_PA3 1 &pcfg_pull_up_8ma>; }; - - sdio_gpio: sdio-gpio { - rockchip,pins = - <4 RK_PA0 0 &pcfg_pull_up_4ma>, - <4 RK_PA1 0 &pcfg_pull_up_4ma>, - <4 RK_PA2 0 &pcfg_pull_up_4ma>, - <4 RK_PA3 0 &pcfg_pull_up_4ma>, - <4 RK_PA4 0 &pcfg_pull_up_4ma>, - <4 RK_PA5 0 &pcfg_pull_up_4ma>; - }; }; - emmc { - emmc_clk: emmc-clk { - rockchip,pins = - <3 RK_PB1 2 &pcfg_pull_none_8ma>; - }; - - emmc_cmd: emmc-cmd { + spdif_in { + spdif_in: spdif-in { rockchip,pins = - <3 RK_PB0 2 &pcfg_pull_up_8ma>; + <0 RK_PC2 1 &pcfg_pull_none>; }; + }; - emmc_pwren: emmc-pwren { + spdif_out { + spdif_out: spdif-out { rockchip,pins = - <3 RK_PB3 2 &pcfg_pull_none>; + <0 RK_PC1 1 &pcfg_pull_none>; }; + }; - emmc_rstn: emmc-rstn { + spi0 { + spi0_clk: spi0-clk { rockchip,pins = - <3 RK_PB2 2 &pcfg_pull_none>; + <2 RK_PA2 2 &pcfg_pull_up_4ma>; }; - emmc_bus1: emmc-bus1 { + spi0_csn0: spi0-csn0 { rockchip,pins = - <3 RK_PA0 2 &pcfg_pull_up_8ma>; + <2 RK_PA3 2 &pcfg_pull_up_4ma>; }; - emmc_bus4: emmc-bus4 { + spi0_miso: spi0-miso { rockchip,pins = - <3 RK_PA0 2 &pcfg_pull_up_8ma>, - <3 RK_PA1 2 &pcfg_pull_up_8ma>, - <3 RK_PA2 2 &pcfg_pull_up_8ma>, - <3 RK_PA3 2 &pcfg_pull_up_8ma>; + <2 RK_PA0 2 &pcfg_pull_up_4ma>; }; - emmc_bus8: emmc-bus8 { + spi0_mosi: spi0-mosi { rockchip,pins = - <3 RK_PA0 2 &pcfg_pull_up_8ma>, - <3 RK_PA1 2 &pcfg_pull_up_8ma>, - <3 RK_PA2 2 &pcfg_pull_up_8ma>, - <3 RK_PA3 2 &pcfg_pull_up_8ma>, - <3 RK_PA4 2 &pcfg_pull_up_8ma>, - <3 RK_PA5 2 &pcfg_pull_up_8ma>, - <3 RK_PA6 2 &pcfg_pull_up_8ma>, - <3 RK_PA7 2 &pcfg_pull_up_8ma>; + <2 RK_PA1 2 &pcfg_pull_up_4ma>; }; }; - flash { - flash_csn0: flash-csn0 { - rockchip,pins = - <3 RK_PB5 1 &pcfg_pull_none>; - }; - - flash_rdy: flash-rdy { - rockchip,pins = - <3 RK_PB4 1 &pcfg_pull_none>; - }; - - flash_ale: flash-ale { - rockchip,pins = - <3 RK_PB3 1 &pcfg_pull_none>; - }; - - flash_cle: flash-cle { + spi1 { + spi1_clk: spi1-clk { rockchip,pins = - <3 RK_PB1 1 &pcfg_pull_none>; + <3 RK_PB3 3 &pcfg_pull_up_4ma>; }; - flash_wrn: flash-wrn { + spi1_csn0: spi1-csn0 { rockchip,pins = - <3 RK_PB0 1 &pcfg_pull_none>; + <3 RK_PB5 3 &pcfg_pull_up_4ma>; }; - flash_rdn: flash-rdn { + spi1_miso: spi1-miso { rockchip,pins = - <3 RK_PB2 1 &pcfg_pull_none>; + <3 RK_PB2 3 &pcfg_pull_up_4ma>; }; - flash_bus8: flash-bus8 { + spi1_mosi: spi1-mosi { rockchip,pins = - <3 RK_PA0 1 &pcfg_pull_up_12ma>, - <3 RK_PA1 1 &pcfg_pull_up_12ma>, - <3 RK_PA2 1 &pcfg_pull_up_12ma>, - <3 RK_PA3 1 &pcfg_pull_up_12ma>, - <3 RK_PA4 1 &pcfg_pull_up_12ma>, - <3 RK_PA5 1 &pcfg_pull_up_12ma>, - <3 RK_PA6 1 &pcfg_pull_up_12ma>, - <3 RK_PA7 1 &pcfg_pull_up_12ma>; + <3 RK_PB4 3 &pcfg_pull_up_4ma>; }; }; - pwm0 { - pwm0_pin: pwm0-pin { + spi1-m1 { + spi1m1_miso: spi1m1-miso { rockchip,pins = - <0 RK_PB5 1 &pcfg_pull_none>; + <2 RK_PA4 2 &pcfg_pull_up_4ma>; }; - pwm0_pin_pull_down: pwm0-pin-pull-down { + spi1m1_mosi: spi1m1-mosi { rockchip,pins = - <0 RK_PB5 1 &pcfg_pull_down>; + <2 RK_PA5 2 &pcfg_pull_up_4ma>; }; - }; - pwm1 { - pwm1_pin: pwm1-pin { + spi1m1_clk: spi1m1-clk { rockchip,pins = - <0 RK_PB6 1 &pcfg_pull_none>; + <2 RK_PA7 2 &pcfg_pull_up_4ma>; }; - pwm1_pin_pull_down: pwm1-pin-pull-down { + spi1m1_csn0: spi1m1-csn0 { rockchip,pins = - <0 RK_PB6 1 &pcfg_pull_down>; + <2 RK_PB1 2 &pcfg_pull_up_4ma>; }; }; - pwm2 { - pwm2_pin: pwm2-pin { + spi2 { + spi2_clk: spi2-clk { rockchip,pins = - <0 RK_PB7 1 &pcfg_pull_none>; + <1 RK_PD0 3 &pcfg_pull_up_4ma>; }; - pwm2_pin_pull_down: pwm2-pin-pull-down { + spi2_csn0: spi2-csn0 { rockchip,pins = - <0 RK_PB7 1 &pcfg_pull_down>; + <1 RK_PD1 3 &pcfg_pull_up_4ma>; }; - }; - pwm3 { - pwm3_pin: pwm3-pin { + spi2_miso: spi2-miso { rockchip,pins = - <0 RK_PC0 1 &pcfg_pull_none>; + <1 RK_PC6 3 &pcfg_pull_up_4ma>; }; - pwm3_pin_pull_down: pwm3-pin-pull-down { + spi2_mosi: spi2-mosi { rockchip,pins = - <0 RK_PC0 1 &pcfg_pull_down>; + <1 RK_PC7 3 &pcfg_pull_up_4ma>; }; }; - pwm4 { - pwm4_pin: pwm4-pin { + tsadc { + tsadc_otp_pin: tsadc-otp-pin { rockchip,pins = - <0 RK_PA1 2 &pcfg_pull_none>; + <0 RK_PB2 0 &pcfg_pull_none>; }; - pwm4_pin_pull_down: pwm4-pin-pull-down { + tsadc_otp_out: tsadc-otp-out { rockchip,pins = - <0 RK_PA1 2 &pcfg_pull_down>; + <0 RK_PB2 1 &pcfg_pull_none>; }; }; - pwm5 { - pwm5_pin: pwm5-pin { + uart0 { + uart0_xfer: uart0-xfer { rockchip,pins = - <0 RK_PC1 2 &pcfg_pull_none>; + <2 RK_PA1 1 &pcfg_pull_up>, + <2 RK_PA0 1 &pcfg_pull_up>; }; - pwm5_pin_pull_down: pwm5-pin-pull-down { + uart0_cts: uart0-cts { rockchip,pins = - <0 RK_PC1 2 &pcfg_pull_down>; + <2 RK_PA2 1 &pcfg_pull_none>; }; - }; - pwm6 { - pwm6_pin: pwm6-pin { + uart0_rts: uart0-rts { rockchip,pins = - <0 RK_PC2 2 &pcfg_pull_none>; + <2 RK_PA3 1 &pcfg_pull_none>; }; - pwm6_pin_pull_down: pwm6-pin-pull-down { + uart0_rts_pin: uart0-rts-pin { rockchip,pins = - <0 RK_PC2 2 &pcfg_pull_down>; + <2 RK_PA3 0 &pcfg_pull_none>; }; }; - pwm7 { - pwm7_pin: pwm7-pin { - rockchip,pins = - <2 RK_PB0 2 &pcfg_pull_none>; - }; - - pwm7_pin_pull_down: pwm7-pin-pull-down { + uart1 { + uart1_xfer: uart1-xfer { rockchip,pins = - <2 RK_PB0 2 &pcfg_pull_down>; + <1 RK_PD1 1 &pcfg_pull_up>, + <1 RK_PD0 1 &pcfg_pull_up>; }; - }; - pwm8 { - pwm8_pin: pwm8-pin { + uart1_cts: uart1-cts { rockchip,pins = - <2 RK_PB2 2 &pcfg_pull_none>; + <1 RK_PC6 1 &pcfg_pull_none>; }; - pwm8_pin_pull_down: pwm8-pin-pull-down { + uart1_rts: uart1-rts { rockchip,pins = - <2 RK_PB2 2 &pcfg_pull_down>; + <1 RK_PC7 1 &pcfg_pull_none>; }; }; - pwm9 { - pwm9_pin: pwm9-pin { - rockchip,pins = - <2 RK_PB3 2 &pcfg_pull_none>; - }; - - pwm9_pin_pull_down: pwm9-pin-pull-down { + uart2-m0 { + uart2m0_xfer: uart2m0-xfer { rockchip,pins = - <2 RK_PB3 2 &pcfg_pull_down>; + <1 RK_PC7 2 &pcfg_pull_up>, + <1 RK_PC6 2 &pcfg_pull_up>; }; }; - pwm10 { - pwm10_pin: pwm10-pin { - rockchip,pins = - <2 RK_PB4 2 &pcfg_pull_none>; - }; - - pwm10_pin_pull_down: pwm10-pin-pull-down { + uart2-m1 { + uart2m1_xfer: uart2m1-xfer { rockchip,pins = - <2 RK_PB4 2 &pcfg_pull_down>; + <4 RK_PD3 2 &pcfg_pull_up>, + <4 RK_PD2 2 &pcfg_pull_up>; }; }; - pwm11 { - pwm11_pin: pwm11-pin { - rockchip,pins = - <2 RK_PC0 4 &pcfg_pull_none>; - }; - - pwm11_pin_pull_down: pwm11-pin-pull-down { + uart3 { + uart3_xfer: uart3-xfer { rockchip,pins = - <2 RK_PC0 4 &pcfg_pull_down>; + <3 RK_PB5 4 &pcfg_pull_up>, + <3 RK_PB4 4 &pcfg_pull_up>; }; }; - gmac { - rmii_pins: rmii-pins { - rockchip,pins = - /* mac_txen */ - <1 RK_PC1 3 &pcfg_pull_none_12ma>, - /* mac_txd1 */ - <1 RK_PC3 3 &pcfg_pull_none_12ma>, - /* mac_txd0 */ - <1 RK_PC2 3 &pcfg_pull_none_12ma>, - /* mac_rxd0 */ - <1 RK_PC4 3 &pcfg_pull_none>, - /* mac_rxd1 */ - <1 RK_PC5 3 &pcfg_pull_none>, - /* mac_rxer */ - <1 RK_PB7 3 &pcfg_pull_none>, - /* mac_rxdv */ - <1 RK_PC0 3 &pcfg_pull_none>, - /* mac_mdio */ - <1 RK_PB6 3 &pcfg_pull_none>, - /* mac_mdc */ - <1 RK_PB5 3 &pcfg_pull_none>; - }; - - mac_refclk_12ma: mac-refclk-12ma { - rockchip,pins = - <1 RK_PB4 3 &pcfg_pull_none_12ma>; - }; - - mac_refclk: mac-refclk { + uart3-m1 { + uart3m1_xfer: uart3m1-xfer { rockchip,pins = - <1 RK_PB4 3 &pcfg_pull_none>; + <0 RK_PC2 3 &pcfg_pull_up>, + <0 RK_PC1 3 &pcfg_pull_up>; }; }; - gmac-m1 { - rmiim1_pins: rmiim1-pins { + uart4 { + uart4_xfer: uart4-xfer { rockchip,pins = - /* mac_txen */ - <4 RK_PB7 2 &pcfg_pull_none_12ma>, - /* mac_txd1 */ - <4 RK_PA5 2 &pcfg_pull_none_12ma>, - /* mac_txd0 */ - <4 RK_PA4 2 &pcfg_pull_none_12ma>, - /* mac_rxd0 */ - <4 RK_PA2 2 &pcfg_pull_none>, - /* mac_rxd1 */ - <4 RK_PA3 2 &pcfg_pull_none>, - /* mac_rxer */ - <4 RK_PA0 2 &pcfg_pull_none>, - /* mac_rxdv */ - <4 RK_PA1 2 &pcfg_pull_none>, - /* mac_mdio */ - <4 RK_PB6 2 &pcfg_pull_none>, - /* mac_mdc */ - <4 RK_PB5 2 &pcfg_pull_none>; + <4 RK_PB1 1 &pcfg_pull_up>, + <4 RK_PB0 1 &pcfg_pull_up>; }; - macm1_refclk_12ma: macm1-refclk-12ma { + uart4_cts: uart4-cts { rockchip,pins = - <4 RK_PB4 2 &pcfg_pull_none_12ma>; + <4 RK_PA6 1 &pcfg_pull_none>; }; - macm1_refclk: macm1-refclk { + uart4_rts: uart4-rts { rockchip,pins = - <4 RK_PB4 2 &pcfg_pull_none>; + <4 RK_PA7 1 &pcfg_pull_none>; }; - }; - rtc { - rtc_32k: rtc-32k { + uart4_rts_pin: uart4-rts-pin { rockchip,pins = - <0 RK_PC3 1 &pcfg_pull_none>; + <4 RK_PA7 0 &pcfg_pull_none>; }; }; - }; }; diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c index c1bae3f68bd4..33fc36da5077 100644 --- a/drivers/net/gmac_rockchip.c +++ b/drivers/net/gmac_rockchip.c @@ -739,7 +739,7 @@ static const struct udevice_id rockchip_gmac_ids[] = { .data = (ulong)&rk3228_gmac_ops }, { .compatible = "rockchip,rk3288-gmac", .data = (ulong)&rk3288_gmac_ops }, - { .compatible = "rockchip,rk3308-mac", + { .compatible = "rockchip,rk3308-gmac", .data = (ulong)&rk3308_gmac_ops }, { .compatible = "rockchip,rk3328-gmac", .data = (ulong)&rk3328_gmac_ops }, From patchwork Sat Mar 16 22:56:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonas Karlman X-Patchwork-Id: 1912839 X-Patchwork-Delegate: ykai007@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; 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a=rsa-sha256; c=relaxed/relaxed; d=kwiboo.se; h=Content-Transfer-Encoding: MIME-Version: References: In-Reply-To: Message-ID: Date: Subject: Cc: To: From; q=dns/txt; s=fe-e1b5cab7be; t=1710629859; bh=R3sxmt+1nsaohBHuQnafEVB7XHLF80gxsfldJFddb/M=; b=SU0hSb4nmRDXp7Xv9acH7n5LCiV5ispdde6UTKDl9SvxgMk5eH5Uy7hp/PxUd1lPdv/eCi+Ry tGBhF/lv3gmtUoBZiDwAu37o40R3Tl9DIHQLTFkcfFgfT1FFiKtdaZyKKw52PVemRWHINiLSXol SuoI55p7O4Q17IOoZHibG7KJ/i6veO6DAQ9ZAhQ+ZDIk7pB/NztUBxWqayWNOjBtCSmIkzN4SsE LjpmUnQrUGiPeEBhJpv/ngyzKbgcCJ9CnsHwTrmR2P4BVHZKT+PP5x8sfs5Y6njtsQCCQD5tY4o WEAcR7B+VoececoVLHOVFQkQZdcDyzoP5I7bscukp/mA== From: Jonas Karlman To: Kever Yang , Simon Glass , Philipp Tomsich , Tom Rini , Andy Yan Cc: Akash Gajjar , u-boot@lists.denx.de, Jonas Karlman Subject: [PATCH 11/13] rockchip: rk3308-evb: Update defconfig Date: Sat, 16 Mar 2024 22:56:37 +0000 Message-ID: <20240316225655.3244348-12-jonas@kwiboo.se> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240316225655.3244348-1-jonas@kwiboo.se> References: <20240316225655.3244348-1-jonas@kwiboo.se> MIME-Version: 1.0 X-Report-Abuse-To: abuse@forwardemail.net X-Report-Abuse: abuse@forwardemail.net X-Complaints-To: abuse@forwardemail.net X-ForwardEmail-Version: 0.4.40 X-ForwardEmail-Sender: rfc822; jonas@kwiboo.se, smtp.forwardemail.net, 149.28.215.223 X-ForwardEmail-ID: 65f623e20957eaab7babfd41 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Update defconfig for rk3308-evb with new defaults. Add OF_LIBFDT_OVERLAY=y to support device tree overlays. Remove the SPL_DRIVERS_MISC=y option, no misc driver is used in SPL. Remove BOOTDELAY=0, SYS_CONSOLE_INFO_QUIET=y and enable more CMD to allow use of U-Boot cmdline. Add DM_ETH_PHY=y and PHY_REALTEK=y to support onboard ethernet PHY. Add PHY_ROCKCHIP_INNO_USB2=y, DM_USB_GADGET=y and remove USB_DWC2=y to allow full use of USB 2.0 host and otg ports. Enable EFI_LOADER to allow EFI boot. Signed-off-by: Jonas Karlman --- configs/evb-rk3308_defconfig | 34 +++++++++++++--------------------- 1 file changed, 13 insertions(+), 21 deletions(-) diff --git a/configs/evb-rk3308_defconfig b/configs/evb-rk3308_defconfig index 9dc7d9c0caea..cf18be051b69 100644 --- a/configs/evb-rk3308_defconfig +++ b/configs/evb-rk3308_defconfig @@ -3,9 +3,9 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_DEFAULT_DEVICE_TREE="rk3308-evb" +CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3308=y -CONFIG_SPL_DRIVERS_MISC=y CONFIG_TARGET_EVB_RK3308=y CONFIG_DEBUG_UART_BASE=0xFF0C0000 CONFIG_DEBUG_UART_CLOCK=24000000 @@ -14,30 +14,20 @@ CONFIG_DEBUG_UART=y CONFIG_ANDROID_BOOT_IMAGE=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y -CONFIG_BOOTDELAY=0 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3308-evb.dtb" -CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set -CONFIG_SPL_MAX_SIZE=0x20000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_CONSOLE is not set -# CONFIG_CMD_ELF is not set -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_XIMG is not set +CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y CONFIG_CMD_USB_MASS_STORAGE=y -# CONFIG_CMD_ITEST is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_SLEEP is not set -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_ISO_PARTITION is not set -CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64 +CONFIG_CMD_RNG=y +CONFIG_CMD_KASLRSEED=y +CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" @@ -51,9 +41,11 @@ CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_SUPPORT_EMMC_RPMB=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y -CONFIG_PHY=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PINCTRL=y CONFIG_REGULATOR_PWM=y CONFIG_DM_REGULATOR_FIXED=y @@ -62,15 +54,15 @@ CONFIG_RAM=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSINFO=y CONFIG_SYSRESET=y CONFIG_USB=y +CONFIG_DM_USB_GADGET=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y -CONFIG_USB_DWC2=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_SPL_TINY_MEMSET=y +CONFIG_USB_FUNCTION_ROCKUSB=y CONFIG_LZO=y CONFIG_ERRNO_STR=y -# CONFIG_EFI_LOADER is not set From patchwork Sat Mar 16 22:56:38 2024 Content-Type: text/plain; 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Sat, 16 Mar 2024 23:57:54 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kwiboo.se Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=SRS0=8b2e=KX=kwiboo.se=jonas@fe-bounces.kwiboo.se DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kwiboo.se; h=Content-Transfer-Encoding: MIME-Version: References: In-Reply-To: Message-ID: Date: Subject: Cc: To: From; q=dns/txt; s=fe-e1b5cab7be; t=1710629863; bh=VT92pgHQfq0WfxmWVcMgkmu3JDjTLOKj/R/cs1XwR+Y=; b=rJTXidhRXLPDcVWL8rlySvb8L67KGUrg1EBgLxpytIt5drJLEC5+XH94jJPZCvZESDOssox2e pEXUYwscruNVdlNZ/4cnEmumyatwj+UV5b1kLWJ76vzrN/LqWtodTDckstrMcTRDutyp6WLwVhD SriORym8Wi4U9Ev2oEOoHigHneSCIDgbjnGEOIqwmWHXwMN3Hjk/gZezG/u9hQFIxdReykVauCT qbCDsBxVxoK4d7ZTVA6eo7nfm3wB6+vh6C+UQD8JahPaAes0W9fsMc/08BpL5MtxJrGnJYn+KeG fPyWfl5EwpqPeNWJd6SDX2T7k37d2AwTJLxmIwrSDL7w== From: Jonas Karlman To: Kever Yang , Simon Glass , Philipp Tomsich , Tom Rini , Andy Yan Cc: Akash Gajjar , u-boot@lists.denx.de, Jonas Karlman Subject: [PATCH 12/13] rockchip: rk3308-roc-cc: Update defconfig Date: Sat, 16 Mar 2024 22:56:38 +0000 Message-ID: <20240316225655.3244348-13-jonas@kwiboo.se> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240316225655.3244348-1-jonas@kwiboo.se> References: <20240316225655.3244348-1-jonas@kwiboo.se> MIME-Version: 1.0 X-Report-Abuse-To: abuse@forwardemail.net X-Report-Abuse: abuse@forwardemail.net X-Complaints-To: abuse@forwardemail.net X-ForwardEmail-Version: 0.4.40 X-ForwardEmail-Sender: rfc822; jonas@kwiboo.se, smtp.forwardemail.net, 149.28.215.223 X-ForwardEmail-ID: 65f623e50957eaab7babfd53 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Update defconfig for rk3308-roc-cc with new defaults. Add OF_LIBFDT_OVERLAY=y to support device tree overlays. Remove the SPL_DRIVERS_MISC=y option, no misc driver is used in SPL. Remove BOOTDELAY=0, SYS_CONSOLE_INFO_QUIET=y and enable more CMD to allow use of U-Boot cmdline. Add DM_ETH_PHY=y and PHY_REALTEK=y to support onboard ethernet PHY. Add PHY_ROCKCHIP_INNO_USB2=y, DM_USB_GADGET=y and remove USB_DWC2=y to allow full use of USB 2.0 host and otg ports. Enable EFI_LOADER to allow EFI boot. Signed-off-by: Jonas Karlman --- configs/roc-cc-rk3308_defconfig | 35 +++++++++++++-------------------- 1 file changed, 14 insertions(+), 21 deletions(-) diff --git a/configs/roc-cc-rk3308_defconfig b/configs/roc-cc-rk3308_defconfig index 041fa75b9659..ef58bd657532 100644 --- a/configs/roc-cc-rk3308_defconfig +++ b/configs/roc-cc-rk3308_defconfig @@ -4,9 +4,9 @@ CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_SPL_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="rk3308-roc-cc" +CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3308=y -CONFIG_SPL_DRIVERS_MISC=y CONFIG_TARGET_ROC_RK3308_CC=y CONFIG_DEBUG_UART_BASE=0xFF0C0000 CONFIG_DEBUG_UART_CLOCK=24000000 @@ -15,30 +15,20 @@ CONFIG_DEBUG_UART=y CONFIG_ANDROID_BOOT_IMAGE=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y -CONFIG_BOOTDELAY=0 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3308-roc-cc.dtb" -CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set -CONFIG_SPL_MAX_SIZE=0x20000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_CONSOLE is not set -# CONFIG_CMD_ELF is not set -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_XIMG is not set +CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y CONFIG_CMD_USB_MASS_STORAGE=y -# CONFIG_CMD_ITEST is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_SLEEP is not set -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_ISO_PARTITION is not set -CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64 +CONFIG_CMD_RNG=y +CONFIG_CMD_KASLRSEED=y +CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" @@ -52,27 +42,30 @@ CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_SUPPORT_EMMC_RPMB=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y -CONFIG_PHY=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PINCTRL=y CONFIG_REGULATOR_PWM=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSINFO=y CONFIG_SYSRESET=y CONFIG_USB=y +CONFIG_DM_USB_GADGET=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y -CONFIG_USB_DWC2=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_SPL_TINY_MEMSET=y +CONFIG_USB_FUNCTION_ROCKUSB=y CONFIG_LZO=y CONFIG_ERRNO_STR=y -# CONFIG_EFI_LOADER is not set From patchwork Sat Mar 16 22:56:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonas Karlman X-Patchwork-Id: 1912842 X-Patchwork-Delegate: ykai007@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=kwiboo.se header.i=@kwiboo.se header.a=rsa-sha256 header.s=fe-e1b5cab7be header.b=xU047OHa; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4TxxQP1bzQz23sC for ; Sun, 17 Mar 2024 09:59:41 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 14394880D5; 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Sat, 16 Mar 2024 23:57:54 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kwiboo.se Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=SRS0=8b2e=KX=kwiboo.se=jonas@fe-bounces.kwiboo.se DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kwiboo.se; h=Content-Transfer-Encoding: MIME-Version: References: In-Reply-To: Message-ID: Date: Subject: Cc: To: From; q=dns/txt; s=fe-e1b5cab7be; t=1710629865; bh=7tqnfCywaeROTSE0y2wp6tIugDiZimrL3vTSLclDwWg=; b=xU047OHaNZO/szaBp2+zjimUm3LUPTRioCC68GxsAbYMMiM1VDCJK34SancQSg1IvqlH8HAcM jRhnPwp7DvQNSqKZHL+7bP9RXaAV+QtRVsLlsDLEYDQMXxl5GkzJaQdXqEi7a0WjVviauBtOfop v7R+WkD+vkhQMpwQvPl7RsXKfVX6I6aJpYEtrCaQAv35CenwV2FyOkkk+Cd0LDktmc3XMpRNZhD HYpM18RFjMUfjHuEZKJvmIUGBb/Ohd8hWwGfzljlT8ciGIxsrF7efLTwaLXmkQ54V+7acsOz6o4 Fy8tm3MSXEnt8rhvxquXSuhOXIe49fPT9VSz0Txv5sNg== From: Jonas Karlman To: Kever Yang , Simon Glass , Philipp Tomsich , Tom Rini , Akash Gajjar , Jonas Karlman Cc: Andy Yan , u-boot@lists.denx.de Subject: [PATCH 13/13] rockchip: rk3308-rock-pi-s: Update defconfig Date: Sat, 16 Mar 2024 22:56:39 +0000 Message-ID: <20240316225655.3244348-14-jonas@kwiboo.se> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240316225655.3244348-1-jonas@kwiboo.se> References: <20240316225655.3244348-1-jonas@kwiboo.se> MIME-Version: 1.0 X-Report-Abuse-To: abuse@forwardemail.net X-Report-Abuse: abuse@forwardemail.net X-Complaints-To: abuse@forwardemail.net X-ForwardEmail-Version: 0.4.40 X-ForwardEmail-Sender: rfc822; jonas@kwiboo.se, smtp.forwardemail.net, 149.28.215.223 X-ForwardEmail-ID: 65f623e80957eaab7babfd65 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Update defconfig for rk3308-rock-pi-s with new defaults. Add OF_LIBFDT_OVERLAY=y to support device tree overlays. Remove the SPL_DRIVERS_MISC=y option, no misc driver is used in SPL. Remove BOOTDELAY=0, SYS_CONSOLE_INFO_QUIET=y and enable more CMD to allow use of U-Boot cmdline. Add DM_ETH_PHY=y and PHY_REALTEK=y to support onboard ethernet PHY. Add PHY_ROCKCHIP_INNO_USB2=y, DM_USB_GADGET=y and remove USB_DWC2=y to allow full use of USB 2.0 host and otg ports. Enable EFI_LOADER to allow EFI boot. Also fix use of USB 2.0 otg port by removing improper use of phy-supply and regulator-always-on props. Signed-off-by: Jonas Karlman --- arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi | 8 ++++++ configs/rock-pi-s-rk3308_defconfig | 33 +++++++++-------------- 2 files changed, 20 insertions(+), 21 deletions(-) diff --git a/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi b/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi index 45ab5c7781e5..474c81334a14 100644 --- a/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi +++ b/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi @@ -14,6 +14,10 @@ bootph-pre-ram; }; +&u2phy_otg { + /delete-property/ phy-supply; +}; + &uart0 { bootph-all; clock-frequency = <24000000>; @@ -31,6 +35,10 @@ bootph-all; }; +&vcc5v0_otg { + /delete-property/ regulator-always-on; +}; + &vdd_core { regulator-init-microvolt = <1015000>; }; diff --git a/configs/rock-pi-s-rk3308_defconfig b/configs/rock-pi-s-rk3308_defconfig index 27ee24a62290..9142671a4c0b 100644 --- a/configs/rock-pi-s-rk3308_defconfig +++ b/configs/rock-pi-s-rk3308_defconfig @@ -6,39 +6,28 @@ CONFIG_DEFAULT_DEVICE_TREE="rk3308-rock-pi-s" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3308=y -CONFIG_SPL_DRIVERS_MISC=y CONFIG_TARGET_EVB_RK3308=y CONFIG_DEBUG_UART_BASE=0xFF0A0000 CONFIG_DEBUG_UART_CLOCK=24000000 -# CONFIG_DEBUG_UART_BOARD_INIT is not set CONFIG_SYS_LOAD_ADDR=0xc00800 CONFIG_DEBUG_UART=y CONFIG_ANDROID_BOOT_IMAGE=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3308-rock-pi-s.dtb" -CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set -CONFIG_SPL_MAX_SIZE=0x20000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_CONSOLE is not set -# CONFIG_CMD_ELF is not set -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_XIMG is not set +CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y CONFIG_CMD_USB_MASS_STORAGE=y -# CONFIG_CMD_ITEST is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_SLEEP is not set -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_ISO_PARTITION is not set -CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64 +CONFIG_CMD_RNG=y +CONFIG_CMD_KASLRSEED=y +CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" @@ -52,9 +41,11 @@ CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_SUPPORT_EMMC_RPMB=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y -CONFIG_PHY=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PINCTRL=y CONFIG_REGULATOR_PWM=y CONFIG_DM_REGULATOR_FIXED=y @@ -63,15 +54,15 @@ CONFIG_RAM=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSINFO=y CONFIG_SYSRESET=y CONFIG_USB=y +CONFIG_DM_USB_GADGET=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y -CONFIG_USB_DWC2=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_SPL_TINY_MEMSET=y +CONFIG_USB_FUNCTION_ROCKUSB=y CONFIG_LZO=y CONFIG_ERRNO_STR=y -# CONFIG_EFI_LOADER is not set