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Fri, 1 Mar 2024 06:27:49 +0000 From: "demin.han" To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, pan2.li@intel.com, jeffreyalaw@gmail.com Subject: [PATCH 1/5] RISC-V: Remove float vector eqne pattern Date: Fri, 1 Mar 2024 14:27:07 +0800 Message-ID: <20240301062711.207137-2-demin.han@starfivetech.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240301062711.207137-1-demin.han@starfivetech.com> References: <20240301062711.207137-1-demin.han@starfivetech.com> X-ClientProxiedBy: BJSPR01CA0023.CHNPR01.prod.partner.outlook.cn (2406:e500:c211:c::35) To ZQ0PR01MB1063.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:d::13) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: ZQ0PR01MB1063:EE_|ZQ0PR01MB1080:EE_ X-MS-Office365-Filtering-Correlation-Id: ef1e59d8-8f3c-41a7-4630-08dc39b8b760 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 2vRWhm0YrajNbd7yUT3bi8y01l4NWbqqVGEMxmA/rJSLhHZi0KJSPc6cy1khCMWWybGSYpc0SCUsg2Gvesw0Ff778x3//Olr45vjhaiMJ+W0t2U0wvmfvJ7TbHPx1REBOjxAt8R2iOS3QpxVv+DJdFyVgXo3xZuRHNMHy+fjW/PherK1tBTqDXHskT4l5A5L790ngRYwz2hYa6efppImiLAF5w6cCpgvPxmfxFsnoIUdI3yELrlsFnCHGAi3dYuraeetMtECbrdsLI6KGMUJ0D7U6f8J4uQkQmStRq2DZqXprfa1839/NLw7pW8a1bAbfSSjQUO1cLMqGy6kKM3HouOtdXvCQU/JEjLuhrNuWml4VsAR4IroJGOzUZR9oSaZnTvIqiDSOyZB8FiC3BbTB5DS4S6FB5iTd8Dq+8sjSDiHOToph5sxusMN6cNL2HVfu14/D53NOpciwHMhIS+dLeF9Yj9yCTFVjA/N2aUlEEszqirdtn0zycKtmgP5RbtJwsbvYJ3uQUXytQL+TU8+ipIzfKFJdl4Gwx+Ahvx+/UOQRtep6rJYjnDjYQ7PgqrMXXX58wupaO22Psq68qKJoFRLCu5F8zZRYJOSkmKc10/V81bgNvI3sxrsLXNbid2q X-Forefront-Antispam-Report: CIP:255.255.255.255; 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Tested on RV32 and RV64 gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc: Remove eqne cond * config/riscv/vector.md (@pred_eqne_scalar): Remove patterns (*pred_eqne_scalar_merge_tie_mask): Ditto (*pred_eqne_scalar): Ditto (*pred_eqne_scalar_narrow): Ditto Signed-off-by: demin.han Signed-off-by: demin.han > --- .../riscv/riscv-vector-builtins-bases.cc | 4 - gcc/config/riscv/vector.md | 86 ------------------- 2 files changed, 90 deletions(-) diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index b6f6e4ff37e..d414721ede8 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -1420,10 +1420,6 @@ public: switch (e.op_info->op) { case OP_TYPE_vf: { - if (CODE == EQ || CODE == NE) - return e.use_compare_insn (CODE, code_for_pred_eqne_scalar ( - e.vector_mode ())); - else return e.use_compare_insn (CODE, code_for_pred_cmp_scalar ( e.vector_mode ())); } diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index ab6e099852d..9210d7c28ad 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -7520,92 +7520,6 @@ (define_insn "*pred_cmp_scalar_narrow" (set_attr "mode" "") (set_attr "spec_restriction" "none,thv,thv,none,none")]) -(define_expand "@pred_eqne_scalar" - [(set (match_operand: 0 "register_operand") - (if_then_else: - (unspec: - [(match_operand: 1 "vector_mask_operand") - (match_operand 6 "vector_length_operand") - (match_operand 7 "const_int_operand") - (match_operand 8 "const_int_operand") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "equality_operator" - [(vec_duplicate:V_VLSF - (match_operand: 5 "register_operand")) - (match_operand:V_VLSF 4 "register_operand")]) - (match_operand: 2 "vector_merge_operand")))] - "TARGET_VECTOR" - {}) - -(define_insn "*pred_eqne_scalar_merge_tie_mask" - [(set (match_operand: 0 "register_operand" "=vm") - (if_then_else: - (unspec: - [(match_operand: 1 "register_operand" " 0") - (match_operand 5 "vector_length_operand" " rK") - (match_operand 6 "const_int_operand" " i") - (match_operand 7 "const_int_operand" " i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 2 "equality_operator" - [(vec_duplicate:V_VLSF - (match_operand: 4 "register_operand" " f")) - (match_operand:V_VLSF 3 "register_operand" " vr")]) - (match_dup 1)))] - "TARGET_VECTOR" - "vmf%B2.vf\t%0,%3,%4,v0.t" - [(set_attr "type" "vfcmp") - (set_attr "mode" "") - (set_attr "merge_op_idx" "1") - (set_attr "vl_op_idx" "5") - (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])")) - (set (attr "avl_type_idx") (const_int 7))]) - -;; We don't use early-clobber for LMUL <= 1 to get better codegen. -(define_insn "*pred_eqne_scalar" - [(set (match_operand: 0 "register_operand" "=vr, vr, &vr, &vr") - (if_then_else: - (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1") - (match_operand 6 "vector_length_operand" " rK, rK, rK, rK") - (match_operand 7 "const_int_operand" " i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "equality_operator" - [(vec_duplicate:V_VLSF - (match_operand: 5 "register_operand" " f, f, f, f")) - (match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr")]) - (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0")))] - "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (mode)" - "vmf%B3.vf\t%0,%4,%5%p1" - [(set_attr "type" "vfcmp") - (set_attr "mode" "") - (set_attr "spec_restriction" "thv,thv,rvv,rvv")]) - -;; We use early-clobber for source LMUL > dest LMUL. -(define_insn "*pred_eqne_scalar_narrow" - [(set (match_operand: 0 "register_operand" "=vm, vr, vr, &vr, &vr") - (if_then_else: - (unspec: - [(match_operand: 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1") - (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK") - (match_operand 7 "const_int_operand" " i, i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "equality_operator" - [(vec_duplicate:V_VLSF - (match_operand: 5 "register_operand" " f, f, f, f, f")) - (match_operand:V_VLSF 4 "register_operand" " vr, 0, 0, vr, vr")]) - (match_operand: 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))] - "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (mode)" - "vmf%B3.vf\t%0,%4,%5%p1" - [(set_attr "type" "vfcmp") - (set_attr "mode" "") - (set_attr "spec_restriction" "none,thv,thv,none,none")]) - ;; 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Fri, 1 Mar 2024 06:27:50 +0000 From: "demin.han" To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, pan2.li@intel.com, jeffreyalaw@gmail.com Subject: [PATCH 2/5] RISC-V: Refactor expand_vec_cmp Date: Fri, 1 Mar 2024 14:27:08 +0800 Message-ID: <20240301062711.207137-3-demin.han@starfivetech.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240301062711.207137-1-demin.han@starfivetech.com> References: <20240301062711.207137-1-demin.han@starfivetech.com> X-ClientProxiedBy: BJSPR01CA0023.CHNPR01.prod.partner.outlook.cn (2406:e500:c211:c::35) To ZQ0PR01MB1063.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:d::13) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: ZQ0PR01MB1063:EE_|ZQ0PR01MB1080:EE_ X-MS-Office365-Filtering-Correlation-Id: c469d51e-8ad4-423b-15e4-08dc39b8b7d5 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 6Yrl66OAo/3gVBHIaptAy5F0meNkZH3Yv69rsNfkXIqHWmIJS4s3S+oqivOlvCrZkPYliGuylfo71Czs25AjkcW6jJA5SkbviyLKP7boVwuU0MNTgPiWJ2qiXG2d1KMjIBznWEQgdNL87ylhwlQUcfScMO6vefpeSp1YnhFlijbl6/rEApW0JzGveJqMk6XvirPZfC0SI6TdXXnpMCbH3kvg+XORj8HGl662nR7YavoGbuugT3yexdKaUKasUalbyiRaPNUX44AIPnmnSikjY+4ZLU8i/1BuanLnG6hn6BDvmeyQL2ULNHewbFIWSSBrxuQn02xutdDz+JwE2zcnfZgogowT5U+/ai53528bAVP44Jh8MOPStlrpwd236Avo94Gay8tEwEVLcNkwaFSuPf2F2hFwzYWJ00RMgklg4yU5fxRjV0hmiWeXXqXNM6g3lWzuIx2+fBtAUeubOm+VXbydJmKJ7ANs3l27MNOZfxIppI5SrtzRSUIRQVGxzct3Ho9KdJiXcmaC7P/cK40HwlbOrVV0j4Im3adfvzehIfTDJDKB0ajYcT89x5UWCeGEYVG9OM0dsshvi9irQ/6yvfKCqND972Z/1WmI/0K2rSuXuwgUUR/igXk1fi45mLAi X-Forefront-Antispam-Report: CIP:255.255.255.255; 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They have same structure and similar code. We can use default arguments instead of overloading. Tested on RV32 and RV64. gcc/ChangeLog: * config/riscv/riscv-protos.h (expand_vec_cmp): Change proto * config/riscv/riscv-v.cc (expand_vec_cmp): Use default arguments (expand_vec_cmp_float): Adapt arguments Signed-off-by: demin.han Signed-off-by: demin.han X-Patchwork-Id: 1906554 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4TmJ9S4yXxz1yXC for ; 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Fri, 1 Mar 2024 06:27:50 +0000 From: "demin.han" To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, pan2.li@intel.com, jeffreyalaw@gmail.com Subject: [PATCH 3/5] RISC-V: Support vmfxx.vf for autovec comparison of vec and imm Date: Fri, 1 Mar 2024 14:27:09 +0800 Message-ID: <20240301062711.207137-4-demin.han@starfivetech.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240301062711.207137-1-demin.han@starfivetech.com> References: <20240301062711.207137-1-demin.han@starfivetech.com> X-ClientProxiedBy: BJSPR01CA0023.CHNPR01.prod.partner.outlook.cn (2406:e500:c211:c::35) To ZQ0PR01MB1063.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:d::13) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: ZQ0PR01MB1063:EE_|ZQ0PR01MB1080:EE_ X-MS-Office365-Filtering-Correlation-Id: c8bd0f30-bacc-4399-abcd-08dc39b8b82f X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: eg40foBzzvUXq7367SrSTk4vTRZsx2M6NAlyhLiOscr3S9E0+Wqeav3xwUnyT0odzA0Rh6AztWusvtDwMv05sItVMUgvxzka3pIL8FxnX7/CPcbbUZepDWBiiXUnwhPFTpbO+VZNLuc17EN7OZ0aJAk2cVg7MqbFa9uz6C5xMvzzeXJoim8ffF9sfLNtlQUFzYNg0q7WSj3fUzEEXekEqCM485yiU8JwLPKXIs62FtkmsGy+OGDBVMYtvVr/xFxcVw839g7j1Nd8Ili3NZinwuWkwMhJut3ABn7XuPUVNp/aJG7MnvGjVPZ8PYs5G+r2/Il3TdY69u26BIJTecydhVqCmO3qlg4mN27dgUDcHMNIHdP5NUite/wJIOcwK9SvRkeSpX7tfRr3smDINwryDbedZRy5fEegFLHAgquvVd4AqGaNePapvruhTGLvW35UkiKQCPtLIltUdBNmh/49RXveVGzKhaNM6wsow5iYGpKGqREvGswwWQz2TscPCbf7GCf3AuT89nP2pgUmO8Kur4rtVsTYUcDHOVT1qjX4wlp79LfWAN8sYuZVTDPQIvaAQLNiney4NezZUnq+c25ERo4oUp68pNlUTo8sDCqA+yf7bfD8oZiyo+fJgGIJ6uci X-Forefront-Antispam-Report: CIP:255.255.255.255; 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Additional vsetvl and vfmv instructions 2. Occupy one vector register and may results in smaller lmul We expect: flw ... vmfxx.vf Tested on RV32 and RV64 gcc/ChangeLog: * config/riscv/autovec.md: Accept imm * config/riscv/riscv-v.cc (get_cmp_insn_code): Select scalar pattern (expand_vec_cmp): Ditto * config/riscv/riscv.cc (riscv_const_insns): Exclude float mode gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/cmp/vcond-1.c: Add new tests Signed-off-by: demin.han Signed-off-by: demin.han > --- gcc/config/riscv/autovec.md | 2 +- gcc/config/riscv/riscv-v.cc | 23 +++++++++---- gcc/config/riscv/riscv.cc | 2 +- .../riscv/rvv/autovec/cmp/vcond-1.c | 34 +++++++++++++++++++ 4 files changed, 52 insertions(+), 9 deletions(-) diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index 3b32369f68c..6cfb0800c45 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -690,7 +690,7 @@ (define_expand "vec_cmp" [(set (match_operand: 0 "register_operand") (match_operator: 1 "comparison_operator" [(match_operand:V_VLSF 2 "register_operand") - (match_operand:V_VLSF 3 "register_operand")]))] + (match_operand:V_VLSF 3 "nonmemory_operand")]))] "TARGET_VECTOR" { riscv_vector::expand_vec_cmp_float (operands[0], GET_CODE (operands[1]), diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 14e75b9a117..2a188ac78e0 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -2610,9 +2610,15 @@ expand_vec_init (rtx target, rtx vals) /* Get insn code for corresponding comparison. */ static insn_code -get_cmp_insn_code (rtx_code code, machine_mode mode) +get_cmp_insn_code (rtx_code code, machine_mode mode, bool scalar_p) { insn_code icode; + if (FLOAT_MODE_P (mode)) + { + icode = !scalar_p ? code_for_pred_cmp (mode) + : code_for_pred_cmp_scalar (mode); + return icode; + } switch (code) { case EQ: @@ -2628,10 +2634,7 @@ get_cmp_insn_code (rtx_code code, machine_mode mode) case LTU: case GE: case GEU: - if (FLOAT_MODE_P (mode)) - icode = code_for_pred_cmp (mode); - else - icode = code_for_pred_ltge (mode); + icode = code_for_pred_ltge (mode); break; default: gcc_unreachable (); @@ -2757,7 +2760,6 @@ expand_vec_cmp (rtx target, rtx_code code, rtx op0, rtx op1, rtx mask, { machine_mode mask_mode = GET_MODE (target); machine_mode data_mode = GET_MODE (op0); - insn_code icode = get_cmp_insn_code (code, data_mode); if (code == LTGT) { @@ -2765,12 +2767,19 @@ expand_vec_cmp (rtx target, rtx_code code, rtx op0, rtx op1, rtx mask, rtx gt = gen_reg_rtx (mask_mode); expand_vec_cmp (lt, LT, op0, op1, mask, maskoff); expand_vec_cmp (gt, GT, op0, op1, mask, maskoff); - icode = code_for_pred (IOR, mask_mode); + insn_code icode = code_for_pred (IOR, mask_mode); rtx ops[] = {target, lt, gt}; emit_vlmax_insn (icode, BINARY_MASK_OP, ops); return; } + rtx elt; + machine_mode scalar_mode = GET_MODE_INNER (GET_MODE (op1)); + bool scalar_p = const_vec_duplicate_p (op1, &elt) && FLOAT_MODE_P (data_mode); + if (scalar_p) + op1 = force_reg (scalar_mode, elt); + insn_code icode = get_cmp_insn_code (code, data_mode, scalar_p); + rtx cmp = gen_rtx_fmt_ee (code, mask_mode, op0, op1); if (!mask && !maskoff) { diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 4100abc9dd1..1ffe4865c19 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -1760,7 +1760,7 @@ riscv_const_insns (rtx x) register vec_duplicate into vmv.v.x. */ scalar_mode smode = GET_MODE_INNER (GET_MODE (x)); if (maybe_gt (GET_MODE_SIZE (smode), UNITS_PER_WORD) - && !immediate_operand (elt, Pmode)) + && !FLOAT_MODE_P (smode) && !immediate_operand (elt, Pmode)) return 0; /* Constants from -16 to 15 can be loaded with vmv.v.i. The Wc0, Wc1 constraints are already covered by the diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-1.c index 99a230d1c8a..7f6738518ee 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-1.c @@ -141,6 +141,34 @@ TEST_VAR_ALL (DEF_VCOND_VAR) TEST_IMM_ALL (DEF_VCOND_IMM) +#define TEST_COND_IMM_FLOAT(T, COND, IMM, SUFFIX) \ + T (float, float, COND, IMM, SUFFIX##_float_float) \ + T (double, double, COND, IMM, SUFFIX##_double_double) + +#define TEST_IMM_FLOAT_ALL(T) \ + TEST_COND_IMM_FLOAT (T, >, 0.0, _gt) \ + TEST_COND_IMM_FLOAT (T, <, 0.0, _lt) \ + TEST_COND_IMM_FLOAT (T, >=, 0.0, _ge) \ + TEST_COND_IMM_FLOAT (T, <=, 0.0, _le) \ + TEST_COND_IMM_FLOAT (T, ==, 0.0, _eq) \ + TEST_COND_IMM_FLOAT (T, !=, 0.0, _ne) \ + \ + TEST_COND_IMM_FLOAT (T, >, 1.0, _gt1) \ + TEST_COND_IMM_FLOAT (T, <, 1.0, _lt1) \ + TEST_COND_IMM_FLOAT (T, >=, 1.0, _ge1) \ + TEST_COND_IMM_FLOAT (T, <=, 1.0, _le1) \ + TEST_COND_IMM_FLOAT (T, ==, 1.0, _eq1) \ + TEST_COND_IMM_FLOAT (T, !=, 1.0, _ne1) \ + \ + TEST_COND_IMM_FLOAT (T, >, -1.0, _gt2) \ + TEST_COND_IMM_FLOAT (T, <, -1.0, _lt2) \ + TEST_COND_IMM_FLOAT (T, >=, -1.0, _ge2) \ + TEST_COND_IMM_FLOAT (T, <=, -1.0, _le2) \ + TEST_COND_IMM_FLOAT (T, ==, -1.0, _eq2) \ + TEST_COND_IMM_FLOAT (T, !=, -1.0, _ne2) + +TEST_IMM_FLOAT_ALL (DEF_VCOND_IMM) + /* { dg-final { scan-assembler-times {\tvmseq\.vi} 42 } } */ /* { dg-final { scan-assembler-times {\tvmsne\.vi} 42 } } */ /* { dg-final { scan-assembler-times {\tvmsgt\.vi} 30 } } */ @@ -155,3 +183,9 @@ TEST_IMM_ALL (DEF_VCOND_IMM) /* { dg-final { scan-assembler-times {\tvmslt} 38 } } */ /* { dg-final { scan-assembler-times {\tvmsge} 38 } } */ /* { dg-final { scan-assembler-times {\tvmsle} 82 } } */ +/* { dg-final { scan-assembler-times {\tvmfgt.vf} 6 } } */ +/* { dg-final { scan-assembler-times {\tvmflt.vf} 6 } } */ +/* { dg-final { scan-assembler-times {\tvmfge.vf} 6 } } */ +/* { dg-final { scan-assembler-times {\tvmfle.vf} 6 } } */ +/* { dg-final { scan-assembler-times {\tvmfeq.vf} 6 } } */ +/* { dg-final { scan-assembler-times {\tvmfne.vf} 6 } } */ From patchwork Fri Mar 1 06:27:10 2024 Content-Type: text/plain; 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Fri, 1 Mar 2024 06:27:51 +0000 From: "demin.han" To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, pan2.li@intel.com, jeffreyalaw@gmail.com Subject: [PATCH 4/5] RISC-V: Remove integer vector eqne pattern Date: Fri, 1 Mar 2024 14:27:10 +0800 Message-ID: <20240301062711.207137-5-demin.han@starfivetech.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240301062711.207137-1-demin.han@starfivetech.com> References: <20240301062711.207137-1-demin.han@starfivetech.com> X-ClientProxiedBy: BJSPR01CA0023.CHNPR01.prod.partner.outlook.cn (2406:e500:c211:c::35) To ZQ0PR01MB1063.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:d::13) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: ZQ0PR01MB1063:EE_|ZQ0PR01MB1080:EE_ X-MS-Office365-Filtering-Correlation-Id: fc18a36c-5375-48c9-c6da-08dc39b8b893 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: dPSQuXrm2cqgkQJVTR7S5cbCapCzvMPbNwtejQrg/5kUcA+ErLVahB92JaOAu5VeAehXAkixfrfWdl0z+IWADiBCQ4LheIvnUew8ouU9dYPvUl2GjUPeO7awsE8qbqdjaJCQ1d61/W8AW9lSN1Z+BBTrUM4sxjd9YEFDlv6gb0Wo82RF/CWlCBhWbegirvf5AukAXVp4/25jTB7MNtfisNTQ1KMN5+CNyVQZy/DINlCAR6MMCUUl9jQqofK61IJoCkT1RGKEmFBu9QlHSiRi7QUoy+UQFYcclHdNjXZvZx4YjTqAaHHShJ/uo2SPx/gpzhUzGmWGPA7mzQo8HGDAs1iuk9PVnYgov6IcLMmgnIIKQzoYI1NbYMgwToZwxDViemJPHcB3nlgxEBkNJg3MWdnXQgiDBLz53y6Wp5kOMLinpf8+GjdL9mIZHHk7Yt/hZTFoce8y4zbUPlMaLTn54q3svoEFxmD3SCEBDnnFFUh/3VTmO49dlnAb1PmgEUjK7Py/l2VSlnZmNLYY784v/B6vKdZBzGhDL/8/TVp4RpH/h3Q2qxh2SSwZlAVNUCkFRV3pRm0+GUs4Izu9yDkVJ9nxkaHTCI0DCpANW8jpNJGbJP8O4XZUALhHCWufspob X-Forefront-Antispam-Report: CIP:255.255.255.255; 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Tested on RV32 and RV64. gcc/ChangeLog: * config/riscv/predicates.md (comparison_except_eqge_operator): Only exclue ge (comparison_except_ge_operator): Ditto * config/riscv/riscv-string.cc (expand_rawmemchr): Use cmp pattern (expand_strcmp): Ditto * config/riscv/riscv-vector-builtins-bases.cc: Remvoe eqne cond * config/riscv/vector.md (@pred_eqne_scalar): Remove eqne patterns (*pred_eqne_scalar_merge_tie_mask): Ditto (*pred_eqne_scalar): Ditto (*pred_eqne_scalar_narrow): Ditto (*pred_eqne_extended_scalar_merge_tie_mask): Ditto (*pred_eqne_extended_scalar): Ditto (*pred_eqne_extended_scalar_narrow): Ditto Signed-off-by: demin.han Signed-off-by: demin.han _scalar" (match_operand 8 "const_int_operand") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "comparison_except_eqge_operator" + (match_operator: 3 "comparison_except_ge_operator" [(match_operand:V_VLSI_QHS 4 "register_operand") (vec_duplicate:V_VLSI_QHS (match_operand: 5 "register_operand"))]) @@ -4689,7 +4689,7 @@ (define_insn "*pred_cmp_scalar_merge_tie_mask" (match_operand 7 "const_int_operand" " i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 2 "comparison_except_eqge_operator" + (match_operator: 2 "comparison_except_ge_operator" [(match_operand:V_VLSI_QHS 3 "register_operand" " vr") (vec_duplicate:V_VLSI_QHS (match_operand: 4 "register_operand" " r"))]) @@ -4714,7 +4714,7 @@ (define_insn "*pred_cmp_scalar" (match_operand 8 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "comparison_except_eqge_operator" + (match_operator: 3 "comparison_except_ge_operator" [(match_operand:V_VLSI_QHS 4 "register_operand" " vr, vr, vr, vr") (vec_duplicate:V_VLSI_QHS (match_operand: 5 "register_operand" " r, r, r, r"))]) @@ -4736,7 +4736,7 @@ (define_insn "*pred_cmp_scalar_narrow" (match_operand 8 "const_int_operand" " i, i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "comparison_except_eqge_operator" + (match_operator: 3 "comparison_except_ge_operator" [(match_operand:V_VLSI_QHS 4 "register_operand" " vr, 0, 0, vr, vr") (vec_duplicate:V_VLSI_QHS (match_operand: 5 "register_operand" " r, r, r, r, r"))]) @@ -4747,92 +4747,6 @@ (define_insn "*pred_cmp_scalar_narrow" (set_attr "mode" "") (set_attr "spec_restriction" "none,thv,thv,none,none")]) -(define_expand "@pred_eqne_scalar" - [(set (match_operand: 0 "register_operand") - (if_then_else: - (unspec: - [(match_operand: 1 "vector_mask_operand") - (match_operand 6 "vector_length_operand") - (match_operand 7 "const_int_operand") - (match_operand 8 "const_int_operand") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "equality_operator" - [(vec_duplicate:V_VLSI_QHS - (match_operand: 5 "register_operand")) - (match_operand:V_VLSI_QHS 4 "register_operand")]) - (match_operand: 2 "vector_merge_operand")))] - "TARGET_VECTOR" - {}) - -(define_insn "*pred_eqne_scalar_merge_tie_mask" - [(set (match_operand: 0 "register_operand" "=vm") - (if_then_else: - (unspec: - [(match_operand: 1 "register_operand" " 0") - (match_operand 5 "vector_length_operand" " rK") - (match_operand 6 "const_int_operand" " i") - (match_operand 7 "const_int_operand" " i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 2 "equality_operator" - [(vec_duplicate:V_VLSI_QHS - (match_operand: 4 "register_operand" " r")) - (match_operand:V_VLSI_QHS 3 "register_operand" " vr")]) - (match_dup 1)))] - "TARGET_VECTOR" - "vms%B2.vx\t%0,%3,%4,v0.t" - [(set_attr "type" "vicmp") - (set_attr "mode" "") - (set_attr "merge_op_idx" "1") - (set_attr "vl_op_idx" "5") - (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])")) - (set (attr "avl_type_idx") (const_int 7))]) - -;; We don't use early-clobber for LMUL <= 1 to get better codegen. -(define_insn "*pred_eqne_scalar" - [(set (match_operand: 0 "register_operand" "=vr, vr, &vr, &vr") - (if_then_else: - (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1") - (match_operand 6 "vector_length_operand" " rK, rK, rK, rK") - (match_operand 7 "const_int_operand" " i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "equality_operator" - [(vec_duplicate:V_VLSI_QHS - (match_operand: 5 "register_operand" " r, r, r, r")) - (match_operand:V_VLSI_QHS 4 "register_operand" " vr, vr, vr, vr")]) - (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0")))] - "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (mode)" - "vms%B3.vx\t%0,%4,%5%p1" - [(set_attr "type" "vicmp") - (set_attr "mode" "") - (set_attr "spec_restriction" "thv,thv,rvv,rvv")]) - -;; We use early-clobber for source LMUL > dest LMUL. -(define_insn "*pred_eqne_scalar_narrow" - [(set (match_operand: 0 "register_operand" "=vm, vr, vr, &vr, &vr") - (if_then_else: - (unspec: - [(match_operand: 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1") - (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK") - (match_operand 7 "const_int_operand" " i, i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "equality_operator" - [(vec_duplicate:V_VLSI_QHS - (match_operand: 5 "register_operand" " r, r, r, r, r")) - (match_operand:V_VLSI_QHS 4 "register_operand" " vr, 0, 0, vr, vr")]) - (match_operand: 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))] - "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (mode)" - "vms%B3.vx\t%0,%4,%5%p1" - [(set_attr "type" "vicmp") - (set_attr "mode" "") - (set_attr "spec_restriction" "none,thv,thv,none,none")]) - ;; Handle GET_MODE_INNER (mode) = DImode. We need to split them since ;; we need to deal with SEW = 64 in RV32 system. (define_expand "@pred_cmp_scalar" @@ -4845,7 +4759,7 @@ (define_expand "@pred_cmp_scalar" (match_operand 8 "const_int_operand") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "comparison_except_eqge_operator" + (match_operator: 3 "comparison_except_ge_operator" [(match_operand:V_VLSI_D 4 "register_operand") (vec_duplicate:V_VLSI_D (match_operand: 5 "reg_or_int_operand"))]) @@ -4875,39 +4789,6 @@ (define_expand "@pred_cmp_scalar" DONE; }) -(define_expand "@pred_eqne_scalar" - [(set (match_operand: 0 "register_operand") - (if_then_else: - (unspec: - [(match_operand: 1 "vector_mask_operand") - (match_operand 6 "vector_length_operand") - (match_operand 7 "const_int_operand") - (match_operand 8 "const_int_operand") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "equality_operator" - [(vec_duplicate:V_VLSI_D - (match_operand: 5 "reg_or_int_operand")) - (match_operand:V_VLSI_D 4 "register_operand")]) - (match_operand: 2 "vector_merge_operand")))] - "TARGET_VECTOR" -{ - enum rtx_code code = GET_CODE (operands[3]); - if (riscv_vector::sew64_scalar_helper ( - operands, - /* scalar op */&operands[5], - /* vl */operands[6], - mode, - riscv_vector::has_vi_variant_p (code, operands[5]), - [] (rtx *operands, rtx boardcast_scalar) { - emit_insn (gen_pred_cmp (operands[0], operands[1], - operands[2], operands[3], operands[4], boardcast_scalar, - operands[6], operands[7], operands[8])); - }, - (riscv_vector::avl_type) INTVAL (operands[8]))) - DONE; -}) - (define_insn "*pred_cmp_scalar_merge_tie_mask" [(set (match_operand: 0 "register_operand" "=vm") (if_then_else: @@ -4918,7 +4799,7 @@ (define_insn "*pred_cmp_scalar_merge_tie_mask" (match_operand 7 "const_int_operand" " i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 2 "comparison_except_eqge_operator" + (match_operator: 2 "comparison_except_ge_operator" [(match_operand:V_VLSI_D 3 "register_operand" " vr") (vec_duplicate:V_VLSI_D (match_operand: 4 "register_operand" " r"))]) @@ -4932,30 +4813,6 @@ (define_insn "*pred_cmp_scalar_merge_tie_mask" (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])")) (set (attr "avl_type_idx") (const_int 7))]) -(define_insn "*pred_eqne_scalar_merge_tie_mask" - [(set (match_operand: 0 "register_operand" "=vm") - (if_then_else: - (unspec: - [(match_operand: 1 "register_operand" " 0") - (match_operand 5 "vector_length_operand" " rK") - (match_operand 6 "const_int_operand" " i") - (match_operand 7 "const_int_operand" " i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 2 "equality_operator" - [(vec_duplicate:V_VLSI_D - (match_operand: 4 "register_operand" " r")) - (match_operand:V_VLSI_D 3 "register_operand" " vr")]) - (match_dup 1)))] - "TARGET_VECTOR" - "vms%B2.vx\t%0,%3,%4,v0.t" - [(set_attr "type" "vicmp") - (set_attr "mode" "") - (set_attr "merge_op_idx" "1") - (set_attr "vl_op_idx" "5") - (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])")) - (set (attr "avl_type_idx") (const_int 7))]) - ;; We don't use early-clobber for LMUL <= 1 to get better codegen. (define_insn "*pred_cmp_scalar" [(set (match_operand: 0 "register_operand" "=vr, vr, &vr, &vr") @@ -4967,7 +4824,7 @@ (define_insn "*pred_cmp_scalar" (match_operand 8 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "comparison_except_eqge_operator" + (match_operator: 3 "comparison_except_ge_operator" [(match_operand:V_VLSI_D 4 "register_operand" " vr, vr, vr, vr") (vec_duplicate:V_VLSI_D (match_operand: 5 "register_operand" " r, r, r, r"))]) @@ -4989,7 +4846,7 @@ (define_insn "*pred_cmp_scalar_narrow" (match_operand 8 "const_int_operand" " i, i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "comparison_except_eqge_operator" + (match_operator: 3 "comparison_except_ge_operator" [(match_operand:V_VLSI_D 4 "register_operand" " vr, 0, 0, vr, vr") (vec_duplicate:V_VLSI_D (match_operand: 5 "register_operand" " r, r, r, r, r"))]) @@ -5000,50 +4857,6 @@ (define_insn "*pred_cmp_scalar_narrow" (set_attr "mode" "") (set_attr "spec_restriction" "none,thv,thv,none,none")]) -;; We don't use early-clobber for LMUL <= 1 to get better codegen. -(define_insn "*pred_eqne_scalar" - [(set (match_operand: 0 "register_operand" "=vr, vr, &vr, &vr") - (if_then_else: - (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1") - (match_operand 6 "vector_length_operand" " rK, rK, rK, rK") - (match_operand 7 "const_int_operand" " i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "equality_operator" - [(vec_duplicate:V_VLSI_D - (match_operand: 5 "register_operand" " r, r, r, r")) - (match_operand:V_VLSI_D 4 "register_operand" " vr, vr, vr, vr")]) - (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0")))] - "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (mode)" - "vms%B3.vx\t%0,%4,%5%p1" - [(set_attr "type" "vicmp") - (set_attr "mode" "") - (set_attr "spec_restriction" "thv,thv,rvv,rvv")]) - -;; We use early-clobber for source LMUL > dest LMUL. -(define_insn "*pred_eqne_scalar_narrow" - [(set (match_operand: 0 "register_operand" "=vm, vr, vr, &vr, &vr") - (if_then_else: - (unspec: - [(match_operand: 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1") - (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK") - (match_operand 7 "const_int_operand" " i, i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "equality_operator" - [(vec_duplicate:V_VLSI_D - (match_operand: 5 "register_operand" " r, r, r, r, r")) - (match_operand:V_VLSI_D 4 "register_operand" " vr, 0, 0, vr, vr")]) - (match_operand: 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))] - "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (mode)" - "vms%B3.vx\t%0,%4,%5%p1" - [(set_attr "type" "vicmp") - (set_attr "mode" "") - (set_attr "spec_restriction" "none,thv,thv,none,none")]) - (define_insn "*pred_cmp_extended_scalar_merge_tie_mask" [(set (match_operand: 0 "register_operand" "=vm") (if_then_else: @@ -5054,7 +4867,7 @@ (define_insn "*pred_cmp_extended_scalar_merge_tie_mask" (match_operand 7 "const_int_operand" " i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 2 "comparison_except_eqge_operator" + (match_operator: 2 "comparison_except_ge_operator" [(match_operand:V_VLSI_D 3 "register_operand" " vr") (vec_duplicate:V_VLSI_D (sign_extend: @@ -5080,7 +4893,7 @@ (define_insn "*pred_cmp_extended_scalar" (match_operand 8 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "comparison_except_eqge_operator" + (match_operator: 3 "comparison_except_ge_operator" [(match_operand:V_VLSI_D 4 "register_operand" " vr, vr, vr, vr") (vec_duplicate:V_VLSI_D (sign_extend: @@ -5102,7 +4915,7 @@ (define_insn "*pred_cmp_extended_scalar_narrow" (match_operand 8 "const_int_operand" " i, i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "comparison_except_eqge_operator" + (match_operator: 3 "comparison_except_ge_operator" [(match_operand:V_VLSI_D 4 "register_operand" " vr, 0, 0, vr, vr") (vec_duplicate:V_VLSI_D (sign_extend: @@ -5114,76 +4927,6 @@ (define_insn "*pred_cmp_extended_scalar_narrow" (set_attr "mode" "") (set_attr "spec_restriction" "none,thv,thv,none,none")]) -(define_insn "*pred_eqne_extended_scalar_merge_tie_mask" - [(set (match_operand: 0 "register_operand" "=vm") - (if_then_else: - (unspec: - [(match_operand: 1 "register_operand" " 0") - (match_operand 5 "vector_length_operand" " rK") - (match_operand 6 "const_int_operand" " i") - (match_operand 7 "const_int_operand" " i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 2 "equality_operator" - [(vec_duplicate:V_VLSI_D - (sign_extend: - (match_operand: 4 "register_operand" " r"))) - (match_operand:V_VLSI_D 3 "register_operand" " vr")]) - (match_dup 1)))] - "TARGET_VECTOR && !TARGET_64BIT" - "vms%B2.vx\t%0,%3,%4,v0.t" - [(set_attr "type" "vicmp") - (set_attr "mode" "") - (set_attr "merge_op_idx" "1") - (set_attr "vl_op_idx" "5") - (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])")) - (set (attr "avl_type_idx") (const_int 7))]) - -;; We don't use early-clobber for LMUL <= 1 to get better codegen. -(define_insn "*pred_eqne_extended_scalar" - [(set (match_operand: 0 "register_operand" "=vr, vr, &vr, &vr") - (if_then_else: - (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1") - (match_operand 6 "vector_length_operand" " rK, rK, rK, rK") - (match_operand 7 "const_int_operand" " i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "equality_operator" - [(vec_duplicate:V_VLSI_D - (sign_extend: - (match_operand: 5 "register_operand" " r, r, r, r"))) - (match_operand:V_VLSI_D 4 "register_operand" " vr, vr, vr, vr")]) - (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0")))] - "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (mode) && !TARGET_64BIT" - "vms%B3.vx\t%0,%4,%5%p1" - [(set_attr "type" "vicmp") - (set_attr "mode" "") - (set_attr "spec_restriction" "thv,thv,rvv,rvv")]) - -(define_insn "*pred_eqne_extended_scalar_narrow" - [(set (match_operand: 0 "register_operand" "=vm, vr, vr, &vr, &vr") - (if_then_else: - (unspec: - [(match_operand: 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1") - (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK") - (match_operand 7 "const_int_operand" " i, i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "equality_operator" - [(vec_duplicate:V_VLSI_D - (sign_extend: - (match_operand: 5 "register_operand" " r, r, r, r, r"))) - (match_operand:V_VLSI_D 4 "register_operand" " vr, 0, 0, vr, vr")]) - (match_operand: 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))] - "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (mode) && !TARGET_64BIT" - "vms%B3.vx\t%0,%4,%5%p1" - [(set_attr "type" "vicmp") - (set_attr "mode" "") - (set_attr "spec_restriction" "none,thv,thv,none,none")]) - ;; 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Fri, 1 Mar 2024 06:27:52 +0000 From: "demin.han" To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, pan2.li@intel.com, jeffreyalaw@gmail.com Subject: [PATCH 5/5] RISC-V: Support vmsxx.vx for autovec comparison of vec and imm Date: Fri, 1 Mar 2024 14:27:11 +0800 Message-ID: <20240301062711.207137-6-demin.han@starfivetech.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240301062711.207137-1-demin.han@starfivetech.com> References: <20240301062711.207137-1-demin.han@starfivetech.com> X-ClientProxiedBy: BJSPR01CA0023.CHNPR01.prod.partner.outlook.cn (2406:e500:c211:c::35) To ZQ0PR01MB1063.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:d::13) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: ZQ0PR01MB1063:EE_|ZQ0PR01MB1000:EE_ X-MS-Office365-Filtering-Correlation-Id: fa16049a-53ed-4700-82a1-08dc39b8b8f5 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: wgw9O8bmXH57vLjdO+qd4UuJSVOGMfH3ujAgrJvF2lOodIbyhIwh3uh58nolN7EvOUQmhQi5/hmF7zUi3GE5vViVdhAwnlhhBU2gUy7eM+A/qC3OoAIclqh3nikXIEinDWt//sC3iTG0cbkKkxjn8kKPIPIJn2H/4/BjxrScmZ1BEBW5uOJhwSEKifsjeD6+tj+qgO4Fv+3gbzstQ6MuBr3byiU1ECmp6bWNSZAE6pfsnoazW97p0AAn5dMF4byhF+TdzZKfs7HXz/+6fPmkx5TsO1qnnZF8vsH0JALtWKphxWCZMfHgMC5A0YNKLLBRjNo5vD5LdAIvW8cI1sEZjolGNHBtI+q272GrRJHj9xjTU7pheMIg85otU3wJUiRixLs2EmqPFu7RnyNjB+Ftxe3RptafyugAf+iXWTYB8eF1+f4mDti0RUUuic0rBJDoDIMhxUgzbu3KmhWNRU7uAMcAWMYMAT/UERyFDsNtM9xp/5KoxPmUBGD9ZpsMp+go4Y/udcypqs9/k6J2pN5mqvjh4EstrBqsms/ilMYF1Jns+IVQ2NUzhroWPzQBTCS73xqixHuTlzvOxqto0ItqL/YbLYLmmibmppG2GKHYseZNFso0fNA12FeKjHxheFZL X-Forefront-Antispam-Report: CIP:255.255.255.255; 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Only those which can't match vi should use vx. 2. DImode is processed by sew64_scalar_helper. Tested on RV32 and RV64. gcc/ChangeLog: * config/riscv/riscv-v.cc (get_cmp_insn_code): Select scalar pattern (expand_vec_cmp): Ditto gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/cmp/vcond-1.c: Update expect Signed-off-by: demin.han Signed-off-by: demin.han