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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id b8-20020a17090ae38800b0029a8e5355fcsm1484842pjz.53.2024.02.28.04.23.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Feb 2024 04:23:49 -0800 (PST) From: Kito Cheng To: gcc-patches@gcc.gnu.org, kito.cheng@gmail.com, palmer@dabbelt.com, pinskia@gmail.com, patrick@rivosinc.com, jeffreyalaw@gmail.com Cc: Kito Cheng Subject: [PATCH] RISC-V: Fix __atomic_compare_exchange with 32 bit value on RV64 Date: Wed, 28 Feb 2024 20:23:02 +0800 Message-Id: <20240228122301.2506029-1-kito.cheng@sifive.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_NUMSUBJECT, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org atomic_compare_and_swapsi will use lr.w and sc.w to do the atomic operation on RV64, however lr.w is doing sign extend to DI and compare instruction only have DI mode on RV64, so the expected value should be sign extend before compare as well, so that we can get right compare result. gcc/ChangeLog: PR target/114130 * config/riscv/sync.md (atomic_compare_and_swap): Sign extend the expected value if needed. gcc/testsuite/ChangeLog: * gcc.target/riscv/pr114130.c: New. Reviewed-by: Palmer Dabbelt --- gcc/config/riscv/sync.md | 9 +++++++++ gcc/testsuite/gcc.target/riscv/pr114130.c | 12 ++++++++++++ 2 files changed, 21 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/pr114130.c diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index 54bb0a66518..6f0b5aae08d 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -353,6 +353,15 @@ (match_operand:SI 7 "const_int_operand" "")] ;; mod_f "TARGET_ATOMIC" { + if (word_mode != mode && operands[3] != const0_rtx) + { + /* We don't have SI mode compare on RV64, so we need to make sure expected + value is sign-extended. */ + rtx tmp0 = gen_reg_rtx (word_mode); + emit_insn (gen_extend_insn (tmp0, operands[3], word_mode, mode, 0)); + operands[3] = simplify_gen_subreg (mode, tmp0, word_mode, 0); + } + emit_insn (gen_atomic_cas_value_strong (operands[1], operands[2], operands[3], operands[4], operands[6], operands[7])); diff --git a/gcc/testsuite/gcc.target/riscv/pr114130.c b/gcc/testsuite/gcc.target/riscv/pr114130.c new file mode 100644 index 00000000000..647e27dab32 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr114130.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64" } */ +#include + +void foo(uint32_t *p) { + uintptr_t x = *(uintptr_t *)p; + uint32_t e = !p ? 0 : (uintptr_t)p >> 1; + uint32_t d = (uintptr_t)x; + __atomic_compare_exchange(p, &e, &d, 0, __ATOMIC_RELAXED, __ATOMIC_RELAXED); +} + +/* { dg-final { scan-assembler-bound {sext.w\t} >= 1 } } */