From patchwork Mon Feb 26 03:25:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 1904063 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=JB9Eamcp; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4TjmHR09n8z23qG for ; Mon, 26 Feb 2024 14:26:25 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 001D33858409 for ; Mon, 26 Feb 2024 03:26:22 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by sourceware.org (Postfix) with ESMTPS id 0DE8B3858D1E for ; Mon, 26 Feb 2024 03:26:04 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 0DE8B3858D1E Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 0DE8B3858D1E Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=192.198.163.12 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1708917966; cv=none; b=ZCy1AR9OXcPDJB7hqmosYXlCCY2nG2vvhRKFHLdAsCcCVWGZl49CQuDuxolmourO8I6R4ctT3pjMdx7a4kGkJx5WVDKgdjNU007IANEUuI5c8pQefF2cHDLXmsx6Dv/sW2ygK8C+y+ABTQTUXsxs+vFWQnlzg7Nx0HJn+lUqe90= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1708917966; c=relaxed/simple; bh=3tRWlaPDPWq6AzRO9JXmhS4L2b/4xkAT1UO2hyWOxaE=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=MHc7Hj/POMY51prvUt4I0HIASGOURAHSPRx4fgbGuwwsj2bvj6UJnMfR1b4piE9OqcwAiTF8ODkf039emDdXvU76eu6tK7aneZBrPXIK5N9XeOgpfBkfVqwO2ktX7e4rrqLny/UGKymqHxYHMEeOI+eHvp2F/x2BxcAxRhpF45c= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1708917965; x=1740453965; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=3tRWlaPDPWq6AzRO9JXmhS4L2b/4xkAT1UO2hyWOxaE=; b=JB9EamcptyfGgzal/xWixqcAKP7TMCx2nbOHD5TqwNiwg1LJcYzde+u0 GZdQrz98+cV3Bdz8prTkiectQEVpMpdzYS7rIEePPilNCz7cUDf7zXAgJ c8hYAMbMBWKCBmPsd+igZPZukyGKUt4bmcDuQz+B+zIdkrWKsH6dDtDQ+ IGwoTG9ZzMP9/ak4jSydnMwkHtK7nMhQhcyFGaxzHSqibyrRR1LoWQFnc Nc0pFdLvDB6ghiuSIdS4qz9OLlfU0p2JyAuBqdS242tE8kk45VGNefKoQ NLFia+RDi8nHFwgPvA66bGJaISG5cbfu6xlYHcHh44ah/BoeM+5cPkExW Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10995"; a="6971916" X-IronPort-AV: E=Sophos;i="6.06,185,1705392000"; d="scan'208";a="6971916" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Feb 2024 19:26:03 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.06,185,1705392000"; d="scan'208";a="11307211" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orviesa005.jf.intel.com with ESMTP; 25 Feb 2024 19:26:01 -0800 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 95C6F1005668; Mon, 26 Feb 2024 11:25:59 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, richard.guenther@gmail.com, yanzhang.wang@intel.com, rdapp.gcc@gmail.com, Pan Li Subject: [PATCH v1] RTL: Bugfix ICE after allow vector type in DSE Date: Mon, 26 Feb 2024 11:25:58 +0800 Message-Id: <20240226032558.587912-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li We allowed vector type for get_stored_val when read is less than or equal to store in previous. Unfortunately, we missed to adjust the validate_subreg part accordingly. For vector type, we don't need to restrict the mode size is greater than the vector register size. Thus, for example when gen_lowpart from E_V2SFmode to E_V4QImode, it will have NULL_RTX(of course ICE after that) because of the mode size is less than vector register size. That also explain that gen_lowpart from E_V8SFmode to E_V16QImode is valid here. This patch would like to remove the the restriction for vector mode, to rid of the ICE when gen_lowpart because of validate_subreg fails. The below test are passed for this patch: * The X86 bootstrap test. * The fully riscv regression tests. gcc/ChangeLog: * emit-rtl.cc (validate_subreg): Bypass register size check if the mode is vector. gcc/testsuite/ChangeLog: * gcc.dg/tree-ssa/ssa-fre-44.c: Add ftree-vectorize to trigger the ICE. * gcc.target/riscv/rvv/base/bug-6.c: New test. Signed-off-by: Pan Li --- gcc/emit-rtl.cc | 3 ++- gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-44.c | 2 +- .../gcc.target/riscv/rvv/base/bug-6.c | 22 +++++++++++++++++++ 3 files changed, 25 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/bug-6.c diff --git a/gcc/emit-rtl.cc b/gcc/emit-rtl.cc index 1856fa4884f..45c6301b487 100644 --- a/gcc/emit-rtl.cc +++ b/gcc/emit-rtl.cc @@ -934,7 +934,8 @@ validate_subreg (machine_mode omode, machine_mode imode, ; /* ??? Similarly, e.g. with (subreg:DF (reg:TI)). Though store_bit_field is the culprit here, and not the backends. */ - else if (known_ge (osize, regsize) && known_ge (isize, osize)) + else if (known_ge (isize, osize) && (known_ge (osize, regsize) + || (VECTOR_MODE_P (imode) || VECTOR_MODE_P (omode)))) ; /* Allow component subregs of complex and vector. Though given the below extraction rules, it's not always clear what that means. */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-44.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-44.c index f79b4c142ae..624a00a4f32 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-44.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-44.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O -fdump-tree-fre1" } */ +/* { dg-options "-O -fdump-tree-fre1 -O3 -ftree-vectorize" } */ struct A { float x, y; }; struct B { struct A u; }; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-6.c new file mode 100644 index 00000000000..5bb00b8f587 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-6.c @@ -0,0 +1,22 @@ +/* Test that we do not have ice when compile */ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize" } */ + +struct A { float x, y; }; +struct B { struct A u; }; + +extern void bar (struct A *); + +float +f3 (struct B *x, int y) +{ + struct A p = {1.0f, 2.0f}; + struct A *q = &x[y].u; + + __builtin_memcpy (&q->x, &p.x, sizeof (float)); + __builtin_memcpy (&q->y, &p.y, sizeof (float)); + + bar (&p); + + return x[y].u.x + x[y].u.y; +}