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Wed, 14 Feb 2024 23:15:36 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 41ENFaTn004731 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 14 Feb 2024 23:15:36 GMT Received: from hu-apinski-lv.qualcomm.com (10.49.16.6) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 14 Feb 2024 15:15:35 -0800 From: Andrew Pinski To: CC: Andrew Pinski Subject: [PATCH 1/2] doc: Fix some standard named pattern documentation modes Date: Wed, 14 Feb 2024 15:15:20 -0800 Message-ID: <20240214231521.1995779-2-quic_apinski@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240214231521.1995779-1-quic_apinski@quicinc.com> References: <20240214231521.1995779-1-quic_apinski@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01b.na.qualcomm.com (10.47.209.197) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: mlnD5L0jtCdhbVLQeSul5rICPsR2J6PX X-Proofpoint-GUID: mlnD5L0jtCdhbVLQeSul5rICPsR2J6PX X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-14_15,2024-02-14_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 suspectscore=0 impostorscore=0 adultscore=0 mlxscore=0 mlxlogscore=632 malwarescore=0 spamscore=0 lowpriorityscore=0 priorityscore=1501 phishscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2401310000 definitions=main-2402140175 X-Spam-Status: No, score=-13.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Currently these use `@var{m3}` but the 3 here is a literal 3 and not part of the mode itself so it should not be inside the var. Fixed as such. Built the documentation to make sure it looks correct now. gcc/ChangeLog: * doc/md.texi (widen_ssum, widen_usum, smulhs, umulhs, smulhrs, umulhrs, sdiv_pow2): Move the 3 outside of the var. Signed-off-by: Andrew Pinski --- gcc/doc/md.texi | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index b0c61925120..274dd03d419 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -5798,19 +5798,19 @@ is of a wider mode, is computed and added to operand 3. Operand 3 is of a mode equal or wider than the mode of the absolute difference. The result is placed in operand 0, which is of the same mode as operand 3. -@cindex @code{widen_ssum@var{m3}} instruction pattern -@cindex @code{widen_usum@var{m3}} instruction pattern -@item @samp{widen_ssum@var{m3}} -@itemx @samp{widen_usum@var{m3}} +@cindex @code{widen_ssum@var{m}3} instruction pattern +@cindex @code{widen_usum@var{m}3} instruction pattern +@item @samp{widen_ssum@var{m}3} +@itemx @samp{widen_usum@var{m}3} Operands 0 and 2 are of the same mode, which is wider than the mode of operand 1. Add operand 1 to operand 2 and place the widened result in operand 0. (This is used express accumulation of elements into an accumulator of a wider mode.) -@cindex @code{smulhs@var{m3}} instruction pattern -@cindex @code{umulhs@var{m3}} instruction pattern -@item @samp{smulhs@var{m3}} -@itemx @samp{umulhs@var{m3}} +@cindex @code{smulhs@var{m}3} instruction pattern +@cindex @code{umulhs@var{m}3} instruction pattern +@item @samp{smulhs@var{m}3} +@itemx @samp{umulhs@var{m}3} Signed/unsigned multiply high with scale. This is equivalent to the C code: @smallexample narrow op0, op1, op2; @@ -5820,10 +5820,10 @@ op0 = (narrow) (((wide) op1 * (wide) op2) >> (N / 2 - 1)); where the sign of @samp{narrow} determines whether this is a signed or unsigned operation, and @var{N} is the size of @samp{wide} in bits. -@cindex @code{smulhrs@var{m3}} instruction pattern -@cindex @code{umulhrs@var{m3}} instruction pattern -@item @samp{smulhrs@var{m3}} -@itemx @samp{umulhrs@var{m3}} +@cindex @code{smulhrs@var{m}3} instruction pattern +@cindex @code{umulhrs@var{m}3} instruction pattern +@item @samp{smulhrs@var{m}3} +@itemx @samp{umulhrs@var{m}3} Signed/unsigned multiply high with round and scale. This is equivalent to the C code: @smallexample @@ -5834,10 +5834,10 @@ op0 = (narrow) (((((wide) op1 * (wide) op2) >> (N / 2 - 2)) + 1) >> 1); where the sign of @samp{narrow} determines whether this is a signed or unsigned operation, and @var{N} is the size of @samp{wide} in bits. -@cindex @code{sdiv_pow2@var{m3}} instruction pattern -@cindex @code{sdiv_pow2@var{m3}} instruction pattern -@item @samp{sdiv_pow2@var{m3}} -@itemx @samp{sdiv_pow2@var{m3}} +@cindex @code{sdiv_pow2@var{m}3} instruction pattern +@cindex @code{sdiv_pow2@var{m}3} instruction pattern +@item @samp{sdiv_pow2@var{m}3} +@itemx @samp{sdiv_pow2@var{m}3} Signed division by power-of-2 immediate. Equivalent to: @smallexample signed op0, op1; From patchwork Wed Feb 14 23:15:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Pinski X-Patchwork-Id: 1899099 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=quicinc.com header.i=@quicinc.com header.a=rsa-sha256 header.s=qcppdkim1 header.b=ETgZA8ve; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4TZvFk38NRz23yP for ; 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Wed, 14 Feb 2024 23:15:37 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 41ENFaIG003322 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 14 Feb 2024 23:15:36 GMT Received: from hu-apinski-lv.qualcomm.com (10.49.16.6) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 14 Feb 2024 15:15:36 -0800 From: Andrew Pinski To: CC: Andrew Pinski Subject: [PATCH 2/2] doc: Add documentation of which operand matches the mode of the standard pattern name [PR113508] Date: Wed, 14 Feb 2024 15:15:21 -0800 Message-ID: <20240214231521.1995779-3-quic_apinski@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240214231521.1995779-1-quic_apinski@quicinc.com> References: <20240214231521.1995779-1-quic_apinski@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01b.na.qualcomm.com (10.47.209.197) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: gc4anpwJZHRl-AKR07Yq9_VeVt9WU3cK X-Proofpoint-ORIG-GUID: gc4anpwJZHRl-AKR07Yq9_VeVt9WU3cK X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-14_14,2024-02-14_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 mlxscore=0 suspectscore=0 spamscore=0 priorityscore=1501 malwarescore=0 adultscore=0 bulkscore=0 mlxlogscore=537 clxscore=1015 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2401310000 definitions=main-2402140174 X-Spam-Status: No, score=-13.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org In some of the standard pattern names, it is not obvious which mode is being used in the pattern name. Is it operand 0, 1, or 2? Is it the wider mode or the narrower mode? This fixes that so there is no confusion by adding a sentence to some of them. Built the documentation to make sure that it builds. gcc/ChangeLog: * doc/md.texi (sdot_prod@var{m}, udot_prod@var{m}, usdot_prod@var{m}, ssad@var{m}, usad@var{m}, widen_usum@var{m}3, smulhs@var{m}3, umulhs@var{m}3, smulhrs@var{m}3, umulhrs@var{m}3): Add sentence about what the mode m is. Signed-off-by: Andrew Pinski --- gcc/doc/md.texi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 274dd03d419..33b37e79cd4 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -5746,6 +5746,7 @@ Operand 1 and operand 2 are of the same mode. Their product, which is of a wider mode, is computed and added to operand 3. Operand 3 is of a mode equal or wider than the mode of the product. The result is placed in operand 0, which is of the same mode as operand 3. +@var{m} is the mode of operand 1 and operand 2. Semantically the expressions perform the multiplication in the following signs @@ -5763,6 +5764,7 @@ Operand 1 and operand 2 are of the same mode. Their product, which is of a wider mode, is computed and added to operand 3. Operand 3 is of a mode equal or wider than the mode of the product. The result is placed in operand 0, which is of the same mode as operand 3. +@var{m} is the mode of operand 1 and operand 2. Semantically the expressions perform the multiplication in the following signs @@ -5779,6 +5781,7 @@ Operand 1 must be unsigned and operand 2 signed. Their product, which is of a wider mode, is computed and added to operand 3. Operand 3 is of a mode equal or wider than the mode of the product. The result is placed in operand 0, which is of the same mode as operand 3. +@var{m} is the mode of operand 1 and operand 2. Semantically the expressions perform the multiplication in the following signs @@ -5797,6 +5800,7 @@ Operand 1 and operand 2 are of the same mode. Their absolute difference, which is of a wider mode, is computed and added to operand 3. Operand 3 is of a mode equal or wider than the mode of the absolute difference. The result is placed in operand 0, which is of the same mode as operand 3. +@var{m} is the mode of operand 1 and operand 2. @cindex @code{widen_ssum@var{m}3} instruction pattern @cindex @code{widen_usum@var{m}3} instruction pattern @@ -5806,6 +5810,7 @@ Operands 0 and 2 are of the same mode, which is wider than the mode of operand 1. Add operand 1 to operand 2 and place the widened result in operand 0. (This is used express accumulation of elements into an accumulator of a wider mode.) +@var{m} is the mode of operand 1. @cindex @code{smulhs@var{m}3} instruction pattern @cindex @code{umulhs@var{m}3} instruction pattern @@ -5819,6 +5824,8 @@ op0 = (narrow) (((wide) op1 * (wide) op2) >> (N / 2 - 1)); @end smallexample where the sign of @samp{narrow} determines whether this is a signed or unsigned operation, and @var{N} is the size of @samp{wide} in bits. +@var{m} is the mode for all 3 operands (narrow). The wide mode is not specified +and is defined to fit the whole multiply. @cindex @code{smulhrs@var{m}3} instruction pattern @cindex @code{umulhrs@var{m}3} instruction pattern @@ -5833,6 +5840,8 @@ op0 = (narrow) (((((wide) op1 * (wide) op2) >> (N / 2 - 2)) + 1) >> 1); @end smallexample where the sign of @samp{narrow} determines whether this is a signed or unsigned operation, and @var{N} is the size of @samp{wide} in bits. +@var{m} is the mode for all 3 operands (narrow). The wide mode is not specified +and is defined to fit the whole multiply. @cindex @code{sdiv_pow2@var{m}3} instruction pattern @cindex @code{sdiv_pow2@var{m}3} instruction pattern