From patchwork Thu Feb 1 23:02:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 1894237 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20230601 header.b=CHtRVgne; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4TQvb00mpzz1yhq for ; Fri, 2 Feb 2024 10:03:24 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 180CB385801E for ; Thu, 1 Feb 2024 23:03:22 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pl1-x631.google.com (mail-pl1-x631.google.com [IPv6:2607:f8b0:4864:20::631]) by sourceware.org (Postfix) with ESMTPS id 989EB3858D33 for ; Thu, 1 Feb 2024 23:02:50 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 989EB3858D33 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 989EB3858D33 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::631 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1706828573; cv=none; b=rmly0T9NTuCK3b2l2e3wLbnvi6ecQ+oTo+ulHAcfYdS+lsZIDWxgWqMuC1y7VMqmJR+eJzbV4HWwHX6O6AKrz+OHECQLExJurXstDpPEDIgjwBem/VnXJK/v8rr6l/Gc2eCOhdsmxL6wevQqC7EIovqbuY/RsZYB6lJNy7oxr3g= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1706828573; c=relaxed/simple; bh=SI/6Do72IDiP4tySQ71MPGBoRCqhPaTbL6NxMQg5758=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=TrOJISw0CBrGA7t1qgcZl9jUIsSHVnKNG3dtY/2eWKBR1pHVkwMFPS4sH+agP5nHq/aqOJ0fz+EaJzrLLWIVw4O50t/MopPs9qCf6GJuf32Oj5ruzDJxOniSKLkFDB4IRV3YQjfz8a8uDuZRvWkEErj+xm8GpJ+KkUZfdD0zO1Q= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-pl1-x631.google.com with SMTP id d9443c01a7336-1d958e0d73dso1725345ad.1 for ; Thu, 01 Feb 2024 15:02:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1706828569; x=1707433369; darn=gcc.gnu.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=L0EvOHtlYK/XQ6YQ2aFPgpYm7Qk3guwXCGuiPTxzKxk=; b=CHtRVgnebnoxWJyJpU6CF0Yb1WXrQrdYKQVSJk5Bcha/sRSKP3ko50t1dhdzbFg92+ EsSlukryZBj7V9aGE3qNX465aOofgKu+VFjmwJmj5rJYG8juMC3DmUPnwA2VkiiExJrB bEU/PKlHIWPP9VMJo6zpPVkW2jT53khsJNk5IawWJpXO97J1mInRmJNiJMUmLwTVFyXT bN45qNfT8pn/gFmYNKwZQsVp3zKCzhj5o6AUkS6exmsSF9tfXrD8cInD8j8ZgNDohdSY 7VugYirj2KnRumRAO/0PYZhdOortsE7LPm4uaMDb2HN2dt8Koj3rb3On57VUzBkjG1EM cbFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706828569; x=1707433369; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=L0EvOHtlYK/XQ6YQ2aFPgpYm7Qk3guwXCGuiPTxzKxk=; b=mYNB8dYtRx2d1Q9mq5xw/SByhTEO4fHaaTvib9uC6jE1OdRb6UFMM5zhLUt4VbRPCa /G9WDuWJt9x7AM/KRGt7B5VZe6ySuVEaZZjaKZu332Rvc9hx2Kv3v81/HrFlmqhaocX8 zR1CwkJphTTiM/XI0ShFaNoGx4tmna+vg5hinC2eAcVB/z1qtFaPIxTMAcvoUpNUleZg 9JUKVRLTWls255kpEz4tySg0V0VzqJ4n+gPdXblGsG943mqmDGf+crvVyJsBX746Qcts /UadX4f07dq5CIIUOhPr1mIA+R6ixICLfEb8olFr2IJApcnZacRLcMyMXn+y6vXS77Sb 9zpg== X-Gm-Message-State: AOJu0YzXXE7i8WMcV3xAftzt99+D/SqIfH8ZaQHq8ZzzTsIax+1TFX+8 oX3p2JG1XdoiEux+gZONTl06HTFn72MkuFJoA4nLgC6FW+y2SXUpOnM7WlEm X-Google-Smtp-Source: AGHT+IFgOi74RxAcshXaRJWz1ffk7BHxgl4mVMh5egU71ZHJjs21kLI/8u8KTm/ekXwIkmyvdMdXZQ== X-Received: by 2002:a17:902:c94a:b0:1d4:e6d0:34db with SMTP id i10-20020a170902c94a00b001d4e6d034dbmr575003pla.19.1706828568975; Thu, 01 Feb 2024 15:02:48 -0800 (PST) Received: from gnu-cfl-3.localdomain ([172.56.169.51]) by smtp.gmail.com with ESMTPSA id j3-20020a170902f24300b001d714a1530bsm331308plc.176.2024.02.01.15.02.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Feb 2024 15:02:48 -0800 (PST) Received: from gnu-cfl-3.. (localhost [IPv6:::1]) by gnu-cfl-3.localdomain (Postfix) with ESMTP id 2899F740270; Thu, 1 Feb 2024 15:02:47 -0800 (PST) From: "H.J. Lu" To: gcc-patches@gcc.gnu.org Cc: jakub@redhat.com Subject: [PATCH v2] x86-64: Find a scratch register for large model profiling Date: Thu, 1 Feb 2024 15:02:47 -0800 Message-ID: <20240201230247.214664-1-hjl.tools@gmail.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-Spam-Status: No, score=-3023.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Changes in v2: 1. Add int_parameter_registers to machine_function to track integer registers used for parameter passing. 2. Update x86_64_select_profile_regnum to try %r10 first and use an caller-saved register, which isn't used for parameter passing. --- 2 scratch registers, %r10 and %r11, are available at function entry for large model profiling. But %r10 may be used by stack realignment and we can't use %r10 in this case. Add x86_64_select_profile_regnum to find an caller-saved register, which isn't used for parameter passing, for large model profiling and sorry if we can't find one. gcc/ PR target/113689 * config/i386/i386.cc (set_int_parameter_registers_bit): New. (test_int_parameter_registers_bit): Likewise. (x86_64_select_profile_regnum): New. (construct_container): Call set_int_parameter_registers_bit for integer register parameter passing. (function_arg_32): Likewise. (x86_function_profiler): Call x86_64_select_profile_regnum to get a scratch register for large model profiling. * config/i386/i386.h (machine_function): Add int_parameter_registers. gcc/testsuite/ PR target/113689 * gcc.target/i386/pr113689-1.c: New file. * gcc.target/i386/pr113689-2.c: Likewise. * gcc.target/i386/pr113689-3.c: Likewise. --- gcc/config/i386/i386.cc | 122 ++++++++++++++++++--- gcc/config/i386/i386.h | 5 + gcc/testsuite/gcc.target/i386/pr113689-1.c | 49 +++++++++ gcc/testsuite/gcc.target/i386/pr113689-2.c | 41 +++++++ gcc/testsuite/gcc.target/i386/pr113689-3.c | 24 ++++ 5 files changed, 225 insertions(+), 16 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr113689-1.c create mode 100644 gcc/testsuite/gcc.target/i386/pr113689-2.c create mode 100644 gcc/testsuite/gcc.target/i386/pr113689-3.c diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc index b3e7c74846e..d0538f138e9 100644 --- a/gcc/config/i386/i386.cc +++ b/gcc/config/i386/i386.cc @@ -2628,6 +2628,32 @@ classify_argument (machine_mode mode, const_tree type, return n; } +/* Set the integer register REGNO bit in int_parameter_registers. */ + +static void +set_int_parameter_registers_bit (int regno) +{ + if (LEGACY_INT_REGNO_P (regno)) + cfun->machine->int_parameter_registers |= 1 << regno; + else + cfun->machine->int_parameter_registers + |= 1 << (regno - FIRST_REX_INT_REG + 8); +} + +/* Return true if the integer register REGNO bit in + int_parameter_registers is set. */ + +static bool +test_int_parameter_registers_bit (int regno) +{ + if (LEGACY_INT_REGNO_P (regno)) + return (cfun->machine->int_parameter_registers + & (1 << regno)) != 0; + else + return (cfun->machine->int_parameter_registers + & (1 << (regno - FIRST_REX_INT_REG + 8))) != 0; +} + /* Examine the argument and return set number of register required in each class. Return true iff parameter should be passed in memory. */ @@ -2763,6 +2789,8 @@ construct_container (machine_mode mode, machine_mode orig_mode, { case X86_64_INTEGER_CLASS: case X86_64_INTEGERSI_CLASS: + if (!in_return) + set_int_parameter_registers_bit (intreg[0]); return gen_rtx_REG (mode, intreg[0]); case X86_64_SSE_CLASS: case X86_64_SSEHF_CLASS: @@ -2821,6 +2849,11 @@ construct_container (machine_mode mode, machine_mode orig_mode, if (mode == BLKmode) { /* Use TImode for BLKmode values in 2 integer registers. */ + if (!in_return) + { + set_int_parameter_registers_bit (intreg[0]); + set_int_parameter_registers_bit (intreg[1]); + } exp[0] = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (TImode, intreg[0]), GEN_INT (0)); @@ -2829,7 +2862,11 @@ construct_container (machine_mode mode, machine_mode orig_mode, return ret; } else - return gen_rtx_REG (mode, intreg[0]); + { + if (!in_return) + set_int_parameter_registers_bit (intreg[0]); + return gen_rtx_REG (mode, intreg[0]); + } } /* Otherwise figure out the entries of the PARALLEL. */ @@ -2860,6 +2897,8 @@ construct_container (machine_mode mode, machine_mode orig_mode, = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (tmpmode, *intreg), GEN_INT (i*8)); + if (!in_return) + set_int_parameter_registers_bit (*intreg); intreg++; break; case X86_64_SSEHF_CLASS: @@ -3241,6 +3280,7 @@ pass_in_reg: if (regno == AX_REG) regno = CX_REG; } + set_int_parameter_registers_bit (regno); return gen_rtx_REG (mode, regno); } break; @@ -22749,6 +22789,38 @@ current_fentry_section (const char **name) return true; } +/* Return an caller-saved register, which isn't used for parameter + passing, at entry for profile. */ + +static int +x86_64_select_profile_regnum (bool r11_ok ATTRIBUTE_UNUSED) +{ + /* Use %r10 if it isn't used by DRAP. */ + bool r10_ok = !crtl->drap_reg || REGNO (crtl->drap_reg) != R10_REG; + if (r10_ok) + return R10_REG; + + int i; + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + if (GENERAL_REGNO_P (i) + && (r10_ok || i != R10_REG) +#ifdef NO_PROFILE_COUNTERS + && (r11_ok || i != R11_REG) +#else + && i != R11_REG +#endif + && (!REX2_INT_REGNO_P (i) || TARGET_APX_EGPR) + && !fixed_regs[i] + && call_used_regs[i] + && !test_int_parameter_registers_bit (i)) + return i; + + sorry ("no register available for profiling %<-mcmodel=large%s%>", + ix86_cmodel == CM_LARGE_PIC ? " -fPIC" : ""); + + return INVALID_REGNUM; +} + /* Output assembler code to FILE to increment profiler label # LABELNO for profiling a function entry. */ void @@ -22783,42 +22855,60 @@ x86_function_profiler (FILE *file, int labelno ATTRIBUTE_UNUSED) fprintf (file, "\tleaq\t%sP%d(%%rip), %%r11\n", LPREFIX, labelno); #endif + int scratch; + const char *reg_prefix; + const char *reg; + if (!TARGET_PECOFF) { switch (ix86_cmodel) { case CM_LARGE: - /* NB: R10 is caller-saved. Although it can be used as a - static chain register, it is preserved when calling - mcount for nested functions. */ + scratch = x86_64_select_profile_regnum (true); + reg = hi_reg_name[scratch]; + reg_prefix = LEGACY_INT_REGNO_P (scratch) ? "r" : ""; if (ASSEMBLER_DIALECT == ASM_INTEL) - fprintf (file, "1:\tmovabs\tr10, OFFSET FLAT:%s\n" - "\tcall\tr10\n", mcount_name); + fprintf (file, + "1:\tmovabs\t%s%s, OFFSET FLAT:%s\n" + "\tcall\t%s%s\n", + reg_prefix, reg, mcount_name, reg_prefix, reg); else - fprintf (file, "1:\tmovabsq\t$%s, %%r10\n\tcall\t*%%r10\n", - mcount_name); + fprintf (file, + "1:\tmovabsq\t$%s, %%%s%s\n\tcall\t*%%%s%s\n", + mcount_name, reg_prefix, reg, reg_prefix, reg); break; case CM_LARGE_PIC: #ifdef NO_PROFILE_COUNTERS + scratch = x86_64_select_profile_regnum (false); + reg = hi_reg_name[scratch]; + reg_prefix = LEGACY_INT_REGNO_P (scratch) ? "r" : ""; if (ASSEMBLER_DIALECT == ASM_INTEL) { fprintf (file, "1:movabs\tr11, " "OFFSET FLAT:_GLOBAL_OFFSET_TABLE_-1b\n"); - fprintf (file, "\tlea\tr10, 1b[rip]\n"); - fprintf (file, "\tadd\tr10, r11\n"); + fprintf (file, "\tlea\t%s%s, 1b[rip]\n", + reg_prefix, reg); + fprintf (file, "\tadd\t%s%s, r11\n", + reg_prefix, reg); fprintf (file, "\tmovabs\tr11, OFFSET FLAT:%s@PLTOFF\n", mcount_name); - fprintf (file, "\tadd\tr10, r11\n"); - fprintf (file, "\tcall\tr10\n"); + fprintf (file, "\tadd\t%s%s, r11\n", + reg_prefix, reg); + fprintf (file, "\tcall\t%s%s\n", + reg_prefix, reg); break; } fprintf (file, "1:\tmovabsq\t$_GLOBAL_OFFSET_TABLE_-1b, %%r11\n"); - fprintf (file, "\tleaq\t1b(%%rip), %%r10\n"); - fprintf (file, "\taddq\t%%r11, %%r10\n"); + fprintf (file, "\tleaq\t1b(%%rip), %%%s%s\n", + reg_prefix, reg); + fprintf (file, "\taddq\t%%r11, %%%s%s\n", + reg_prefix, reg); fprintf (file, "\tmovabsq\t$%s@PLTOFF, %%r11\n", mcount_name); - fprintf (file, "\taddq\t%%r11, %%r10\n"); - fprintf (file, "\tcall\t*%%r10\n"); + fprintf (file, "\taddq\t%%r11, %%%s%s\n", + reg_prefix, reg); + fprintf (file, "\tcall\t*%%%s%s\n", + reg_prefix, reg); #else sorry ("profiling %<-mcmodel=large%> with PIC is not supported"); #endif diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index 35ce8b00d36..7967bc5196c 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -2847,6 +2847,11 @@ struct GTY(()) machine_function { /* True if red zone is used. */ BOOL_BITFIELD red_zone_used : 1; + /* Bit mask for integer registers used for parameter passing. + The lower 8 bits are for legacy registers and the upper + 8 bits are for r8-r15. */ + unsigned int int_parameter_registers : 16; + /* The largest alignment, in bytes, of stack slot actually used. */ unsigned int max_used_stack_alignment; diff --git a/gcc/testsuite/gcc.target/i386/pr113689-1.c b/gcc/testsuite/gcc.target/i386/pr113689-1.c new file mode 100644 index 00000000000..c32445e0fc4 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr113689-1.c @@ -0,0 +1,49 @@ +/* { dg-do run { target { lp64 && fpic } } } */ +/* { dg-options "-O2 -fno-pic -fprofile -mcmodel=large" } */ + +#include + +__attribute__((noipa,noclone,noinline)) +void +bar (int a1, int a2, int a3, int a4, int a5, int a6, + char *x, char *y, int *z) +{ + if (a1 != 1) + __builtin_abort (); + if (a2 != 2) + __builtin_abort (); + if (a3 != 3) + __builtin_abort (); + if (a4 != 4) + __builtin_abort (); + if (a5 != 5) + __builtin_abort (); + if (a6 != 6) + __builtin_abort (); + x[0] = 42; + y[0] = 42; + if (z[0] != 16) + __builtin_abort (); +} + +__attribute__((noipa,noclone,noinline)) +void +foo (int c, int d, int e, int f, int g, int h, int z, ...) +{ + typedef char B[32]; + B b __attribute__((aligned (32))); + va_list ap; + va_start (ap, z); + int x = va_arg (ap, int); + if (x != 38) + __builtin_abort (); + bar (c, d, e, f, g, h, &b[0], __builtin_alloca (z), &z); + va_end (ap); +} + +int +main () +{ + foo (1, 2, 3, 4, 5, 6, 16, 38); + return 0; +} diff --git a/gcc/testsuite/gcc.target/i386/pr113689-2.c b/gcc/testsuite/gcc.target/i386/pr113689-2.c new file mode 100644 index 00000000000..fec5b171a39 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr113689-2.c @@ -0,0 +1,41 @@ +/* { dg-do run { target { lp64 && fpic } } } */ +/* { dg-options "-O2 -fpic -fprofile -mcmodel=large" } */ + +__attribute__((noipa,noclone,noinline)) +void +bar (int a1, int a2, int a3, int a4, int a5, int a6, + char *x, char *y, int *z) +{ + if (a1 != 1) + __builtin_abort (); + if (a2 != 2) + __builtin_abort (); + if (a3 != 3) + __builtin_abort (); + if (a4 != 4) + __builtin_abort (); + if (a5 != 5) + __builtin_abort (); + if (a6 != 6) + __builtin_abort (); + x[0] = 42; + y[0] = 42; + if (z[0] != 16) + __builtin_abort (); +} + +__attribute__((noipa,noclone,noinline)) +void +foo (int c, int d, int e, int f, int g, int h, int z) +{ + typedef char B[32]; + B b __attribute__((aligned (32))); + bar (c, d, e, f, g, h, &b[0], __builtin_alloca (z), &z); +} + +int +main () +{ + foo (1, 2, 3, 4, 5, 6, 16); + return 0; +} diff --git a/gcc/testsuite/gcc.target/i386/pr113689-3.c b/gcc/testsuite/gcc.target/i386/pr113689-3.c new file mode 100644 index 00000000000..10099fc8d96 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr113689-3.c @@ -0,0 +1,24 @@ +/* { dg-do run { target { lp64 && avx_runtime } } } */ +/* { dg-options "-O2 -fprofile -mcmodel=large -mavx" } */ + +__attribute__((noipa,noclone,noinline)) +_BitInt(511) +foo(_BitInt(7) a, _BitInt(511) b) +{ + ({ + volatile _BitInt(511) d = (-b / a); + if (d != -1) + __builtin_abort(); + d; + }); + return b; +} + +int +main(void) +{ + _BitInt(511) x = foo(5, 5); + if (x != 5) + __builtin_abort(); + return 0; +}