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Wed, 31 Jan 2024 09:46:01 +0100 (CET) Received: from llp-hahn.hahn.test (172.25.0.11) by Berlix.phytec.de (172.25.0.12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.6; Wed, 31 Jan 2024 09:46:00 +0100 From: Benjamin Hahn Date: Wed, 31 Jan 2024 09:45:37 +0100 Subject: [PATCH v2 1/4] imx8mp-phyboard-pollux-rdk: sync with kernel devicetree from v6.8-rc2 MIME-Version: 1.0 Message-ID: <20240131-usb_support-v2-1-7521c554b597@phytec.de> References: <20240131-usb_support-v2-0-7521c554b597@phytec.de> In-Reply-To: <20240131-usb_support-v2-0-7521c554b597@phytec.de> To: Stefano Babic , Fabio Estevam , NXP i.MX U-Boot Team , Teresa Remmet , Tom Rini CC: , , Benjamin Hahn X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1706690760; l=5229; i=B.Hahn@phytec.de; s=20240126; h=from:subject:message-id; bh=eVFHJvtghKo5F0TpB1WY/m6pWa9zA4PiqeKziUCKaAc=; b=AzjTUQe8MnWKx4b2UGw3Xu+XcDhqQ75tI1KC4rJUf1m2MdwNZZuPJ3vfZZ+mynb5g3E+MnQDZ /6oUsXVmWK/BThZZWhP0Mw2C5UFq8LOsPZEX4HyLCXsUjrOwkP7nriv X-Developer-Key: i=B.Hahn@phytec.de; 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}; + reg_can1_stby: regulator-can1-stby { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1_reg>; + gpio = <&gpio3 20 GPIO_ACTIVE_LOW>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "can1-stby"; + }; + + reg_can2_stby: regulator-can2-stby { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2_reg>; + gpio = <&gpio3 21 GPIO_ACTIVE_LOW>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "can2-stby"; + }; + + reg_usb1_vbus: regulator-usb1-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1_vbus>; + gpio = <&gpio1 12 GPIO_ACTIVE_LOW>; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "usb1_host_vbus"; + }; + reg_usdhc2_vmmc: regulator-usdhc2 { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -57,6 +87,21 @@ }; }; +/* CAN FD */ +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can1_stby>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can2_stby>; + status = "okay"; +}; + &i2c2 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; @@ -76,15 +121,15 @@ compatible = "nxp,pca9533"; reg = <0x62>; - led1 { + led-1 { type = ; }; - led2 { + led-2 { type = ; }; - led3 { + led-3 { type = ; }; }; @@ -101,8 +146,51 @@ status = "okay"; }; +/* USB1 Host mode Type-A */ +&usb3_phy0 { + vbus-supply = <®_usb1_vbus>; + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "host"; + status = "okay"; +}; + +/* USB2 4-port USB3.0 HUB */ +&usb3_phy1 { + status = "okay"; +}; + +&usb3_1 { + fsl,permanently-attached; + fsl,disable-port-power-control; + status = "okay"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +/* RS232/RS485 */ +&uart2 { + assigned-clocks = <&clk IMX8MP_CLK_UART2>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; + status = "okay"; +}; + /* SD-Card */ &usdhc2 { + assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; + assigned-clock-rates = <200000000>; pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_pins>; pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_pins>; @@ -113,6 +201,33 @@ status = "okay"; }; +&gpio1 { + gpio-line-names = "", "", "X_PMIC_WDOG_B", "", + "PMIC_SD_VSEL", "", "", "", "", "", + "", "", "USB1_OTG_PWR", "", "", "X_nETHPHY_INT"; +}; + +&gpio2 { + gpio-line-names = "", "", "", "", + "", "", "", "", "", "", + "", "", "X_SD2_CD_B", "", "", "", + "", "", "", "SD2_RESET_B"; +}; + +&gpio3 { + gpio-line-names = "", "", "", "", + "", "", "", "", "", "", + "", "", "", "", "", "", + "", "", "", "", "nCAN1_EN", "nCAN2_EN"; +}; + +&gpio4 { + gpio-line-names = "", "", "", "", + "", "", "", "", "", "", + "", "", "", "", "", "", + "", "", "X_PMIC_IRQ_B", "", "nENET0_INT_PWDN"; +}; + &iomuxc { pinctrl_eqos: eqosgrp { fsl,pins = < @@ -134,6 +249,32 @@ >; }; + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x154 + MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x154 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 + MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 + >; + }; + + pinctrl_flexcan1_reg: flexcan1reggrp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x154 + >; + }; + + pinctrl_flexcan2_reg: flexcan2reggrp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x154 + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 @@ -161,6 +302,21 @@ >; }; + pinctrl_usb1_vbus: usb1vbusgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x10 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 + MX8MP_IOMUXC_SAI3_RXC__UART2_DCE_CTS 0x140 + MX8MP_IOMUXC_SAI3_RXD__UART2_DCE_RTS 0x140 + >; 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Add support for USB host and USB storage for the USB1 port. Signed-off-by: Benjamin Hahn --- configs/phycore-imx8mp_defconfig | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig index 519e0cfb3d..74450b957b 100644 --- a/configs/phycore-imx8mp_defconfig +++ b/configs/phycore-imx8mp_defconfig @@ -65,6 +65,7 @@ CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y @@ -104,6 +105,7 @@ CONFIG_DM_ETH_PHY=y CONFIG_FEC_MXC=y CONFIG_RGMII=y CONFIG_MII=y +CONFIG_PHY_IMX8MQ_USB=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_IMX8M=y @@ -120,4 +122,12 @@ CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_DM_THERMAL=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_STORAGE=y CONFIG_IMX_WATCHDOG=y From patchwork Wed Jan 31 08:45:39 2024 Content-Type: text/plain; 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Wed, 31 Jan 2024 09:46:01 +0100 (CET) Received: from llp-hahn.hahn.test (172.25.0.11) by Berlix.phytec.de (172.25.0.12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.6; Wed, 31 Jan 2024 09:46:01 +0100 From: Benjamin Hahn Date: Wed, 31 Jan 2024 09:45:39 +0100 Subject: [PATCH v2 3/4] phycore-imx8mp: add USB mass storage support MIME-Version: 1.0 Message-ID: <20240131-usb_support-v2-3-7521c554b597@phytec.de> References: <20240131-usb_support-v2-0-7521c554b597@phytec.de> In-Reply-To: <20240131-usb_support-v2-0-7521c554b597@phytec.de> To: Stefano Babic , Fabio Estevam , NXP i.MX U-Boot Team , Teresa Remmet , Tom Rini CC: , , Benjamin Hahn X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1706690760; l=1653; i=B.Hahn@phytec.de; s=20240126; h=from:subject:message-id; bh=pC2aqOGQjcXUBUu0U2ik6UHuCXn2Fs0fhyVtRc9Y4JA=; b=B9pvWiBDYk4h0boRpn6sYAzLK/gOnLb6pziV3e7jHI8WDZ01BpTL5OyyAPkyIac4DD2ijTLZD nh8dgwpddfkCqdxow/htdg9PG5SVcIMUrZF4R6bV3e4bhd1GKGGU4sE X-Developer-Key: i=B.Hahn@phytec.de; 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}; +&usb_dwc3_0 { + dr_mode = "peripheral"; +}; + &usdhc2 { bootph-pre-ram; }; diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig index 74450b957b..e3fe4ed94e 100644 --- a/configs/phycore-imx8mp_defconfig +++ b/configs/phycore-imx8mp_defconfig @@ -66,6 +66,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y @@ -123,6 +124,7 @@ CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_DM_THERMAL=y CONFIG_USB=y +CONFIG_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y @@ -130,4 +132,9 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_IMX_WATCHDOG=y From patchwork Wed Jan 31 08:45:40 2024 Content-Type: text/plain; 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Reviewed-by: Fabio Estevam Signed-off-by: Benjamin Hahn --- board/phytec/phycore_imx8mp/phycore-imx8mp.c | 4 ++++ configs/phycore-imx8mp_defconfig | 18 ++++++++++++++++-- include/configs/phycore_imx8mp.h | 5 +++++ 3 files changed, 25 insertions(+), 2 deletions(-) diff --git a/board/phytec/phycore_imx8mp/phycore-imx8mp.c b/board/phytec/phycore_imx8mp/phycore-imx8mp.c index a8f0821437..dbdd6bb793 100644 --- a/board/phytec/phycore_imx8mp/phycore-imx8mp.c +++ b/board/phytec/phycore_imx8mp/phycore-imx8mp.c @@ -46,6 +46,10 @@ int board_late_init(void) case MMC3_BOOT: env_set_ulong("mmcdev", 2); break; + case USB_BOOT: + printf("Detect USB boot. Will enter fastboot mode!\n"); + env_set_ulong("dofastboot", 1); + break; default: break; } diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig index e3fe4ed94e..0f37286d5d 100644 --- a/configs/phycore-imx8mp_defconfig +++ b/configs/phycore-imx8mp_defconfig @@ -27,7 +27,7 @@ CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadimage; then run mmcboot; else run netboot; fi; fi;" +CONFIG_BOOTCOMMAND="if test ${dofastboot} = 1; then fastboot 0; fi; mmc dev ${mmcdev}; if mmc rescan; then if run loadimage; then run mmcboot; else run netboot; fi; fi;" CONFIG_DEFAULT_FDT_FILE="oftree" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 @@ -66,6 +66,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +CONFIG_CMD_USB_SDP=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y @@ -87,6 +88,17 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y CONFIG_CLK_COMPOSITE_CCF=y CONFIG_CLK_IMX8MP=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x13000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=2 +CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y +CONFIG_FASTBOOT_MMC_BOOT1_NAME="mmc2boot0" +CONFIG_FASTBOOT_MMC_BOOT2_NAME="mmc2boot1" +CONFIG_FASTBOOT_MMC_USER_SUPPORT=y +CONFIG_FASTBOOT_MMC_USER_NAME="mmc2" CONFIG_MXC_GPIO=y CONFIG_DM_I2C=y # CONFIG_SPL_DM_I2C is not set @@ -111,6 +123,9 @@ CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_IMX8M=y CONFIG_SPL_POWER_LEGACY=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8M_POWER_DOMAIN=y +CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y CONFIG_POWER_PCA9450=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y @@ -136,5 +151,4 @@ CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 -CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_IMX_WATCHDOG=y diff --git a/include/configs/phycore_imx8mp.h b/include/configs/phycore_imx8mp.h index d79d364c8e..11a17be7fe 100644 --- a/include/configs/phycore_imx8mp.h +++ b/include/configs/phycore_imx8mp.h @@ -19,6 +19,11 @@ "fdt_addr=0x48000000\0" \ "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ "ip_dyn=yes\0" \ + "dofastboot=0\0" \ + "fastboot_raw_partition_bootloader=64 8128\0" \ + "fastboot_raw_partition_all=0 4194304\0" \ + "emmc_dev=2\0" \ + "sd_dev=1\0" \ "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ "mmcpart=1\0" \ "mmcroot=2\0" \