From patchwork Thu Jan 25 17:45:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Andre Vieira (lists)" X-Patchwork-Id: 1890941 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4TLSsp5wdbz1yS7 for ; Fri, 26 Jan 2024 04:45:50 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id CE96438582BF for ; Thu, 25 Jan 2024 17:45:48 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 2E42A3858427 for ; Thu, 25 Jan 2024 17:45:29 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 2E42A3858427 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 2E42A3858427 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1706204730; cv=none; b=MZE57YCT2IOxTsPrGfqQXwhtljO0Olf+COx1mryb/7CQF7fHrdiPguootNxXbDUCCybu6Bu9he5p68s4tK5jExWZQytpoMfMXAhbpPgy6cfSeLbLorMC0rxzMAkb8gx1FTEmu50SzMgCyzaFv2HU4oF06xpYWnY/r0RTtBXD5QQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1706204730; c=relaxed/simple; bh=p6/9EUYO8rIr21t8Ylisx7lfhuAP0tJFGdLnzRExgdY=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=EiH3H81TOdhRGtCsT+pThCR78R8YYUF+J9GRDh3rZZCWcnbiOdSQxOd5rtLn70ubBN4sb3tKIINfSOC5PDYBxVtUJhLXY7+Ba1J8uqYKZb7vP5xCEk9rpnA9az8NJYISxyMvJRGxWozpE0YhO3NQ5PyXPbJzJForJZWZfXhfqRY= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 44B7F1FB; Thu, 25 Jan 2024 09:46:13 -0800 (PST) Received: from e107157-lin.cambridge.arm.com (e107157-lin.cambridge.arm.com [10.2.78.70]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 167223F73F; Thu, 25 Jan 2024 09:45:27 -0800 (PST) From: Andre Vieira To: gcc-patches@gcc.gnu.org Cc: Richard.Sandiford@arm.com, Jakub@redhat.com, kyrylo.tkachov@arm.com, Andre Vieira Subject: [PATCH 1/2] bitint: Use TARGET_ARRAY_MODE for large bitints where target supports it Date: Thu, 25 Jan 2024 17:45:00 +0000 Message-Id: <20240125174501.32634-2-andre.simoesdiasvieira@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240125174501.32634-1-andre.simoesdiasvieira@arm.com> References: <20240125174501.32634-1-andre.simoesdiasvieira@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-13.1 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org This patch ensures we use TARGET_ARRAY_MODE to determine the storage mode of large bitints that are represented as arrays in memory. This is required to support such bitints for aarch64 and potential other targets with similar bitint specifications. Existing tests like gcc.dg/torture/bitint-25.c are affected by this for aarch64 targets. gcc/ChangeLog: stor-layout.cc (layout_type): Use TARGET_ARRAY_MODE for large bitints for targets that implement it. --- gcc/stor-layout.cc | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/gcc/stor-layout.cc b/gcc/stor-layout.cc index 4cf249133e9..31da2c123ab 100644 --- a/gcc/stor-layout.cc +++ b/gcc/stor-layout.cc @@ -2427,8 +2427,16 @@ layout_type (tree type) } else { - SET_TYPE_MODE (type, BLKmode); cnt = CEIL (TYPE_PRECISION (type), GET_MODE_PRECISION (limb_mode)); + machine_mode mode; + /* Some targets use TARGET_ARRAY_MODE to select the mode they use + for arrays with a specific element mode and a specific element + count and we should use this mode for large bitints that are + stored as such arrays. */ + if (!targetm.array_mode (limb_mode, cnt).exists (&mode) + || !targetm.array_mode_supported_p (limb_mode, cnt)) + mode = BLKmode; + SET_TYPE_MODE (type, mode); gcc_assert (info.abi_limb_mode == info.limb_mode || !info.big_endian == !WORDS_BIG_ENDIAN); } From patchwork Thu Jan 25 17:45:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Andre Vieira (lists)" X-Patchwork-Id: 1890942 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4TLSsw0mDGz1yS7 for ; Fri, 26 Jan 2024 04:45:56 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 285843858014 for ; Thu, 25 Jan 2024 17:45:54 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id C2D873858008 for ; Thu, 25 Jan 2024 17:45:32 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org C2D873858008 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org C2D873858008 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1706204734; cv=none; b=sYZSvnhxQLHbmg9+1TQ1oVWobASEPtHxCjy2jknJwYHmN84A7OvXwNYzpi24AiSJ79f5N5islZkdJ+9/wqKsWWRb4KoPHZ5AFqGcpVufq8q/4kDa+1YVL47TJQ5V3bsarutAC0TKg0+S8qMsk4UBFziHchutxK7pwMFM23TcuxM= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1706204734; c=relaxed/simple; bh=Ha6NkDN89jK6oZ0Bih/0l6UJOcZnSFtkvH+wXewbZ/w=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=MS+vkZnwVh+0sbu5uMIHRl0KDaOMsIJPlHLQU0QfmwvRxTj/vM9k+8V1+GW2fNni5/M6UNhskpC+fF+GXd7ds+2pNJaA7n4r8WZS/TK8C6HqVmszR9K8x1jVVHipBHZtl389v+XVJPiVBFYS4So3v9HYgYHM6hKhN1TYZHe9EiQ= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F22411FB; Thu, 25 Jan 2024 09:46:16 -0800 (PST) Received: from e107157-lin.cambridge.arm.com (e107157-lin.cambridge.arm.com [10.2.78.70]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C44C23F73F; Thu, 25 Jan 2024 09:45:31 -0800 (PST) From: Andre Vieira To: gcc-patches@gcc.gnu.org Cc: Richard.Sandiford@arm.com, Jakub@redhat.com, kyrylo.tkachov@arm.com, Andre Vieira Subject: [PATCH 2/2] aarch64: Add support for _BitInt Date: Thu, 25 Jan 2024 17:45:01 +0000 Message-Id: <20240125174501.32634-3-andre.simoesdiasvieira@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240125174501.32634-1-andre.simoesdiasvieira@arm.com> References: <20240125174501.32634-1-andre.simoesdiasvieira@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-13.1 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org This patch adds support for C23's _BitInt for the AArch64 port when compiling for little endianness. Big Endianness requires further target-agnostic support and we therefor disable it for now. gcc/ChangeLog: * config/aarch64/aarch64.cc (TARGET_C_BITINT_TYPE_INFO): Declare MACRO. (aarch64_bitint_type_info): New function. (aarch64_return_in_memory_1): Return large _BitInt's in memory. (aarch64_function_arg_alignment): Adapt to correctly return the ABI mandated alignment of _BitInt(N) where N > 128 as the alignment of TImode. (aarch64_composite_type_p): Return true for _BitInt(N), where N > 128. libgcc/ChangeLog: * config/aarch64/t-softfp: Add fixtfbitint, floatbitinttf and floatbitinthf to the softfp_extras variable to ensure the runtime support is available for _BitInt. --- gcc/config/aarch64/aarch64.cc | 44 +++++++++++++++++++++++++++++++++- libgcc/config/aarch64/t-softfp | 3 ++- 2 files changed, 45 insertions(+), 2 deletions(-) diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index e6bd3fd0bb4..48bac51bc7c 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -6534,7 +6534,7 @@ aarch64_return_in_memory_1 (const_tree type) machine_mode ag_mode; int count; - if (!AGGREGATE_TYPE_P (type) + if (!(AGGREGATE_TYPE_P (type) || TREE_CODE (type) == BITINT_TYPE) && TREE_CODE (type) != COMPLEX_TYPE && TREE_CODE (type) != VECTOR_TYPE) /* Simple scalar types always returned in registers. */ @@ -6618,6 +6618,10 @@ aarch64_function_arg_alignment (machine_mode mode, const_tree type, gcc_assert (TYPE_MODE (type) == mode); + if (TREE_CODE (type) == BITINT_TYPE + && int_size_in_bytes (type) > 16) + return GET_MODE_ALIGNMENT (TImode); + if (!AGGREGATE_TYPE_P (type)) { /* The ABI alignment is the natural alignment of the type, without @@ -21793,6 +21797,11 @@ aarch64_composite_type_p (const_tree type, if (type && (AGGREGATE_TYPE_P (type) || TREE_CODE (type) == COMPLEX_TYPE)) return true; + if (type + && TREE_CODE (type) == BITINT_TYPE + && int_size_in_bytes (type) > 16) + return true; + if (mode == BLKmode || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT) @@ -28330,6 +28339,36 @@ aarch64_excess_precision (enum excess_precision_type type) return FLT_EVAL_METHOD_UNPREDICTABLE; } +/* Implement TARGET_C_BITINT_TYPE_INFO. + Return true if _BitInt(N) is supported and fill its details into *INFO. */ +bool +aarch64_bitint_type_info (int n, struct bitint_info *info) +{ + if (TARGET_BIG_END) + return false; + + if (n <= 8) + info->limb_mode = QImode; + else if (n <= 16) + info->limb_mode = HImode; + else if (n <= 32) + info->limb_mode = SImode; + else if (n <= 64) + info->limb_mode = DImode; + else if (n <= 128) + info->limb_mode = TImode; + else + info->limb_mode = DImode; + + if (n > 128) + info->abi_limb_mode = TImode; + else + info->abi_limb_mode = info->limb_mode; + info->big_endian = TARGET_BIG_END; + info->extended = false; + return true; +} + /* Implement TARGET_SCHED_CAN_SPECULATE_INSN. Return true if INSN can be scheduled for speculative execution. Reject the long-running division and square-root instructions. */ @@ -30439,6 +30478,9 @@ aarch64_run_selftests (void) #undef TARGET_C_EXCESS_PRECISION #define TARGET_C_EXCESS_PRECISION aarch64_excess_precision +#undef TARGET_C_BITINT_TYPE_INFO +#define TARGET_C_BITINT_TYPE_INFO aarch64_bitint_type_info + #undef TARGET_EXPAND_BUILTIN #define TARGET_EXPAND_BUILTIN aarch64_expand_builtin diff --git a/libgcc/config/aarch64/t-softfp b/libgcc/config/aarch64/t-softfp index 2e32366f891..a335a34c243 100644 --- a/libgcc/config/aarch64/t-softfp +++ b/libgcc/config/aarch64/t-softfp @@ -4,7 +4,8 @@ softfp_extensions := sftf dftf hftf bfsf softfp_truncations := tfsf tfdf tfhf tfbf dfbf sfbf hfbf softfp_exclude_libgcc2 := n softfp_extras += fixhfti fixunshfti floattihf floatuntihf \ - floatdibf floatundibf floattibf floatuntibf + floatdibf floatundibf floattibf floatuntibf \ + fixtfbitint floatbitinttf floatbitinthf TARGET_LIBGCC2_CFLAGS += -Wno-missing-prototypes