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Mon, 22 Jan 2024 07:46:26 -0500 (EST) Received: by feathertop.org (sSMTP sendmail emulation); Mon, 22 Jan 2024 23:46:23 +1100 From: Tim Lunn To: u-boot@lists.denx.de Cc: Tim Lunn , Kever Yang , Philipp Tomsich , Philipp Tomsich , Simon Glass , Tom Rini Subject: [PATCH 1/5] arm: dts: rockchip: Sync rv1126 dts from linux 6.8-rc1 Date: Mon, 22 Jan 2024 23:45:59 +1100 Message-Id: <20240122124603.3341988-2-tim@feathertop.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240122124603.3341988-1-tim@feathertop.org> References: <20240122124603.3341988-1-tim@feathertop.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Sync linux dts files for rv1126 boards from linux v6.8-rc1 tag. Includes the newly added dts for Sonoff iHost. Signed-off-by: Tim Lunn --- arch/arm/dts/rv1126-edgeble-neu2-io.dts | 70 ++++ arch/arm/dts/rv1126-edgeble-neu2.dtsi | 27 +- arch/arm/dts/rv1126-pinctrl.dtsi | 130 ++++++++ arch/arm/dts/rv1126-sonoff-ihost.dts | 29 ++ arch/arm/dts/rv1126-sonoff-ihost.dtsi | 404 ++++++++++++++++++++++++ arch/arm/dts/rv1126.dtsi | 185 +++++++++++ 6 files changed, 835 insertions(+), 10 deletions(-) create mode 100644 arch/arm/dts/rv1126-sonoff-ihost.dts create mode 100644 arch/arm/dts/rv1126-sonoff-ihost.dtsi diff --git a/arch/arm/dts/rv1126-edgeble-neu2-io.dts b/arch/arm/dts/rv1126-edgeble-neu2-io.dts index dded0a12f0..0c2396b8f8 100644 --- a/arch/arm/dts/rv1126-edgeble-neu2-io.dts +++ b/arch/arm/dts/rv1126-edgeble-neu2-io.dts @@ -20,6 +20,76 @@ chosen { stdout-path = "serial2:1500000n8"; }; + + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + v3v3_sys: v3v3-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "v3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&gmac { + assigned-clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>, + <&cru CLK_GMAC_ETHERNET_OUT>; + assigned-clock-parents = <&cru CLK_GMAC_SRC_M1>, <&cru RGMII_MODE_CLK>; + assigned-clock-rates = <125000000>, <0>, <25000000>; + clock_in_out = "input"; + phy-handle = <&phy>; + phy-mode = "rgmii"; + phy-supply = <&vcc_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmiim1_miim &rgmiim1_bus2 &rgmiim1_bus4 &clk_out_ethernetm1_pins>; + tx_delay = <0x2a>; + rx_delay = <0x1a>; + status = "okay"; +}; + +&mdio { + phy: ethernet-phy@0 { + compatible = "ethernet-phy-id001c.c916", + "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + pinctrl-names = "default"; + pinctrl-0 = <ð_phy_rst>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + ethernet { + eth_phy_rst: eth-phy-rst { + rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + +&pwm11 { + status = "okay"; }; &sdmmc { diff --git a/arch/arm/dts/rv1126-edgeble-neu2.dtsi b/arch/arm/dts/rv1126-edgeble-neu2.dtsi index cc64ba4be3..7ea8d7d16f 100644 --- a/arch/arm/dts/rv1126-edgeble-neu2.dtsi +++ b/arch/arm/dts/rv1126-edgeble-neu2.dtsi @@ -11,15 +11,6 @@ mmc0 = &emmc; }; - vcc5v0_sys: vcc5v0-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - vccio_flash: vccio-flash-regulator { compatible = "regulator-fixed"; enable-active-high; @@ -52,7 +43,7 @@ bus-width = <8>; non-removable; pinctrl-names = "default"; - pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk &emmc_rstnout>; + pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk>; rockchip,default-sample-phase = <90>; vmmc-supply = <&vcc_3v3>; vqmmc-supply = <&vccio_flash>; @@ -301,6 +292,22 @@ status = "okay"; }; +&sfc { + pinctrl-names = "default"; + pinctrl-0 = <&fspi_pins>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + &sdio { bus-width = <4>; cap-sd-highspeed; diff --git a/arch/arm/dts/rv1126-pinctrl.dtsi b/arch/arm/dts/rv1126-pinctrl.dtsi index 28d8d29942..f84f5f2d96 100644 --- a/arch/arm/dts/rv1126-pinctrl.dtsi +++ b/arch/arm/dts/rv1126-pinctrl.dtsi @@ -11,6 +11,14 @@ * by adding changes at end of this file. */ &pinctrl { + clk_out_ethernet { + /omit-if-no-ref/ + clk_out_ethernetm1_pins: clk-out-ethernetm1-pins { + rockchip,pins = + /* clk_out_ethernet_m1 */ + <2 RK_PC5 2 &pcfg_pull_none>; + }; + }; emmc { /omit-if-no-ref/ emmc_rstnout: emmc-rstnout { @@ -51,6 +59,24 @@ <0 RK_PD5 2 &pcfg_pull_up_drv_level_2>; }; }; + fspi { + /omit-if-no-ref/ + fspi_pins: fspi-pins { + rockchip,pins = + /* fspi_clk */ + <1 RK_PA3 3 &pcfg_pull_down>, + /* fspi_cs0n */ + <0 RK_PD4 3 &pcfg_pull_up>, + /* fspi_d0 */ + <1 RK_PA0 3 &pcfg_pull_up>, + /* fspi_d1 */ + <1 RK_PA1 3 &pcfg_pull_up>, + /* fspi_d2 */ + <0 RK_PD6 3 &pcfg_pull_up>, + /* fspi_d3 */ + <1 RK_PA2 3 &pcfg_pull_up>; + }; + }; i2c0 { /omit-if-no-ref/ i2c0_xfer: i2c0-xfer { @@ -61,6 +87,86 @@ <0 RK_PB5 1 &pcfg_pull_none_drv_level_0_smt>; }; }; + i2c2 { + /omit-if-no-ref/ + i2c2_xfer: i2c2-xfer { + rockchip,pins = + /* i2c2_scl */ + <0 RK_PC2 1 &pcfg_pull_none_drv_level_0_smt>, + /* i2c2_sda */ + <0 RK_PC3 1 &pcfg_pull_none_drv_level_0_smt>; + }; + }; + pwm2 { + /omit-if-no-ref/ + pwm2m0_pins: pwm2m0-pins { + rockchip,pins = + /* pwm2_pin_m0 */ + <0 RK_PC0 3 &pcfg_pull_none>; + }; + }; + pwm11 { + /omit-if-no-ref/ + pwm11m0_pins: pwm11m0-pins { + rockchip,pins = + /* pwm11_pin_m0 */ + <3 RK_PA7 6 &pcfg_pull_none>; + }; + }; + rgmii { + /omit-if-no-ref/ + rgmiim1_miim: rgmiim1-miim { + rockchip,pins = + /* rgmii_mdc_m1 */ + <2 RK_PC2 2 &pcfg_pull_none>, + /* rgmii_mdio_m1 */ + <2 RK_PC1 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rgmiim1_rxer: rgmiim1-rxer { + rockchip,pins = + /* rgmii_rxer_m1 */ + <2 RK_PC0 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rgmiim1_bus2: rgmiim1-bus2 { + rockchip,pins = + /* rgmii_rxd0_m1 */ + <2 RK_PB5 2 &pcfg_pull_none>, + /* rgmii_rxd1_m1 */ + <2 RK_PB6 2 &pcfg_pull_none>, + /* rgmii_rxdv_m1 */ + <2 RK_PB4 2 &pcfg_pull_none>, + /* rgmii_txd0_m1 */ + <2 RK_PC3 2 &pcfg_pull_none_drv_level_3>, + /* rgmii_txd1_m1 */ + <2 RK_PC4 2 &pcfg_pull_none_drv_level_3>, + /* rgmii_txen_m1 */ + <2 RK_PC6 2 &pcfg_pull_none_drv_level_3>; + }; + /omit-if-no-ref/ + rgmiim1_bus4: rgmiim1-bus4 { + rockchip,pins = + /* rgmii_rxclk_m1 */ + <2 RK_PD3 2 &pcfg_pull_none>, + /* rgmii_rxd2_m1 */ + <2 RK_PC7 2 &pcfg_pull_none>, + /* rgmii_rxd3_m1 */ + <2 RK_PD0 2 &pcfg_pull_none>, + /* rgmii_txclk_m1 */ + <2 RK_PD2 2 &pcfg_pull_none_drv_level_3>, + /* rgmii_txd2_m1 */ + <2 RK_PD1 2 &pcfg_pull_none_drv_level_3>, + /* rgmii_txd3_m1 */ + <2 RK_PA4 2 &pcfg_pull_none_drv_level_3>; + }; + /omit-if-no-ref/ + rgmiim1_mclkinout: rgmiim1-mclkinout { + rockchip,pins = + /* rgmii_clk_m1 */ + <2 RK_PB7 2 &pcfg_pull_none>; + }; + }; sdmmc0 { /omit-if-no-ref/ sdmmc0_bus4: sdmmc0-bus4 { @@ -187,6 +293,14 @@ /* uart3_tx_m0 */ <3 RK_PC6 4 &pcfg_pull_up>; }; + /omit-if-no-ref/ + uart3m2_xfer: uart3m2-xfer { + rockchip,pins = + /* uart3_rx_m2 */ + <3 RK_PA1 4 &pcfg_pull_up>, + /* uart3_tx_m2 */ + <3 RK_PA0 4 &pcfg_pull_up>; + }; }; uart4 { /omit-if-no-ref/ @@ -197,6 +311,14 @@ /* uart4_tx_m0 */ <3 RK_PA4 4 &pcfg_pull_up>; }; + /omit-if-no-ref/ + uart4m2_xfer: uart4m2-xfer { + rockchip,pins = + /* uart4_rx_m2 */ + <1 RK_PD4 3 &pcfg_pull_up>, + /* uart4_tx_m2 */ + <1 RK_PD5 3 &pcfg_pull_up>; + }; }; uart5 { /omit-if-no-ref/ @@ -207,5 +329,13 @@ /* uart5_tx_m0 */ <3 RK_PA6 4 &pcfg_pull_up>; }; + /omit-if-no-ref/ + uart5m2_xfer: uart5m2-xfer { + rockchip,pins = + /* uart5_rx_m2 */ + <2 RK_PA1 3 &pcfg_pull_up>, + /* uart5_tx_m2 */ + <2 RK_PA0 3 &pcfg_pull_up>; + }; }; }; diff --git a/arch/arm/dts/rv1126-sonoff-ihost.dts b/arch/arm/dts/rv1126-sonoff-ihost.dts new file mode 100644 index 0000000000..77386a48d8 --- /dev/null +++ b/arch/arm/dts/rv1126-sonoff-ihost.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; +#include "rv1126.dtsi" +#include "rv1126-sonoff-ihost.dtsi" + +/ { + model = "Sonoff iHost 4G"; + compatible = "itead,sonoff-ihost", "rockchip,rv1126"; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; diff --git a/arch/arm/dts/rv1126-sonoff-ihost.dtsi b/arch/arm/dts/rv1126-sonoff-ihost.dtsi new file mode 100644 index 0000000000..32b329e87a --- /dev/null +++ b/arch/arm/dts/rv1126-sonoff-ihost.dtsi @@ -0,0 +1,404 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. + */ + +/ { + aliases { + ethernet0 = &gmac; + mmc0 = &emmc; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + vcc5v0_sys: regulator-vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + sdio_pwrseq: pwrseq-sdio { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + reset-gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>; + }; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk &emmc_rstnout>; + rockchip,default-sample-phase = <90>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + status = "okay"; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = ; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc_buck5>; + vcc6-supply = <&vcc_buck5>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + + regulators { + vdd_npu_vepu: DCDC_REG1 { + regulator-name = "vdd_npu_vepu"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc3v3_sys: DCDC_REG4 { + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_buck5: DCDC_REG5 { + regulator-name = "vcc_buck5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2200000>; + }; + }; + + vcc_0v8: LDO_REG1 { + regulator-name = "vcc_0v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_pmu: LDO_REG2 { + regulator-name = "vcc1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd0v8_pmu: LDO_REG3 { + regulator-name = "vcc0v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <800000>; + }; + }; + + vcc_1v8: LDO_REG4 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_dovdd: LDO_REG5 { + regulator-name = "vcc_dovdd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_dvdd: LDO_REG6 { + regulator-name = "vcc_dvdd"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_avdd: LDO_REG7 { + regulator-name = "vcc_avdd"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG8 { + regulator-name = "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: LDO_REG9 { + regulator-name = "vcc3v3_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_5v0: SWITCH_REG1 { + regulator-name = "vcc_5v0"; + }; + + vcc_3v3: SWITCH_REG2 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + +&i2c2 { + status = "okay"; + clock-frequency = <400000>; + + pcf8563: rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + #clock-cells = <0>; + interrupt-parent = <&gpio0>; + interrupts = ; + clock-output-names = "xin32k"; + }; +}; + +&gmac { + assigned-clocks = <&cru CLK_GMAC_SRC_M1>, <&cru CLK_GMAC_SRC>, + <&cru CLK_GMAC_TX_RX>; + assigned-clock-parents = <&cru CLK_GMAC_RGMII_M1>, <&cru CLK_GMAC_SRC_M1>, + <&cru RMII_MODE_CLK>; + assigned-clock-rates = <0>, <50000000>; + clock_in_out = "output"; + phy-handle = <&phy>; + phy-mode = "rmii"; + phy-supply = <&vcc_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmiim1_miim &rgmiim1_rxer &rgmiim1_bus2 &rgmiim1_mclkinout>; + status = "okay"; +}; + +&mdio { + phy: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + pinctrl-names = "default"; + pinctrl-0 = <ð_phy_rst>; + reset-active-low; + reset-assert-us = <50000>; + reset-deassert-us = <10000>; + reset-gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + ethernet { + eth_phy_rst: eth-phy-rst { + rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + bt { + bt_enable: bt-enable { + rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_dev: bt-wake-dev { + rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_host: bt-wake-host { + rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + wifi { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + pmuio0-supply = <&vcc1v8_pmu>; + pmuio1-supply = <&vcc3v3_sys>; + vccio1-supply = <&vcc_1v8>; + vccio2-supply = <&vccio_sd>; + vccio3-supply = <&vcc_1v8>; + vccio4-supply = <&vcc_dovdd>; + vccio5-supply = <&vcc_1v8>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_dovdd>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdio { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + max-frequency = <100000000>; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_clk &sdmmc1_cmd &sdmmc1_bus4>; + rockchip,default-sample-phase = <90>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sys>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_bus4 &sdmmc0_det>; + rockchip,default-sample-phase = <90>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr104; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_ctsn &uart0_rtsn>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "realtek,rtl8723ds-bt"; + device-wake-gpios = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>; /* BT_WAKE */ + enable-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; /* BT_RST */ + host-wake-gpios = <&gpio1 RK_PC5 GPIO_ACTIVE_HIGH>; /* BT_WAKE_HOST */ + max-speed = <2000000>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_enable>, <&bt_wake_dev>, <&bt_wake_host>; + }; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3m2_xfer>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4m2_xfer>; + status = "okay"; +}; diff --git a/arch/arm/dts/rv1126.dtsi b/arch/arm/dts/rv1126.dtsi index 1cb43147e9..bb603cae13 100644 --- a/arch/arm/dts/rv1126.dtsi +++ b/arch/arm/dts/rv1126.dtsi @@ -21,6 +21,13 @@ aliases { i2c0 = &i2c0; + i2c2 = &i2c2; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; }; cpus { @@ -83,6 +90,11 @@ clock-frequency = <24000000>; }; + display_subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vop_out>; + }; + xin24m: oscillator { compatible = "fixed-clock"; clock-frequency = <24000000>; @@ -125,6 +137,26 @@ reg = <0xfe86c000 0x20>; }; + qos_iep: qos@fe8a0000 { + compatible = "rockchip,rv1126-qos", "syscon"; + reg = <0xfe8a0000 0x20>; + }; + + qos_rga_rd: qos@fe8a0080 { + compatible = "rockchip,rv1126-qos", "syscon"; + reg = <0xfe8a0080 0x20>; + }; + + qos_rga_wr: qos@fe8a0100 { + compatible = "rockchip,rv1126-qos", "syscon"; + reg = <0xfe8a0100 0x20>; + }; + + qos_vop: qos@fe8a0180 { + compatible = "rockchip,rv1126-qos", "syscon"; + reg = <0xfe8a0180 0x20>; + }; + gic: interrupt-controller@feff0000 { compatible = "arm,gic-400"; interrupt-controller; @@ -170,6 +202,25 @@ pm_qos = <&qos_sdio>; #power-domain-cells = <0>; }; + + power-domain@RV1126_PD_VO { + reg = ; + clocks = <&cru ACLK_RGA>, + <&cru HCLK_RGA>, + <&cru CLK_RGA_CORE>, + <&cru ACLK_VOP>, + <&cru HCLK_VOP>, + <&cru DCLK_VOP>, + <&cru PCLK_DSIHOST>, + <&cru ACLK_IEP>, + <&cru HCLK_IEP>, + <&cru CLK_IEP_CORE>; + pm_qos = <&qos_rga_rd>, + <&qos_rga_wr>, + <&qos_vop>, + <&qos_iep>; + #power-domain-cells = <0>; + }; }; }; @@ -187,6 +238,20 @@ status = "disabled"; }; + i2c2: i2c@ff400000 { + compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c"; + reg = <0xff400000 0x1000>; + interrupts = ; + rockchip,grf = <&pmugrf>; + clocks = <&pmucru CLK_I2C2>, <&pmucru PCLK_I2C2>; + clock-names = "i2c", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + uart1: serial@ff410000 { compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; reg = <0xff410000 0x100>; @@ -203,6 +268,17 @@ status = "disabled"; }; + pwm2: pwm@ff430020 { + compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; + reg = <0xff430020 0x10>; + clock-names = "pwm", "pclk"; + clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm2m0_pins>; + #pwm-cells = <3>; + status = "disabled"; + }; + pmucru: clock-controller@ff480000 { compatible = "rockchip,rv1126-pmucru"; reg = <0xff480000 0x1000>; @@ -232,6 +308,17 @@ clock-names = "apb_pclk"; }; + pwm11: pwm@ff550030 { + compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; + reg = <0xff550030 0x10>; + clock-names = "pwm", "pclk"; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + pinctrl-0 = <&pwm11m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + uart0: serial@ff560000 { compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; reg = <0xff560000 0x100>; @@ -332,6 +419,92 @@ clock-names = "pclk", "timer"; }; + vop: vop@ffb00000 { + compatible = "rockchip,rv1126-vop"; + reg = <0xffb00000 0x200>, <0xffb00a00 0x400>; + interrupts = ; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>; + reset-names = "axi", "ahb", "dclk"; + resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>; + iommus = <&vop_mmu>; + power-domains = <&power RV1126_PD_VO>; + status = "disabled"; + + vop_out: port { + #address-cells = <1>; + #size-cells = <0>; + + vop_out_rgb: endpoint@0 { + reg = <0>; + }; + + vop_out_dsi: endpoint@1 { + reg = <1>; + }; + }; + }; + + vop_mmu: iommu@ffb00f00 { + compatible = "rockchip,iommu"; + reg = <0xffb00f00 0x100>; + interrupts = ; + clock-names = "aclk", "iface"; + clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; + #iommu-cells = <0>; + power-domains = <&power RV1126_PD_VO>; + status = "disabled"; + }; + + gmac: ethernet@ffc40000 { + compatible = "rockchip,rv1126-gmac", "snps,dwmac-4.20a"; + reg = <0xffc40000 0x4000>; + interrupts = , + ; + interrupt-names = "macirq", "eth_wake_irq"; + rockchip,grf = <&grf>; + clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>, + <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_REF>, + <&cru ACLK_GMAC>, <&cru PCLK_GMAC>, + <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_PTPREF>; + clock-names = "stmmaceth", "mac_clk_rx", + "mac_clk_tx", "clk_mac_ref", + "aclk_mac", "pclk_mac", + "clk_mac_speed", "ptp_ref"; + resets = <&cru SRST_GMAC_A>; + reset-names = "stmmaceth"; + + snps,mixed-burst; + snps,tso; + + snps,axi-config = <&stmmac_axi_setup>; + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + status = "disabled"; + + mdio: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + + stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <4>; + snps,rd_osr_lmt = <8>; + snps,blen = <0 0 0 0 16 8 4>; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <1>; + queue0 {}; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <1>; + queue0 {}; + }; + }; + emmc: mmc@ffc50000 { compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0xffc50000 0x4000>; @@ -370,6 +543,18 @@ status = "disabled"; }; + sfc: spi@ffc90000 { + compatible = "rockchip,sfc"; + reg = <0xffc90000 0x4000>; + interrupts = ; + assigned-clocks = <&cru SCLK_SFC>; + assigned-clock-rates = <80000000>; + clock-names = "clk_sfc", "hclk_sfc"; + clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; + power-domains = <&power RV1126_PD_NVM>; + status = "disabled"; + }; + pinctrl: pinctrl { compatible = "rockchip,rv1126-pinctrl"; rockchip,grf = <&grf>; From patchwork Mon Jan 22 12:46:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tim Lunn X-Patchwork-Id: 1889160 X-Patchwork-Delegate: ykai007@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=feathertop.org header.i=@feathertop.org header.a=rsa-sha256 header.s=fm2 header.b=p4XKJola; dkim=pass (2048-bit key; unprotected) header.d=messagingengine.com header.i=@messagingengine.com header.a=rsa-sha256 header.s=fm3 header.b=MQhNfTT8; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; 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Mon, 22 Jan 2024 07:46:34 -0500 (EST) Received: by feathertop.org (sSMTP sendmail emulation); Mon, 22 Jan 2024 23:46:31 +1100 From: Tim Lunn To: u-boot@lists.denx.de Cc: Tim Lunn , Kever Yang , Philipp Tomsich , Philipp Tomsich , Simon Glass , Tom Rini Subject: [PATCH 2/5] ram: rockchip: Add rv1126 ddr4 support Date: Mon, 22 Jan 2024 23:46:00 +1100 Message-Id: <20240122124603.3341988-3-tim@feathertop.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240122124603.3341988-1-tim@feathertop.org> References: <20240122124603.3341988-1-tim@feathertop.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Add support for ddr4 on rv1126. Timing detection files are imported from downstream Rockchip BSP u-boot. Allow selecting ddr4 ram with define CONFIG_RAM_ROCKCHIP_DDR4. Signed-off-by: Tim Lunn --- .../sdram-rv1126-ddr4-detect-1056.inc | 75 +++++++++++++++++++ .../rockchip/sdram-rv1126-ddr4-detect-328.inc | 75 +++++++++++++++++++ .../rockchip/sdram-rv1126-ddr4-detect-396.inc | 75 +++++++++++++++++++ .../rockchip/sdram-rv1126-ddr4-detect-528.inc | 75 +++++++++++++++++++ .../rockchip/sdram-rv1126-ddr4-detect-664.inc | 75 +++++++++++++++++++ .../rockchip/sdram-rv1126-ddr4-detect-784.inc | 75 +++++++++++++++++++ .../rockchip/sdram-rv1126-ddr4-detect-924.inc | 75 +++++++++++++++++++ drivers/ram/rockchip/sdram_rv1126.c | 8 ++ 8 files changed, 533 insertions(+) create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr4-detect-1056.inc create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr4-detect-328.inc create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr4-detect-396.inc create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr4-detect-528.inc create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr4-detect-664.inc create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr4-detect-784.inc create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr4-detect-924.inc diff --git a/drivers/ram/rockchip/sdram-rv1126-ddr4-detect-1056.inc b/drivers/ram/rockchip/sdram-rv1126-ddr4-detect-1056.inc new file mode 100644 index 0000000000..295b0871e0 --- /dev/null +++ b/drivers/ram/rockchip/sdram-rv1126-ddr4-detect-1056.inc @@ -0,0 +1,75 @@ +{ + { + { + .rank = 0x1, + .col = 0xA, + .bk = 0x2, + .bw = 0x1, + .dbw = 0x0, + .row_3_4 = 0x0, + .cs0_row = 0x11, + .cs1_row = 0x0, + .cs0_high16bit_row = 0x11, + .cs1_high16bit_row = 0x0, + .ddrconfig = 0 + }, + { + {0x561d1219}, + {0x10030703}, + {0x00000002}, + {0x00001111}, + {0x0000000c}, + {0x0000034b}, + 0x000000ff + } + }, + { + .ddr_freq = 1056, /* clock rate(MHz) */ + .dramtype = DDR4, + .num_channels = 1, + .stride = 0, + .odt = 1 + }, + { + { + {0x00000000, 0x43041010}, /* MSTR */ + {0x00000064, 0x008000b9}, /* RFSHTMG */ + {0x000000d0, 0x00020103}, /* INIT0 */ + {0x000000d4, 0x00690000}, /* INIT1 */ + {0x000000d8, 0x00000100}, /* INIT2 */ + {0x000000dc, 0x07340401}, /* INIT3 */ + {0x000000e0, 0x00100000}, /* INIT4 */ + {0x000000e4, 0x00110000}, /* INIT5 */ + {0x000000e8, 0x00000420}, /* INIT6 */ + {0x000000ec, 0x00000800}, /* INIT7 */ + {0x000000f4, 0x000f011f}, /* RANKCTL */ + {0x00000100, 0x0f102411}, /* DRAMTMG0 */ + {0x00000104, 0x0004041a}, /* DRAMTMG1 */ + {0x00000108, 0x0608060d}, /* DRAMTMG2 */ + {0x0000010c, 0x0040400c}, /* DRAMTMG3 */ + {0x00000110, 0x08030409}, /* DRAMTMG4 */ + {0x00000114, 0x06060403}, /* DRAMTMG5 */ + {0x00000120, 0x07070d07}, /* DRAMTMG8 */ + {0x00000124, 0x00020309}, /* DRAMTMG9 */ + {0x00000180, 0x01000040}, /* ZQCTL0 */ + {0x00000184, 0x00000000}, /* ZQCTL1 */ + {0x00000190, 0x07060004}, /* DFITMG0 */ + {0x00000198, 0x07000101}, /* DFILPCFG0 */ + {0x000001a0, 0xc0400003}, /* DFIUPD0 */ + {0x00000240, 0x06000614}, /* ODTCFG */ + {0x00000244, 0x00000201}, /* ODTMAP */ + {0x00000250, 0x00001f00}, /* SCHED */ + {0x00000490, 0x00000001}, /* PCTRL_0 */ + {0xffffffff, 0xffffffff} + } + }, + { + { + {0x00000004, 0x0000008c}, /* PHYREG01 */ + {0x00000014, 0x00000010}, /* PHYREG05 */ + {0x00000018, 0x00000000}, /* PHYREG06 */ + {0x0000001c, 0x0000000b}, /* PHYREG07 */ + {0xffffffff, 0xffffffff} + } + } +}, diff --git a/drivers/ram/rockchip/sdram-rv1126-ddr4-detect-328.inc b/drivers/ram/rockchip/sdram-rv1126-ddr4-detect-328.inc new file mode 100644 index 0000000000..4b424fb440 --- /dev/null +++ b/drivers/ram/rockchip/sdram-rv1126-ddr4-detect-328.inc @@ -0,0 +1,75 @@ +{ + { + { + .rank = 0x1, + .col = 0xA, + .bk = 0x2, + .bw = 0x1, + .dbw = 0x0, + .row_3_4 = 0x0, + .cs0_row = 0x11, + .cs1_row = 0x0, + .cs0_high16bit_row = 0x11, + .cs1_high16bit_row = 0x0, + .ddrconfig = 0 + }, + { + {0x4d110a08}, + {0x06020501}, + {0x00000002}, + {0x00001111}, + {0x0000000c}, + {0x00000232}, + 0x000000ff + } + }, + { + .ddr_freq = 328, /* clock rate(MHz) */ + .dramtype = DDR4, + .num_channels = 1, + .stride = 0, + .odt = 0 + }, + { + { + {0x00000000, 0x43049010}, /* MSTR */ + {0x00000064, 0x0027003a}, /* RFSHTMG */ + {0x000000d0, 0x00020052}, /* INIT0 */ + {0x000000d4, 0x00220000}, /* INIT1 */ + {0x000000d8, 0x00000100}, /* INIT2 */ + {0x000000dc, 0x00040000}, /* INIT3 */ + {0x000000e0, 0x00000000}, /* INIT4 */ + {0x000000e4, 0x00110000}, /* INIT5 */ + {0x000000e8, 0x00000420}, /* INIT6 */ + {0x000000ec, 0x00000400}, /* INIT7 */ + {0x000000f4, 0x000f011f}, /* RANKCTL */ + {0x00000100, 0x09060b06}, /* DRAMTMG0 */ + {0x00000104, 0x00020209}, /* DRAMTMG1 */ + {0x00000108, 0x0505040a}, /* DRAMTMG2 */ + {0x0000010c, 0x0040400c}, /* DRAMTMG3 */ + {0x00000110, 0x05030206}, /* DRAMTMG4 */ + {0x00000114, 0x03030202}, /* DRAMTMG5 */ + {0x00000120, 0x03030b03}, /* DRAMTMG8 */ + {0x00000124, 0x00020208}, /* DRAMTMG9 */ + {0x00000180, 0x01000040}, /* ZQCTL0 */ + {0x00000184, 0x00000000}, /* ZQCTL1 */ + {0x00000190, 0x07030003}, /* DFITMG0 */ + {0x00000198, 0x07000101}, /* DFILPCFG0 */ + {0x000001a0, 0xc0400003}, /* DFIUPD0 */ + {0x00000240, 0x06000604}, /* ODTCFG */ + {0x00000244, 0x00000201}, /* ODTMAP */ + {0x00000250, 0x00001f00}, /* SCHED */ + {0x00000490, 0x00000001}, /* PCTRL_0 */ + {0xffffffff, 0xffffffff} + } + }, + { + { + {0x00000004, 0x0000008c}, /* PHYREG01 */ + {0x00000014, 0x0000000a}, /* PHYREG05 */ + {0x00000018, 0x00000000}, /* PHYREG06 */ + {0x0000001c, 0x00000009}, /* PHYREG07 */ + {0xffffffff, 0xffffffff} + } + } +}, diff --git a/drivers/ram/rockchip/sdram-rv1126-ddr4-detect-396.inc b/drivers/ram/rockchip/sdram-rv1126-ddr4-detect-396.inc new file mode 100644 index 0000000000..980be8cf18 --- /dev/null +++ b/drivers/ram/rockchip/sdram-rv1126-ddr4-detect-396.inc @@ -0,0 +1,75 @@ +{ + { + { + .rank = 0x1, + .col = 0xA, + .bk = 0x2, + .bw = 0x1, + .dbw = 0x0, + .row_3_4 = 0x0, + .cs0_row = 0x11, + .cs1_row = 0x0, + .cs0_high16bit_row = 0x11, + .cs1_high16bit_row = 0x0, + .ddrconfig = 0 + }, + { + {0x4d110a0a}, + {0x07020501}, + {0x00000002}, + {0x00001111}, + {0x0000000c}, + {0x00000232}, + 0x000000ff + } + }, + { + .ddr_freq = 396, /* clock rate(MHz) */ + .dramtype = DDR4, + .num_channels = 1, + .stride = 0, + .odt = 0 + }, + { + { + {0x00000000, 0x43049010}, /* MSTR */ + {0x00000064, 0x00300046}, /* RFSHTMG */ + {0x000000d0, 0x00020062}, /* INIT0 */ + {0x000000d4, 0x00280000}, /* INIT1 */ + {0x000000d8, 0x00000100}, /* INIT2 */ + {0x000000dc, 0x00040000}, /* INIT3 */ + {0x000000e0, 0x00000000}, /* INIT4 */ + {0x000000e4, 0x00110000}, /* INIT5 */ + {0x000000e8, 0x00000420}, /* INIT6 */ + {0x000000ec, 0x00000400}, /* INIT7 */ + {0x000000f4, 0x000f011f}, /* RANKCTL */ + {0x00000100, 0x09070d07}, /* DRAMTMG0 */ + {0x00000104, 0x0002020a}, /* DRAMTMG1 */ + {0x00000108, 0x0505040a}, /* DRAMTMG2 */ + {0x0000010c, 0x0040400c}, /* DRAMTMG3 */ + {0x00000110, 0x05030206}, /* DRAMTMG4 */ + {0x00000114, 0x03030202}, /* DRAMTMG5 */ + {0x00000120, 0x04040b04}, /* DRAMTMG8 */ + {0x00000124, 0x00020208}, /* DRAMTMG9 */ + {0x00000180, 0x01000040}, /* ZQCTL0 */ + {0x00000184, 0x00000000}, /* ZQCTL1 */ + {0x00000190, 0x07030003}, /* DFITMG0 */ + {0x00000198, 0x07000101}, /* DFILPCFG0 */ + {0x000001a0, 0xc0400003}, /* DFIUPD0 */ + {0x00000240, 0x06000604}, /* ODTCFG */ + {0x00000244, 0x00000201}, /* ODTMAP */ + {0x00000250, 0x00001f00}, /* SCHED */ + {0x00000490, 0x00000001}, /* PCTRL_0 */ + {0xffffffff, 0xffffffff} + } + }, + { + { + {0x00000004, 0x0000008c}, /* PHYREG01 */ + {0x00000014, 0x0000000a}, /* PHYREG05 */ + {0x00000018, 0x00000000}, /* PHYREG06 */ + {0x0000001c, 0x00000009}, /* PHYREG07 */ + {0xffffffff, 0xffffffff} + } + } +}, diff --git a/drivers/ram/rockchip/sdram-rv1126-ddr4-detect-528.inc b/drivers/ram/rockchip/sdram-rv1126-ddr4-detect-528.inc new file mode 100644 index 0000000000..3bde055e8d --- /dev/null +++ b/drivers/ram/rockchip/sdram-rv1126-ddr4-detect-528.inc @@ -0,0 +1,75 @@ +{ + { + { + .rank = 0x1, + .col = 0xA, + .bk = 0x2, + .bw = 0x1, + .dbw = 0x0, + .row_3_4 = 0x0, + .cs0_row = 0x11, + .cs1_row = 0x0, + .cs0_high16bit_row = 0x11, + .cs1_high16bit_row = 0x0, + .ddrconfig = 0 + }, + { + {0x4d120a0d}, + {0x09020501}, + {0x00000002}, + {0x00001111}, + {0x0000000c}, + {0x00000232}, + 0x000000ff + } + }, + { + .ddr_freq = 528, /* clock rate(MHz) */ + .dramtype = DDR4, + .num_channels = 1, + .stride = 0, + .odt = 0 + }, + { + { + {0x00000000, 0x43049010}, /* MSTR */ + {0x00000064, 0x0040005d}, /* RFSHTMG */ + {0x000000d0, 0x00020082}, /* INIT0 */ + {0x000000d4, 0x00350000}, /* INIT1 */ + {0x000000d8, 0x00000100}, /* INIT2 */ + {0x000000dc, 0x00040000}, /* INIT3 */ + {0x000000e0, 0x00000000}, /* INIT4 */ + {0x000000e4, 0x00110000}, /* INIT5 */ + {0x000000e8, 0x00000420}, /* INIT6 */ + {0x000000ec, 0x00000400}, /* INIT7 */ + {0x000000f4, 0x000f011f}, /* RANKCTL */ + {0x00000100, 0x0a0a1209}, /* DRAMTMG0 */ + {0x00000104, 0x0002020e}, /* DRAMTMG1 */ + {0x00000108, 0x0505040a}, /* DRAMTMG2 */ + {0x0000010c, 0x0040400c}, /* DRAMTMG3 */ + {0x00000110, 0x05030206}, /* DRAMTMG4 */ + {0x00000114, 0x03030202}, /* DRAMTMG5 */ + {0x00000120, 0x04040b04}, /* DRAMTMG8 */ + {0x00000124, 0x00020208}, /* DRAMTMG9 */ + {0x00000180, 0x01000040}, /* ZQCTL0 */ + {0x00000184, 0x00000000}, /* ZQCTL1 */ + {0x00000190, 0x07030003}, /* DFITMG0 */ + {0x00000198, 0x07000101}, /* DFILPCFG0 */ + {0x000001a0, 0xc0400003}, /* DFIUPD0 */ + {0x00000240, 0x06000604}, /* ODTCFG */ + {0x00000244, 0x00000201}, /* ODTMAP */ + {0x00000250, 0x00001f00}, /* SCHED */ + {0x00000490, 0x00000001}, /* PCTRL_0 */ + {0xffffffff, 0xffffffff} + } + }, + { + { + {0x00000004, 0x0000008c}, /* PHYREG01 */ + {0x00000014, 0x0000000a}, /* PHYREG05 */ + {0x00000018, 0x00000000}, /* PHYREG06 */ + {0x0000001c, 0x00000009}, /* PHYREG07 */ + {0xffffffff, 0xffffffff} + } + } +}, diff --git a/drivers/ram/rockchip/sdram-rv1126-ddr4-detect-664.inc b/drivers/ram/rockchip/sdram-rv1126-ddr4-detect-664.inc new file mode 100644 index 0000000000..c9341166d6 --- /dev/null +++ b/drivers/ram/rockchip/sdram-rv1126-ddr4-detect-664.inc @@ -0,0 +1,75 @@ +{ + { + { + .rank = 0x1, + .col = 0xA, + .bk = 0x2, + .bw = 0x1, + .dbw = 0x0, + .row_3_4 = 0x0, + .cs0_row = 0x11, + .cs1_row = 0x0, + .cs0_high16bit_row = 0x11, + .cs1_high16bit_row = 0x0, + .ddrconfig = 0 + }, + { + {0x4d130a11}, + {0x0c020501}, + {0x00000002}, + {0x00001111}, + {0x0000000c}, + {0x0000023a}, + 0x000000ff + } + }, + { + .ddr_freq = 664, /* clock rate(MHz) */ + .dramtype = DDR4, + .num_channels = 1, + .stride = 0, + .odt = 1 + }, + { + { + {0x00000000, 0x43041010}, /* MSTR */ + {0x00000064, 0x00500075}, /* RFSHTMG */ + {0x000000d0, 0x000200a4}, /* INIT0 */ + {0x000000d4, 0x00420000}, /* INIT1 */ + {0x000000d8, 0x00000100}, /* INIT2 */ + {0x000000dc, 0x01040401}, /* INIT3 */ + {0x000000e0, 0x00000000}, /* INIT4 */ + {0x000000e4, 0x00110000}, /* INIT5 */ + {0x000000e8, 0x00000420}, /* INIT6 */ + {0x000000ec, 0x00000400}, /* INIT7 */ + {0x000000f4, 0x000f011f}, /* RANKCTL */ + {0x00000100, 0x0b0c160c}, /* DRAMTMG0 */ + {0x00000104, 0x00020211}, /* DRAMTMG1 */ + {0x00000108, 0x0505040a}, /* DRAMTMG2 */ + {0x0000010c, 0x0040400c}, /* DRAMTMG3 */ + {0x00000110, 0x05030306}, /* DRAMTMG4 */ + {0x00000114, 0x04040302}, /* DRAMTMG5 */ + {0x00000120, 0x05050b05}, /* DRAMTMG8 */ + {0x00000124, 0x00020208}, /* DRAMTMG9 */ + {0x00000180, 0x01000040}, /* ZQCTL0 */ + {0x00000184, 0x00000000}, /* ZQCTL1 */ + {0x00000190, 0x07030003}, /* DFITMG0 */ + {0x00000198, 0x07000101}, /* DFILPCFG0 */ + {0x000001a0, 0xc0400003}, /* DFIUPD0 */ + {0x00000240, 0x06000604}, /* ODTCFG */ + {0x00000244, 0x00000201}, /* ODTMAP */ + {0x00000250, 0x00001f00}, /* SCHED */ + {0x00000490, 0x00000001}, /* PCTRL_0 */ + {0xffffffff, 0xffffffff} + } + }, + { + { + {0x00000004, 0x0000008c}, /* PHYREG01 */ + {0x00000014, 0x0000000a}, /* PHYREG05 */ + {0x00000018, 0x00000000}, /* PHYREG06 */ + {0x0000001c, 0x00000009}, /* PHYREG07 */ + {0xffffffff, 0xffffffff} + } + } +}, diff --git a/drivers/ram/rockchip/sdram-rv1126-ddr4-detect-784.inc b/drivers/ram/rockchip/sdram-rv1126-ddr4-detect-784.inc new file mode 100644 index 0000000000..ef2e9347bf --- /dev/null +++ b/drivers/ram/rockchip/sdram-rv1126-ddr4-detect-784.inc @@ -0,0 +1,75 @@ +{ + { + { + .rank = 0x1, + .col = 0xA, + .bk = 0x2, + .bw = 0x1, + .dbw = 0x0, + .row_3_4 = 0x0, + .cs0_row = 0x11, + .cs1_row = 0x0, + .cs0_high16bit_row = 0x11, + .cs1_high16bit_row = 0x0, + .ddrconfig = 0 + }, + { + {0x50160d14}, + {0x0e020502}, + {0x00000002}, + {0x00001111}, + {0x0000000c}, + {0x0000033a}, + 0x000000ff + } + }, + { + .ddr_freq = 784, /* clock rate(MHz) */ + .dramtype = DDR4, + .num_channels = 1, + .stride = 0, + .odt = 1 + }, + { + { + {0x00000000, 0x43041010}, /* MSTR */ + {0x00000064, 0x005f008a}, /* RFSHTMG */ + {0x000000d0, 0x000200c1}, /* INIT0 */ + {0x000000d4, 0x004e0000}, /* INIT1 */ + {0x000000d8, 0x00000100}, /* INIT2 */ + {0x000000dc, 0x03140401}, /* INIT3 */ + {0x000000e0, 0x00000000}, /* INIT4 */ + {0x000000e4, 0x00110000}, /* INIT5 */ + {0x000000e8, 0x00000420}, /* INIT6 */ + {0x000000ec, 0x00000400}, /* INIT7 */ + {0x000000f4, 0x000f011f}, /* RANKCTL */ + {0x00000100, 0x0c0e1a0e}, /* DRAMTMG0 */ + {0x00000104, 0x00030314}, /* DRAMTMG1 */ + {0x00000108, 0x0506050b}, /* DRAMTMG2 */ + {0x0000010c, 0x0040400c}, /* DRAMTMG3 */ + {0x00000110, 0x06030307}, /* DRAMTMG4 */ + {0x00000114, 0x04040302}, /* DRAMTMG5 */ + {0x00000120, 0x06060b06}, /* DRAMTMG8 */ + {0x00000124, 0x00020308}, /* DRAMTMG9 */ + {0x00000180, 0x01000040}, /* ZQCTL0 */ + {0x00000184, 0x00000000}, /* ZQCTL1 */ + {0x00000190, 0x07040003}, /* DFITMG0 */ + {0x00000198, 0x07000101}, /* DFILPCFG0 */ + {0x000001a0, 0xc0400003}, /* DFIUPD0 */ + {0x00000240, 0x0600060c}, /* ODTCFG */ + {0x00000244, 0x00000201}, /* ODTMAP */ + {0x00000250, 0x00001f00}, /* SCHED */ + {0x00000490, 0x00000001}, /* PCTRL_0 */ + {0xffffffff, 0xffffffff} + } + }, + { + { + {0x00000004, 0x0000008c}, /* PHYREG01 */ + {0x00000014, 0x0000000c}, /* PHYREG05 */ + {0x00000018, 0x00000000}, /* PHYREG06 */ + {0x0000001c, 0x00000009}, /* PHYREG07 */ + {0xffffffff, 0xffffffff} + } + } +}, diff --git a/drivers/ram/rockchip/sdram-rv1126-ddr4-detect-924.inc b/drivers/ram/rockchip/sdram-rv1126-ddr4-detect-924.inc new file mode 100644 index 0000000000..acb33bd315 --- /dev/null +++ b/drivers/ram/rockchip/sdram-rv1126-ddr4-detect-924.inc @@ -0,0 +1,75 @@ +{ + { + { + .rank = 0x1, + .col = 0xA, + .bk = 0x2, + .bw = 0x1, + .dbw = 0x0, + .row_3_4 = 0x0, + .cs0_row = 0x11, + .cs1_row = 0x0, + .cs0_high16bit_row = 0x11, + .cs1_high16bit_row = 0x0, + .ddrconfig = 0 + }, + { + {0x531a0f17}, + {0x0e020603}, + {0x00000002}, + {0x00001111}, + {0x0000000c}, + {0x00000342}, + 0x000000ff + } + }, + { + .ddr_freq = 924, /* clock rate(MHz) */ + .dramtype = DDR4, + .num_channels = 1, + .stride = 0, + .odt = 1 + }, + { + { + {0x00000000, 0x43041010}, /* MSTR */ + {0x00000064, 0x007000a2}, /* RFSHTMG */ + {0x000000d0, 0x000200e3}, /* INIT0 */ + {0x000000d4, 0x005c0000}, /* INIT1 */ + {0x000000d8, 0x00000100}, /* INIT2 */ + {0x000000dc, 0x05240401}, /* INIT3 */ + {0x000000e0, 0x00080000}, /* INIT4 */ + {0x000000e4, 0x00110000}, /* INIT5 */ + {0x000000e8, 0x00000420}, /* INIT6 */ + {0x000000ec, 0x00000400}, /* INIT7 */ + {0x000000f4, 0x000f011f}, /* RANKCTL */ + {0x00000100, 0x0e0e1f10}, /* DRAMTMG0 */ + {0x00000104, 0x00030317}, /* DRAMTMG1 */ + {0x00000108, 0x0507050c}, /* DRAMTMG2 */ + {0x0000010c, 0x0040400c}, /* DRAMTMG3 */ + {0x00000110, 0x07030308}, /* DRAMTMG4 */ + {0x00000114, 0x05050303}, /* DRAMTMG5 */ + {0x00000120, 0x07070b07}, /* DRAMTMG8 */ + {0x00000124, 0x00020309}, /* DRAMTMG9 */ + {0x00000180, 0x01000040}, /* ZQCTL0 */ + {0x00000184, 0x00000000}, /* ZQCTL1 */ + {0x00000190, 0x07050003}, /* DFITMG0 */ + {0x00000198, 0x07000101}, /* DFILPCFG0 */ + {0x000001a0, 0xc0400003}, /* DFIUPD0 */ + {0x00000240, 0x06000610}, /* ODTCFG */ + {0x00000244, 0x00000201}, /* ODTMAP */ + {0x00000250, 0x00001f00}, /* SCHED */ + {0x00000490, 0x00000001}, /* PCTRL_0 */ + {0xffffffff, 0xffffffff} + } + }, + { + { + {0x00000004, 0x0000008c}, /* PHYREG01 */ + {0x00000014, 0x0000000e}, /* PHYREG05 */ + {0x00000018, 0x00000000}, /* PHYREG06 */ + {0x0000001c, 0x0000000a}, /* PHYREG07 */ + {0xffffffff, 0xffffffff} + } + } +}, diff --git a/drivers/ram/rockchip/sdram_rv1126.c b/drivers/ram/rockchip/sdram_rv1126.c index 9e1376a940..0a78e18c73 100644 --- a/drivers/ram/rockchip/sdram_rv1126.c +++ b/drivers/ram/rockchip/sdram_rv1126.c @@ -76,6 +76,14 @@ struct rv1126_sdram_params sdram_configs[] = { # include "sdram-rv1126-lpddr4-detect-784.inc" # include "sdram-rv1126-lpddr4-detect-924.inc" # include "sdram-rv1126-lpddr4-detect-1056.inc" +#elif defined(CONFIG_RAM_ROCKCHIP_DDR4) +# include "sdram-rv1126-ddr4-detect-328.inc" +# include "sdram-rv1126-ddr4-detect-396.inc" +# include "sdram-rv1126-ddr4-detect-528.inc" +# include "sdram-rv1126-ddr4-detect-664.inc" +# include "sdram-rv1126-ddr4-detect-784.inc" +# include "sdram-rv1126-ddr4-detect-924.inc" +# include "sdram-rv1126-ddr4-detect-1056.inc" #else # include "sdram-rv1126-ddr3-detect-328.inc" # include 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hnpeefffeuhfetgeeikeejvefgtdefteehgfdvhfetfeeuffeuhffhfeekgfekgeehieen ucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhgrihhlfhhrohhmpehtihhmse hfvggrthhhvghrthhophdrohhrgh X-ME-Proxy: Feedback-ID: i1f8241ce:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Mon, 22 Jan 2024 07:46:41 -0500 (EST) Received: by feathertop.org (sSMTP sendmail emulation); Mon, 22 Jan 2024 23:46:38 +1100 From: Tim Lunn To: u-boot@lists.denx.de Cc: Tim Lunn , Kever Yang , Philipp Tomsich , Philipp Tomsich , Simon Glass , Tom Rini Subject: [PATCH 3/5] board: rockchip: Add Sonoff iHost board Date: Mon, 22 Jan 2024 23:46:01 +1100 Message-Id: <20240122124603.3341988-4-tim@feathertop.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240122124603.3341988-1-tim@feathertop.org> References: <20240122124603.3341988-1-tim@feathertop.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Sonoff iHost is gateway device designed to provide a Smart Home Hub, it is based on Rockchip RV1126. There is also a version with 2GB RAM based off the RV1109 dual core SoC however this works with the same config as the RV1126 for uboot purposes. Features: - Rockchip RV1126 - 4GB DDR4 - 8GB eMMC - microSD slot - RMII Ethernet PHY - 1x USB 2.0 Host - 1x USB 2.0 OTG - Realtek RTL8723DS WiFi/BT - EFR32MG21 Silabs Zigbee radio - Speaker/Microphone Signed-off-by: Tim Lunn --- arch/arm/dts/rv1126-sonoff-ihost-u-boot.dtsi | 13 +++++ arch/arm/mach-rockchip/rv1126/Kconfig | 8 +++ board/itead/sonoff-ihost/Kconfig | 16 ++++++ board/itead/sonoff-ihost/MAINTAINERS | 6 ++ configs/sonoff-ihost-rv1126_defconfig | 60 ++++++++++++++++++++ include/configs/sonoff-ihost.h | 18 ++++++ 6 files changed, 121 insertions(+) create mode 100644 arch/arm/dts/rv1126-sonoff-ihost-u-boot.dtsi create mode 100644 board/itead/sonoff-ihost/Kconfig create mode 100644 board/itead/sonoff-ihost/MAINTAINERS create mode 100644 configs/sonoff-ihost-rv1126_defconfig create mode 100644 include/configs/sonoff-ihost.h diff --git a/arch/arm/dts/rv1126-sonoff-ihost-u-boot.dtsi b/arch/arm/dts/rv1126-sonoff-ihost-u-boot.dtsi new file mode 100644 index 0000000000..a625660d58 --- /dev/null +++ b/arch/arm/dts/rv1126-sonoff-ihost-u-boot.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rv1126-u-boot.dtsi" + +/ { + chosen { + u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc; + }; +}; + +&sdio { + status = "disabled"; +}; diff --git a/arch/arm/mach-rockchip/rv1126/Kconfig b/arch/arm/mach-rockchip/rv1126/Kconfig index a6e2b5903c..55b1112120 100644 --- a/arch/arm/mach-rockchip/rv1126/Kconfig +++ b/arch/arm/mach-rockchip/rv1126/Kconfig @@ -14,6 +14,13 @@ config TARGET_RV1126_NEU2 IO board and Neu2 needs to mount on top of this IO board in order to create complete Edgeble Neural Compute Module 2(Neu2) IO platform. +config TARGET_RV1126_SONOFF_IHOST + bool "Sonoff iHost smart home hub" + help + Sonoff iHost is a smart home gateway based on Rockchip RV1126 SoC. + It features Wifi, Bluetooth and Zigbee radios that are used by many + smart home devices. + config SOC_SPECIFIC_OPTIONS # dummy def_bool y select HAS_CUSTOM_SYS_INIT_SP_ADDR @@ -58,5 +65,6 @@ config TEXT_BASE default 0x600000 source board/edgeble/neural-compute-module-2/Kconfig +source board/itead/sonoff-ihost/Kconfig endif diff --git a/board/itead/sonoff-ihost/Kconfig b/board/itead/sonoff-ihost/Kconfig new file mode 100644 index 0000000000..30d9a6b3e6 --- /dev/null +++ b/board/itead/sonoff-ihost/Kconfig @@ -0,0 +1,16 @@ +if TARGET_RV1126_SONOFF_IHOST + +config SYS_BOARD + default "sonoff-ihost" + +config SYS_VENDOR + default "itead" + +config SYS_CONFIG_NAME + default "sonoff-ihost" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select RAM_ROCKCHIP_DDR4 + +endif diff --git a/board/itead/sonoff-ihost/MAINTAINERS b/board/itead/sonoff-ihost/MAINTAINERS new file mode 100644 index 0000000000..eff9274bea --- /dev/null +++ b/board/itead/sonoff-ihost/MAINTAINERS @@ -0,0 +1,6 @@ +RV1126-SONOFF-IHOST +M: Tim Lunn +S: Maintained +F: board/itead/sonoff-ihost +F: include/configs/sonoff-ihost.h +F: configs/sonoff-ihost-rv1126_defconfig diff --git a/configs/sonoff-ihost-rv1126_defconfig b/configs/sonoff-ihost-rv1126_defconfig new file mode 100644 index 0000000000..fe99bd92f9 --- /dev/null +++ b/configs/sonoff-ihost-rv1126_defconfig @@ -0,0 +1,60 @@ +CONFIG_ARM=y +CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y +CONFIG_TPL_SKIP_LOWLEVEL_INIT_ONLY=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_SYS_ARCH_TIMER=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="rv1126-sonoff-ihost" +CONFIG_SYS_MONITOR_LEN=614400 +CONFIG_ROCKCHIP_RV1126=y +CONFIG_TARGET_RV1126_SONOFF_IHOST=y +CONFIG_DEBUG_UART_BASE=0xff570000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0xe00800 +CONFIG_DEBUG_UART=y +CONFIG_FIT_VERBOSE=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_SPL_FIT=y +CONFIG_SPL_LOAD_FIT=y +# CONFIG_USE_SPL_FIT_GENERATOR is not set +CONFIG_SYS_BOOTM_LEN=0x4000000 +CONFIG_DEFAULT_FDT_FILE="rv1126-sonoff-ihost.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_NO_BSS_LIMIT=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +CONFIG_CMD_GPT=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_ISO_PARTITION is not set +CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64 +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_REGULATOR_PWM=y +CONFIG_PWM_ROCKCHIP=y +# CONFIG_RAM_ROCKCHIP_DEBUG is not set +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +# CONFIG_TPL_SYSRESET is not set +CONFIG_DM_THERMAL=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_LZO=y +CONFIG_ERRNO_STR=y diff --git a/include/configs/sonoff-ihost.h b/include/configs/sonoff-ihost.h new file mode 100644 index 0000000000..8ed5d78687 --- /dev/null +++ b/include/configs/sonoff-ihost.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __SONOFF_IHOST_H +#define __SONOFF_IHOST_H + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdout=serial\0" \ + "stderr=serial\0" + +#include + +#undef BOOT_TARGET_DEVICES + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) + +#endif /* __SONOFF_IHOST_H */ From patchwork Mon Jan 22 12:46:02 2024 Content-Type: text/plain; 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Mon, 22 Jan 2024 07:46:49 -0500 (EST) Received: by feathertop.org (sSMTP sendmail emulation); Mon, 22 Jan 2024 23:46:46 +1100 From: Tim Lunn To: u-boot@lists.denx.de Cc: Tim Lunn , Jagan Teki , Johan Jonker , Jonas Karlman , Kever Yang , Massimo Pegorer , Michal Simek , Philipp Tomsich , Philipp Tomsich , Quentin Schulz , Simon Glass , Tom Rini Subject: [PATCH 4/5] rockchip: rv1126: select SPL_OPTEE_IMAGE Date: Mon, 22 Jan 2024 23:46:02 +1100 Message-Id: <20240122124603.3341988-5-tim@feathertop.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240122124603.3341988-1-tim@feathertop.org> References: <20240122124603.3341988-1-tim@feathertop.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean rv1126 requires OPTEE as it provides pcsi support. Mainline Linux kernel will fail to boot without this. Select SPL_OPTEE_IMAGE when building FIT image. TEE must be provided when building. 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Mon, 22 Jan 2024 07:46:58 -0500 (EST) Received: by feathertop.org (sSMTP sendmail emulation); Mon, 22 Jan 2024 23:46:55 +1100 From: Tim Lunn To: u-boot@lists.denx.de Cc: Tim Lunn , Jagan Teki , Kever Yang , Philipp Tomsich , Simon Glass , Tom Rini Subject: [PATCH 5/5] rockchip: rv1126: Move RAM disk address Date: Mon, 22 Jan 2024 23:46:03 +1100 Message-Id: <20240122124603.3341988-6-tim@feathertop.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240122124603.3341988-1-tim@feathertop.org> References: <20240122124603.3341988-1-tim@feathertop.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean OPTEE gets loaded into a memory region overlapping with the ram disk. Fix the ramdisk address so it doesn't overlap with the OPTEE memory region. Signed-off-by: Tim Lunn --- include/configs/rv1126_common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/rv1126_common.h b/include/configs/rv1126_common.h index a64c0c6364..6961dbe20b 100644 --- a/include/configs/rv1126_common.h +++ b/include/configs/rv1126_common.h @@ -26,7 +26,7 @@ "fdt_addr_r=0x08300000\0" \ "fdtoverlay_addr_r=0x02000000\0" \ "kernel_addr_r=0x02008000\0" \ - "ramdisk_addr_r=0x0a200000\0" + "ramdisk_addr_r=0x0a400000\0" #include #define CFG_EXTRA_ENV_SETTINGS \