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bh=x/BtWxPZSNhBcD6nHUwGTOj5StFt9BCCl5RHjDs7OIk=; h=From:To:Subject:Date:Message-ID:MIME-Version; b=bKP9YV/rFoIyoWTBYWJtTLfc59Aj4M2yGSRzibhEYH6EtCKvWrJgLs3+Co6/+PjITDvWX7VlfTrMDOCy424kRqIrB2nEXO8HjIA2oxiKdmtgSSoTWNx7/GhTiELFZiTqkaVKNch24+BQrB9N0MkA9tU6HOQujX4YlNAEIYLa+hI= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from loongson.cn (unknown [114.243.106.119]) by gateway (Coremail) with SMTP id _____8CxrutRqZdl6TgCAA--.8412S3; Fri, 05 Jan 2024 15:01:37 +0800 (CST) Received: from localhost.localdomain (unknown [114.243.106.119]) by localhost.localdomain (Coremail) with SMTP id AQAAf8AxjodPqZdlggMDAA--.318S3; Fri, 05 Jan 2024 15:01:35 +0800 (CST) From: Yang Yujie To: gcc-patches@gcc.gnu.org Cc: chenglulu@loongson.cn, xry111@xry111.site, xuchenghua@loongson.cn, Yang Yujie Subject: [PATCH 1/4] LoongArch: Handle ISA evolution switches along with other options Date: Fri, 5 Jan 2024 14:55:32 +0800 Message-ID: <20240105065535.1364530-2-yangyujie@loongson.cn> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240105065535.1364530-1-yangyujie@loongson.cn> References: <20240105065535.1364530-1-yangyujie@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf8AxjodPqZdlggMDAA--.318S3 X-CM-SenderInfo: 51dqw5pxmlvqxorr0wxvrqhubq/1tbiAQAHAGWXVSgHMQAAs- X-Coremail-Antispam: 1Uk129KBj9fXoW3CF4kJw4DZF1ftryrZFyxZwc_yoW8WrWfKo WYyFWDZw48Gr1Sv3yUtrnIqrWqqrn0yrWDAayIv3WUGFs7Zr98JFy7Wa1avry7Jas2qry5 C347Wrs7Xa4xJF4Dl-sFpf9Il3svdjkaLaAFLSUrUUUUjb8apTn2vfkv8UJUUUU8wcxFpf 9Il3svdxBIdaVrn0xqx4xG64xvF2IEw4CE5I8CrVC2j2Jv73VFW2AGmfu7bjvjm3AaLaJ3 UjIYCTnIWjp_UUUY17kC6x804xWl14x267AKxVWUJVW8JwAFc2x0x2IEx4CE42xK8VAvwI 8IcIk0rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xG Y2AK021l84ACjcxK6xIIjxv20xvE14v26r1I6r4UM28EF7xvwVC0I7IYx2IY6xkF7I0E14 v26r1j6r4UM28EF7xvwVC2z280aVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIEc7CjxVAF wI0_Gr1j6F4UJwAS0I0E0xvYzxvE52x082IY62kv0487Mc804VCY07AIYIkI8VC2zVCFFI 0UMc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2IY67AKxVWUXVWUAwAv7VC2z280 aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0Y48IcxkI7VAKI48JMxAIw28Icx kI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2Iq xVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAVWUtwCIc40Y0x0EwIxGrwCI42 IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWUJVW8JwCI42IY 6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aV CY1x0267AKxVWUJVW8JbIYCTnIWIevJa73UjIFyTuYvjxUwmhFDUUUU X-Spam-Status: No, score=-10.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_BARRACUDACENTRAL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org gcc/ChangeLog: * config/loongarch/genopts/genstr.sh: Prepend the isa_evolution variable with the common la_ prefix. * config/loongarch/genopts/loongarch.opt.in: Mark ISA evolution flags as saved using TargetVariable. * config/loongarch/loongarch.opt: Same. * config/loongarch/loongarch-def.h: Define evolution_set to mark changes to the -march default. * config/loongarch/loongarch-driver.cc: Same. * config/loongarch/loongarch-opts.cc: Same. * config/loongarch/loongarch-opts.h: Define and use ISA evolution conditions around the la_target structure. * config/loongarch/loongarch.cc: Same. * config/loongarch/loongarch.md: Same. * config/loongarch/loongarch-builtins.cc: Same. * config/loongarch/loongarch-c.cc: Same. * config/loongarch/lasx.md: Same. * config/loongarch/lsx.md: Same. --- gcc/config/loongarch/genopts/genstr.sh | 2 +- gcc/config/loongarch/genopts/loongarch.opt.in | 6 ++--- gcc/config/loongarch/lasx.md | 4 ++-- gcc/config/loongarch/loongarch-builtins.cc | 6 ++--- gcc/config/loongarch/loongarch-c.cc | 2 +- gcc/config/loongarch/loongarch-def.h | 5 +++- gcc/config/loongarch/loongarch-driver.cc | 5 ++-- gcc/config/loongarch/loongarch-opts.cc | 17 ++++++++++++- gcc/config/loongarch/loongarch-opts.h | 24 +++++++++++++++---- gcc/config/loongarch/loongarch.cc | 20 +++++++--------- gcc/config/loongarch/loongarch.md | 4 ++-- gcc/config/loongarch/loongarch.opt | 16 ++++++------- gcc/config/loongarch/lsx.md | 4 ++-- 13 files changed, 73 insertions(+), 42 deletions(-) diff --git a/gcc/config/loongarch/genopts/genstr.sh b/gcc/config/loongarch/genopts/genstr.sh index 5865b87d516..724c9aaedac 100755 --- a/gcc/config/loongarch/genopts/genstr.sh +++ b/gcc/config/loongarch/genopts/genstr.sh @@ -107,7 +107,7 @@ EOF print("") print("m"$3) gsub(/-/, "_", $3) - print("Target Mask(ISA_"toupper($3)") Var(isa_evolution)") + print("Target Mask(ISA_"toupper($3)") Var(la_isa_evolution)") $1=""; $2=""; $3="" sub(/^ */, "", $0) print($0) diff --git a/gcc/config/loongarch/genopts/loongarch.opt.in b/gcc/config/loongarch/genopts/loongarch.opt.in index f2e7ea2ef2f..e643deacd21 100644 --- a/gcc/config/loongarch/genopts/loongarch.opt.in +++ b/gcc/config/loongarch/genopts/loongarch.opt.in @@ -259,6 +259,6 @@ default value is 4. ; Features added during ISA evolution. This concept is different from ISA ; extension, read Section 1.5 of LoongArch v1.10 Volume 1 for the ; explanation. These features may be implemented and enumerated with -; CPUCFG independantly, so we use bit flags to specify them. -Variable -HOST_WIDE_INT isa_evolution = 0 +; CPUCFG independently, so we use bit flags to specify them. +TargetVariable +HOST_WIDE_INT la_isa_evolution = 0 diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md index 027021b45d5..429c59504b9 100644 --- a/gcc/config/loongarch/lasx.md +++ b/gcc/config/loongarch/lasx.md @@ -1539,7 +1539,7 @@ (define_insn "lasx_xvfrecipe_" [(set (match_operand:FLASX 0 "register_operand" "=f") (unspec:FLASX [(match_operand:FLASX 1 "register_operand" "f")] UNSPEC_LASX_XVFRECIPE))] - "ISA_HAS_LASX && TARGET_FRECIPE" + "ISA_HAS_LASX && ISA_HAS_FRECIPE" "xvfrecipe.\t%u0,%u1" [(set_attr "type" "simd_fdiv") (set_attr "mode" "")]) @@ -1572,7 +1572,7 @@ (define_insn "lasx_xvfrsqrte_" [(set (match_operand:FLASX 0 "register_operand" "=f") (unspec:FLASX [(match_operand:FLASX 1 "register_operand" "f")] UNSPEC_LASX_XVFRSQRTE))] - "ISA_HAS_LASX && TARGET_FRECIPE" + "ISA_HAS_LASX && ISA_HAS_FRECIPE" "xvfrsqrte.\t%u0,%u1" [(set_attr "type" "simd_fdiv") (set_attr "mode" "")]) diff --git a/gcc/config/loongarch/loongarch-builtins.cc b/gcc/config/loongarch/loongarch-builtins.cc index 45ec6aca030..efe7e5e5ebc 100644 --- a/gcc/config/loongarch/loongarch-builtins.cc +++ b/gcc/config/loongarch/loongarch-builtins.cc @@ -120,9 +120,9 @@ struct loongarch_builtin_description AVAIL_ALL (hard_float, TARGET_HARD_FLOAT_ABI) AVAIL_ALL (lsx, ISA_HAS_LSX) AVAIL_ALL (lasx, ISA_HAS_LASX) -AVAIL_ALL (frecipe, TARGET_FRECIPE && TARGET_HARD_FLOAT_ABI) -AVAIL_ALL (lsx_frecipe, ISA_HAS_LSX && TARGET_FRECIPE) -AVAIL_ALL (lasx_frecipe, ISA_HAS_LASX && TARGET_FRECIPE) +AVAIL_ALL (frecipe, ISA_HAS_FRECIPE && TARGET_HARD_FLOAT_ABI) +AVAIL_ALL (lsx_frecipe, ISA_HAS_LSX && ISA_HAS_FRECIPE) +AVAIL_ALL (lasx_frecipe, ISA_HAS_LASX && ISA_HAS_FRECIPE) /* Construct a loongarch_builtin_description from the given arguments. diff --git a/gcc/config/loongarch/loongarch-c.cc b/gcc/config/loongarch/loongarch-c.cc index 118b1512e1e..4d88c1729ff 100644 --- a/gcc/config/loongarch/loongarch-c.cc +++ b/gcc/config/loongarch/loongarch-c.cc @@ -102,7 +102,7 @@ loongarch_cpu_cpp_builtins (cpp_reader *pfile) else builtin_define ("__loongarch_frlen=0"); - if (TARGET_HARD_FLOAT && TARGET_FRECIPE) + if (TARGET_HARD_FLOAT && ISA_HAS_FRECIPE) builtin_define ("__loongarch_frecipe"); if (ISA_HAS_LSX) diff --git a/gcc/config/loongarch/loongarch-def.h b/gcc/config/loongarch/loongarch-def.h index 403b024812d..1fab4f4d315 100644 --- a/gcc/config/loongarch/loongarch-def.h +++ b/gcc/config/loongarch/loongarch-def.h @@ -132,8 +132,11 @@ struct loongarch_isa Using int64_t instead of HOST_WIDE_INT for C compatibility. */ int64_t evolution; + int64_t evolution_set; - loongarch_isa () : base (0), fpu (0), simd (0), evolution (0) {} + loongarch_isa () : + base (0), fpu (0), simd (0), evolution (0), evolution_set (0) + {} loongarch_isa base_ (int _base) { base = _base; return *this; } loongarch_isa fpu_ (int _fpu) { fpu = _fpu; return *this; } loongarch_isa simd_ (int _simd) { simd = _simd; return *this; } diff --git a/gcc/config/loongarch/loongarch-driver.cc b/gcc/config/loongarch/loongarch-driver.cc index ef1db3104e7..62658f531ad 100644 --- a/gcc/config/loongarch/loongarch-driver.cc +++ b/gcc/config/loongarch/loongarch-driver.cc @@ -42,9 +42,10 @@ extern struct obstack opts_obstack; const char* la_driver_init (int argc ATTRIBUTE_UNUSED, const char **argv ATTRIBUTE_UNUSED) { - /* Initialize all fields of la_target to -1 */ + /* Initialize all fields of la_target. */ loongarch_init_target (&la_target, M_OPT_UNSET, M_OPT_UNSET, M_OPT_UNSET, - M_OPT_UNSET, M_OPT_UNSET, M_OPT_UNSET, M_OPT_UNSET); + M_OPT_UNSET, M_OPT_UNSET, M_OPT_UNSET, M_OPT_UNSET, + 0, 0); return ""; } diff --git a/gcc/config/loongarch/loongarch-opts.cc b/gcc/config/loongarch/loongarch-opts.cc index d28b4363c7b..9483060ab62 100644 --- a/gcc/config/loongarch/loongarch-opts.cc +++ b/gcc/config/loongarch/loongarch-opts.cc @@ -140,7 +140,9 @@ static int with_default_simd = 0; void loongarch_init_target (struct loongarch_target *target, int cpu_arch, int cpu_tune, int fpu, int simd, - int abi_base, int abi_ext, int cmodel) + int abi_base, int abi_ext, int cmodel, + HOST_WIDE_INT isa_evolution, + HOST_WIDE_INT isa_evolution_set) { if (!target) return; @@ -148,6 +150,8 @@ loongarch_init_target (struct loongarch_target *target, target->cpu_tune = cpu_tune; target->isa.fpu = fpu; target->isa.simd = simd; + target->isa.evolution = isa_evolution; + target->isa.evolution_set = isa_evolution_set; target->abi.base = abi_base; target->abi.ext = abi_ext; target->cmodel = cmodel; @@ -184,6 +188,9 @@ loongarch_config_target (struct loongarch_target *target, M_OPT_ABSENT (target->abi.base) ? 0 : 1, }; + int64_t isa_evolution = target->isa.evolution; + int64_t isa_evolution_set = target->isa.evolution_set; + /* 1. Target ABI */ if (constrained.abi_base) t.abi.base = target->abi.base; @@ -394,6 +401,13 @@ config_target_isa: } } + /* Apply the ISA evolution feature switches from the user. */ + HOST_WIDE_INT isa_evolution_orig = t.isa.evolution; + t.isa.evolution &= ~(~isa_evolution & isa_evolution_set); + t.isa.evolution |= isa_evolution & isa_evolution_set; + + /* evolution_set means "what's different from the -march default". */ + t.isa.evolution_set = isa_evolution_orig ^ t.isa.evolution; /* 4. ABI-ISA compatibility */ /* Note: @@ -774,4 +788,5 @@ loongarch_update_gcc_opt_status (struct loongarch_target *target, /* status of -mfpu */ opts->x_la_opt_fpu = target->isa.fpu; opts->x_la_opt_simd = target->isa.simd; + opts->x_la_isa_evolution = target->isa.evolution; } diff --git a/gcc/config/loongarch/loongarch-opts.h b/gcc/config/loongarch/loongarch-opts.h index b28dcbfb791..c6545f691a1 100644 --- a/gcc/config/loongarch/loongarch-opts.h +++ b/gcc/config/loongarch/loongarch-opts.h @@ -34,7 +34,9 @@ extern struct loongarch_target la_target; void loongarch_init_target (struct loongarch_target *target, int cpu_arch, int cpu_tune, int fpu, int simd, - int abi_base, int abi_ext, int cmodel); + int abi_base, int abi_ext, int cmodel, + HOST_WIDE_INT isa_evolutions, + HOST_WIDE_INT isa_evolutions_set); /* Handler for "-m" option combinations, @@ -82,9 +84,23 @@ struct loongarch_flags { || la_target.abi.base == ABI_BASE_LP64F \ || la_target.abi.base == ABI_BASE_LP64S) -#define ISA_HAS_LSX (la_target.isa.simd == ISA_EXT_SIMD_LSX \ - || la_target.isa.simd == ISA_EXT_SIMD_LASX) -#define ISA_HAS_LASX (la_target.isa.simd == ISA_EXT_SIMD_LASX) +#define ISA_HAS_LSX \ + (la_target.isa.simd == ISA_EXT_SIMD_LSX \ + || la_target.isa.simd == ISA_EXT_SIMD_LASX) + +#define ISA_HAS_LASX \ + (la_target.isa.simd == ISA_EXT_SIMD_LASX) + +#define ISA_HAS_FRECIPE \ + (la_target.isa.evolution & OPTION_MASK_ISA_FRECIPE) +#define ISA_HAS_DIV32 \ + (la_target.isa.evolution & OPTION_MASK_ISA_DIV32) +#define ISA_HAS_LAM_BH \ + (la_target.isa.evolution & OPTION_MASK_ISA_LAM_BH) +#define ISA_HAS_LAMCAS \ + (la_target.isa.evolution & OPTION_MASK_ISA_LAM_BH) +#define ISA_HAS_LD_SEQ_SA \ + (la_target.isa.evolution & OPTION_MASK_ISA_LD_SEQ_SA) /* TARGET_ macros for use in *.md template conditionals */ #define TARGET_uARCH_LA464 (la_target.cpu_tune == CPU_LA464) diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc index 91e6bb3e95a..ce760fda009 100644 --- a/gcc/config/loongarch/loongarch.cc +++ b/gcc/config/loongarch/loongarch.cc @@ -7524,7 +7524,8 @@ loongarch_option_override_internal (struct gcc_options *opts, loongarch_init_target (&la_target, la_opt_cpu_arch, la_opt_cpu_tune, la_opt_fpu, la_opt_simd, la_opt_abi_base, la_opt_abi_ext, - la_opt_cmodel); + la_opt_cmodel, opts->x_la_isa_evolution, + opts_set->x_la_isa_evolution); /* Handle target-specific options: compute defaults/conflicts etc. */ loongarch_config_target (&la_target, NULL, 0); @@ -7565,11 +7566,6 @@ loongarch_option_override_internal (struct gcc_options *opts, if (loongarch_branch_cost == 0) loongarch_branch_cost = loongarch_cost->branch_cost; - /* If the user hasn't disabled a feature added during ISA evolution, - use the processor's default. */ - isa_evolution |= (la_target.isa.evolution & - ~global_options_set.x_isa_evolution); - /* Enable sw prefetching at -O3 and higher. */ if (opts->x_flag_prefetch_loop_arrays < 0 && (opts->x_optimize >= 3 || opts->x_flag_profile_use) @@ -7700,7 +7696,7 @@ loongarch_option_override_internal (struct gcc_options *opts, } if (loongarch_recip) recip_mask |= RECIP_MASK_ALL; - if (!TARGET_FRECIPE) + if (!ISA_HAS_FRECIPE) recip_mask = RECIP_MASK_NONE; } @@ -11743,11 +11739,11 @@ loongarch_asm_code_end (void) loongarch_cpu_strings [la_target.cpu_tune]); fprintf (asm_out_file, "%s Base ISA: %s\n", ASM_COMMENT_START, loongarch_isa_base_strings [la_target.isa.base]); - DUMP_FEATURE (TARGET_FRECIPE); - DUMP_FEATURE (TARGET_DIV32); - DUMP_FEATURE (TARGET_LAM_BH); - DUMP_FEATURE (TARGET_LAMCAS); - DUMP_FEATURE (TARGET_LD_SEQ_SA); + DUMP_FEATURE (ISA_HAS_FRECIPE); + DUMP_FEATURE (ISA_HAS_DIV32); + DUMP_FEATURE (ISA_HAS_LAM_BH); + DUMP_FEATURE (ISA_HAS_LAMCAS); + DUMP_FEATURE (ISA_HAS_LD_SEQ_SA); } fputs ("\n\n", asm_out_file); diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md index d1f5b94f5d6..a03db97ec55 100644 --- a/gcc/config/loongarch/loongarch.md +++ b/gcc/config/loongarch/loongarch.md @@ -941,7 +941,7 @@ (define_insn "loongarch_frecipe_" [(set (match_operand:ANYF 0 "register_operand" "=f") (unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f")] UNSPEC_RECIPE))] - "TARGET_FRECIPE" + "ISA_HAS_FRECIPE" "frecipe.\t%0,%1" [(set_attr "type" "frecipe") (set_attr "mode" "") @@ -1197,7 +1197,7 @@ (define_insn "loongarch_frsqrte_" [(set (match_operand:ANYF 0 "register_operand" "=f") (unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f")] UNSPEC_RSQRTE))] - "TARGET_FRECIPE" + "ISA_HAS_FRECIPE" "frsqrte.\t%0,%1" [(set_attr "type" "frsqrte") (set_attr "mode" "")]) diff --git a/gcc/config/loongarch/loongarch.opt b/gcc/config/loongarch/loongarch.opt index b285a74acea..8b36f1a1495 100644 --- a/gcc/config/loongarch/loongarch.opt +++ b/gcc/config/loongarch/loongarch.opt @@ -267,26 +267,26 @@ default value is 4. ; Features added during ISA evolution. This concept is different from ISA ; extension, read Section 1.5 of LoongArch v1.10 Volume 1 for the ; explanation. These features may be implemented and enumerated with -; CPUCFG independantly, so we use bit flags to specify them. -Variable -HOST_WIDE_INT isa_evolution = 0 +; CPUCFG independently, so we use bit flags to specify them. +TargetVariable +HOST_WIDE_INT la_isa_evolution = 0 mfrecipe -Target Mask(ISA_FRECIPE) Var(isa_evolution) +Target Mask(ISA_FRECIPE) Var(la_isa_evolution) Support frecipe.{s/d} and frsqrte.{s/d} instructions. mdiv32 -Target Mask(ISA_DIV32) Var(isa_evolution) +Target Mask(ISA_DIV32) Var(la_isa_evolution) Support div.w[u] and mod.w[u] instructions with inputs not sign-extended. mlam-bh -Target Mask(ISA_LAM_BH) Var(isa_evolution) +Target Mask(ISA_LAM_BH) Var(la_isa_evolution) Support am{swap/add}[_db].{b/h} instructions. mlamcas -Target Mask(ISA_LAMCAS) Var(isa_evolution) +Target Mask(ISA_LAMCAS) Var(la_isa_evolution) Support amcas[_db].{b/h/w/d} instructions. mld-seq-sa -Target Mask(ISA_LD_SEQ_SA) Var(isa_evolution) +Target Mask(ISA_LD_SEQ_SA) Var(la_isa_evolution) Do not need load-load barriers (dbar 0x700). diff --git a/gcc/config/loongarch/lsx.md b/gcc/config/loongarch/lsx.md index 76d33a3b88a..a1632accdd9 100644 --- a/gcc/config/loongarch/lsx.md +++ b/gcc/config/loongarch/lsx.md @@ -1505,7 +1505,7 @@ (define_insn "lsx_vfrecipe_" [(set (match_operand:FLSX 0 "register_operand" "=f") (unspec:FLSX [(match_operand:FLSX 1 "register_operand" "f")] UNSPEC_LSX_VFRECIPE))] - "ISA_HAS_LSX && TARGET_FRECIPE" + "ISA_HAS_LSX && ISA_HAS_FRECIPE" "vfrecipe.\t%w0,%w1" [(set_attr "type" "simd_fdiv") (set_attr "mode" "")]) @@ -1538,7 +1538,7 @@ (define_insn "lsx_vfrsqrte_" [(set (match_operand:FLSX 0 "register_operand" "=f") (unspec:FLSX [(match_operand:FLSX 1 "register_operand" "f")] UNSPEC_LSX_VFRSQRTE))] - "ISA_HAS_LSX && TARGET_FRECIPE" + "ISA_HAS_LSX && ISA_HAS_FRECIPE" "vfrsqrte.\t%w0,%w1" [(set_attr "type" "simd_fdiv") (set_attr "mode" "")]) From patchwork Fri Jan 5 06:55:33 2024 Content-Type: text/plain; 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bh=cFgXR4yrK5vy7e80lYobMzgywgzuFi3Q64fpE4GlqRc=; h=From:To:Subject:Date:Message-ID:MIME-Version; b=XHlAOp4ndyECG699qPTZQbMjwcKH34OXhi67g+PJp+rbRn9OL4v7QtBxC/IvyJ2uEu9aQpH0jTFabuG53jXjKhrZQd75mKb2MnZppWsCHzKkcT3xWYz20gr7cH+hjHrkR2IddmLPJyYCtl7HKlQ4q/40almY/4a4aDNoUb3/jAA= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from loongson.cn (unknown [114.243.106.119]) by gateway (Coremail) with SMTP id _____8AxSepXqZdl7DgCAA--.67S3; Fri, 05 Jan 2024 15:01:43 +0800 (CST) Received: from localhost.localdomain (unknown [114.243.106.119]) by localhost.localdomain (Coremail) with SMTP id AQAAf8AxjodPqZdlggMDAA--.318S4; Fri, 05 Jan 2024 15:01:37 +0800 (CST) From: Yang Yujie To: gcc-patches@gcc.gnu.org Cc: chenglulu@loongson.cn, xry111@xry111.site, xuchenghua@loongson.cn, Yang Yujie Subject: [PATCH 2/4] LoongArch: Rename ISA_BASE_LA64V100 to ISA_BASE_LA64 Date: Fri, 5 Jan 2024 14:55:33 +0800 Message-ID: <20240105065535.1364530-3-yangyujie@loongson.cn> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240105065535.1364530-1-yangyujie@loongson.cn> References: <20240105065535.1364530-1-yangyujie@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf8AxjodPqZdlggMDAA--.318S4 X-CM-SenderInfo: 51dqw5pxmlvqxorr0wxvrqhubq/1tbiAQAHAGWXVSgHMwAAs9 X-Coremail-Antispam: 1Uk129KBj93XoW3AFW8GFy7ArW5Wr15Kr4rJFc_yoW3urykpF 9ruwsxJr48CrsxWr1Dt3s5Ww4DJ3s7Kr12q3Wftr18Cr47Xr1UZF48GFZxXF1jqa15try2 qrWFka1ava1UK3cCm3ZEXasCq-sJn29KB7ZKAUJUUUU8529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUkFb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Gr0_Cr1l84ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x0267AK xVW8Jr0_Cr1UM2AIxVAIcxkEcVAq07x20xvEncxIr21l57IF6xkI12xvs2x26I8E6xACxx 1l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r126r1DMcIj6I8E87Iv 67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41l42xK82IYc2 Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s02 6x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r126r1DMIIYrxkI7VAKI48JMIIF0x vE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r1j6r4UMIIF0xvE 42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6x kF7I0E14v26r1j6r4UYxBIdaVFxhVjvjDU0xZFpf9x07UMpBfUUUUU= X-Spam-Status: No, score=-10.0 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_NUMSUBJECT, RCVD_IN_BARRACUDACENTRAL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org LoongArch ISA manual v1.10 suggests that software should not depend on the ISA version number for marking processor features. The ISA version number is now defined as a collective name of individual ISA evolutions. Since there is a independent ISA evolution mask now, we can drop the version information from the base ISA. gcc/ChangeLog: * config/loongarch/genopts/loongarch-strings: Rename. * config/loongarch/genopts/loongarch.opt.in: Same. * config/loongarch/loongarch-cpu.cc: Same. * config/loongarch/loongarch-def.cc: Same. * config/loongarch/loongarch-def.h: Same. * config/loongarch/loongarch-opts.cc: Same. * config/loongarch/loongarch-opts.h: Same. * config/loongarch/loongarch-str.h: Same. * config/loongarch/loongarch.opt: Same. --- gcc/config/loongarch/genopts/loongarch-strings | 2 +- gcc/config/loongarch/genopts/loongarch.opt.in | 2 +- gcc/config/loongarch/loongarch-cpu.cc | 2 +- gcc/config/loongarch/loongarch-def.cc | 14 +++++++------- gcc/config/loongarch/loongarch-def.h | 6 +++--- gcc/config/loongarch/loongarch-opts.cc | 10 +++++----- gcc/config/loongarch/loongarch-opts.h | 2 +- gcc/config/loongarch/loongarch-str.h | 2 +- gcc/config/loongarch/loongarch.opt | 2 +- 9 files changed, 21 insertions(+), 21 deletions(-) diff --git a/gcc/config/loongarch/genopts/loongarch-strings b/gcc/config/loongarch/genopts/loongarch-strings index f40b014f017..ba47be31227 100644 --- a/gcc/config/loongarch/genopts/loongarch-strings +++ b/gcc/config/loongarch/genopts/loongarch-strings @@ -29,7 +29,7 @@ STR_CPU_LA464 la464 STR_CPU_LA664 la664 # Base architecture -STR_ISA_BASE_LA64V100 la64 +STR_ISA_BASE_LA64 la64 # -mfpu OPTSTR_ISA_EXT_FPU fpu diff --git a/gcc/config/loongarch/genopts/loongarch.opt.in b/gcc/config/loongarch/genopts/loongarch.opt.in index e643deacd21..38ac347c660 100644 --- a/gcc/config/loongarch/genopts/loongarch.opt.in +++ b/gcc/config/loongarch/genopts/loongarch.opt.in @@ -33,7 +33,7 @@ Name(isa_base) Type(int) Basic ISAs of LoongArch: EnumValue -Enum(isa_base) String(@@STR_ISA_BASE_LA64V100@@) Value(ISA_BASE_LA64V100) +Enum(isa_base) String(@@STR_ISA_BASE_LA64@@) Value(ISA_BASE_LA64) ;; ISA extensions / adjustments Enum diff --git a/gcc/config/loongarch/loongarch-cpu.cc b/gcc/config/loongarch/loongarch-cpu.cc index e1771fc0b4f..97ac5fed9d8 100644 --- a/gcc/config/loongarch/loongarch-cpu.cc +++ b/gcc/config/loongarch/loongarch-cpu.cc @@ -133,7 +133,7 @@ fill_native_cpu_config (struct loongarch_target *tgt) switch (cpucfg_cache[1] & 0x3) { case 0x02: - tmp = ISA_BASE_LA64V100; + tmp = ISA_BASE_LA64; break; default: diff --git a/gcc/config/loongarch/loongarch-def.cc b/gcc/config/loongarch/loongarch-def.cc index 48d28315064..e8c129ce643 100644 --- a/gcc/config/loongarch/loongarch-def.cc +++ b/gcc/config/loongarch/loongarch-def.cc @@ -48,16 +48,16 @@ array_arch loongarch_cpu_default_isa = array_arch () .set (CPU_LOONGARCH64, loongarch_isa () - .base_ (ISA_BASE_LA64V100) + .base_ (ISA_BASE_LA64) .fpu_ (ISA_EXT_FPU64)) .set (CPU_LA464, loongarch_isa () - .base_ (ISA_BASE_LA64V100) + .base_ (ISA_BASE_LA64) .fpu_ (ISA_EXT_FPU64) .simd_ (ISA_EXT_SIMD_LASX)) .set (CPU_LA664, loongarch_isa () - .base_ (ISA_BASE_LA64V100) + .base_ (ISA_BASE_LA64) .fpu_ (ISA_EXT_FPU64) .simd_ (ISA_EXT_SIMD_LASX) .evolution_ (OPTION_MASK_ISA_DIV32 | OPTION_MASK_ISA_LD_SEQ_SA @@ -153,7 +153,7 @@ array_tune loongarch_cpu_multipass_dfa_lookahead = array_tune () array loongarch_isa_base_strings = array () - .set (ISA_BASE_LA64V100, STR_ISA_BASE_LA64V100); + .set (ISA_BASE_LA64, STR_ISA_BASE_LA64); array loongarch_isa_ext_strings = array () @@ -189,15 +189,15 @@ array, N_ABI_BASE_TYPES> array () .set (ABI_EXT_BASE, loongarch_isa () - .base_ (ISA_BASE_LA64V100) + .base_ (ISA_BASE_LA64) .fpu_ (ISA_EXT_FPU64))) .set (ABI_BASE_LP64F, array () .set (ABI_EXT_BASE, loongarch_isa () - .base_ (ISA_BASE_LA64V100) + .base_ (ISA_BASE_LA64) .fpu_ (ISA_EXT_FPU32))) .set (ABI_BASE_LP64S, array () .set (ABI_EXT_BASE, - loongarch_isa ().base_ (ISA_BASE_LA64V100))); + loongarch_isa ().base_ (ISA_BASE_LA64))); diff --git a/gcc/config/loongarch/loongarch-def.h b/gcc/config/loongarch/loongarch-def.h index 1fab4f4d315..f8cb3adf509 100644 --- a/gcc/config/loongarch/loongarch-def.h +++ b/gcc/config/loongarch/loongarch-def.h @@ -55,9 +55,9 @@ along with GCC; see the file COPYING3. If not see /* enum isa_base */ -/* LoongArch V1.00. */ -#define ISA_BASE_LA64V100 0 -#define N_ISA_BASE_TYPES 1 +/* LoongArch64 */ +#define ISA_BASE_LA64 0 +#define N_ISA_BASE_TYPES 1 extern loongarch_def_array loongarch_isa_base_strings; diff --git a/gcc/config/loongarch/loongarch-opts.cc b/gcc/config/loongarch/loongarch-opts.cc index 9483060ab62..7eb1f2d4f2e 100644 --- a/gcc/config/loongarch/loongarch-opts.cc +++ b/gcc/config/loongarch/loongarch-opts.cc @@ -567,17 +567,17 @@ isa_default_abi (const struct loongarch_isa *isa) switch (isa->fpu) { case ISA_EXT_FPU64: - if (isa->base >= ISA_BASE_LA64V100) + if (isa->base >= ISA_BASE_LA64) abi.base = ABI_BASE_LP64D; break; case ISA_EXT_FPU32: - if (isa->base >= ISA_BASE_LA64V100) + if (isa->base >= ISA_BASE_LA64) abi.base = ABI_BASE_LP64F; break; case ISA_EXT_NONE: - if (isa->base >= ISA_BASE_LA64V100) + if (isa->base >= ISA_BASE_LA64) abi.base = ABI_BASE_LP64S; break; @@ -596,8 +596,8 @@ isa_base_compat_p (const struct loongarch_isa *set1, { switch (set2->base) { - case ISA_BASE_LA64V100: - return (set1->base >= ISA_BASE_LA64V100); + case ISA_BASE_LA64: + return (set1->base >= ISA_BASE_LA64); default: gcc_unreachable (); diff --git a/gcc/config/loongarch/loongarch-opts.h b/gcc/config/loongarch/loongarch-opts.h index c6545f691a1..36ad12cb480 100644 --- a/gcc/config/loongarch/loongarch-opts.h +++ b/gcc/config/loongarch/loongarch-opts.h @@ -79,7 +79,7 @@ struct loongarch_flags { #define TARGET_DOUBLE_FLOAT (la_target.isa.fpu == ISA_EXT_FPU64) #define TARGET_DOUBLE_FLOAT_ABI (la_target.abi.base == ABI_BASE_LP64D) -#define TARGET_64BIT (la_target.isa.base == ISA_BASE_LA64V100) +#define TARGET_64BIT (la_target.isa.base == ISA_BASE_LA64) #define TARGET_ABI_LP64 (la_target.abi.base == ABI_BASE_LP64D \ || la_target.abi.base == ABI_BASE_LP64F \ || la_target.abi.base == ABI_BASE_LP64S) diff --git a/gcc/config/loongarch/loongarch-str.h b/gcc/config/loongarch/loongarch-str.h index 2221c57f78e..0a6a36c5783 100644 --- a/gcc/config/loongarch/loongarch-str.h +++ b/gcc/config/loongarch/loongarch-str.h @@ -32,7 +32,7 @@ along with GCC; see the file COPYING3. If not see #define STR_CPU_LA464 "la464" #define STR_CPU_LA664 "la664" -#define STR_ISA_BASE_LA64V100 "la64" +#define STR_ISA_BASE_LA64 "la64" #define OPTSTR_ISA_EXT_FPU "fpu" #define STR_NONE "none" diff --git a/gcc/config/loongarch/loongarch.opt b/gcc/config/loongarch/loongarch.opt index 8b36f1a1495..76b42d51d09 100644 --- a/gcc/config/loongarch/loongarch.opt +++ b/gcc/config/loongarch/loongarch.opt @@ -41,7 +41,7 @@ Name(isa_base) Type(int) Basic ISAs of LoongArch: EnumValue -Enum(isa_base) String(la64) Value(ISA_BASE_LA64V100) +Enum(isa_base) String(la64) Value(ISA_BASE_LA64) ;; ISA extensions / adjustments Enum From patchwork Fri Jan 5 06:55:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yang Yujie X-Patchwork-Id: 1882752 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; 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Fri, 05 Jan 2024 02:01:54 -0500 Received: from loongson.cn (unknown [114.243.106.119]) by gateway (Coremail) with SMTP id _____8BxXetaqZdl8DgCAA--.8304S3; Fri, 05 Jan 2024 15:01:46 +0800 (CST) Received: from localhost.localdomain (unknown [114.243.106.119]) by localhost.localdomain (Coremail) with SMTP id AQAAf8AxjodPqZdlggMDAA--.318S5; Fri, 05 Jan 2024 15:01:43 +0800 (CST) From: Yang Yujie To: gcc-patches@gcc.gnu.org Cc: chenglulu@loongson.cn, xry111@xry111.site, xuchenghua@loongson.cn, Yang Yujie Subject: [PATCH 3/4] LoongArch: Use enums for constants Date: Fri, 5 Jan 2024 14:55:34 +0800 Message-ID: <20240105065535.1364530-4-yangyujie@loongson.cn> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240105065535.1364530-1-yangyujie@loongson.cn> References: <20240105065535.1364530-1-yangyujie@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf8AxjodPqZdlggMDAA--.318S5 X-CM-SenderInfo: 51dqw5pxmlvqxorr0wxvrqhubq/1tbiAQAHAGWXVSgHNQAAs7 X-Coremail-Antispam: 1Uk129KBj93XoWxAFykJF1UWFW8KrWrKF4UAwc_yoWrZw1xpa 9xu395tr40yFsxX34kt3s5u347Xr4xGrW2qa1agry8u3yDG348Wr4UGay5Xa4Yqa95K347 Xrn5X3W0v3W5GrXCm3ZEXasCq-sJn29KB7ZKAUJUUUU8529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUkFb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r106r15M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Gr0_Cr1l84ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x0267AK xVW8Jr0_Cr1UM2AIxVAIcxkEcVAq07x20xvEncxIr21l57IF6xkI12xvs2x26I8E6xACxx 1l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r126r1DMcIj6I8E87Iv 67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41l42xK82IYc2 Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s02 6x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r126r1DMIIYrxkI7VAKI48JMIIF0x vE2Ix0cI8IcVAFwI0_JFI_Gr1lIxAIcVC0I7IYx2IY6xkF7I0E14v26r1j6r4UMIIF0xvE 42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6x kF7I0E14v26r1j6r4UYxBIdaVFxhVjvjDU0xZFpf9x07j1LvtUUUUU= Received-SPF: pass client-ip=114.242.206.163; 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Switch to enums for better look in the debugger. gcc/ChangeLog: * config/loongarch/loongarch-def.h: Define constants with enums instead of Macros. --- gcc/config/loongarch/loongarch-def.h | 115 ++++++++++++++++----------- 1 file changed, 67 insertions(+), 48 deletions(-) diff --git a/gcc/config/loongarch/loongarch-def.h b/gcc/config/loongarch/loongarch-def.h index f8cb3adf509..a1237ecf1fd 100644 --- a/gcc/config/loongarch/loongarch-def.h +++ b/gcc/config/loongarch/loongarch-def.h @@ -23,12 +23,10 @@ along with GCC; see the file COPYING3. If not see - ISA extensions (isa_ext), - base ABI types (abi_base), - ABI extension types (abi_ext). - - - code models (cmodel) - - other command-line switches (switch) + - code models (cmodel) These values are primarily used for implementing option handling - logic in "loongarch.opt", "loongarch-driver.c" and "loongarch-opt.c". + logic in "loongarch.opt", "loongarch-driver.cc" and "loongarch-opt.cc". As for the result of this option handling process, the following scheme is adopted to represent the final configuration: @@ -53,30 +51,40 @@ along with GCC; see the file COPYING3. If not see #include "loongarch-def-array.h" #include "loongarch-tune.h" -/* enum isa_base */ -/* LoongArch64 */ -#define ISA_BASE_LA64 0 -#define N_ISA_BASE_TYPES 1 +/* ISA base */ +enum { + ISA_BASE_LA64 = 0, /* LoongArch64 */ + N_ISA_BASE_TYPES = 1 +}; + extern loongarch_def_array loongarch_isa_base_strings; -/* enum isa_ext_* */ -#define ISA_EXT_NONE 0 -#define ISA_EXT_FPU32 1 -#define ISA_EXT_FPU64 2 -#define N_ISA_EXT_FPU_TYPES 3 -#define ISA_EXT_SIMD_LSX 3 -#define ISA_EXT_SIMD_LASX 4 -#define N_ISA_EXT_TYPES 5 + +/* ISA extensions */ +enum { + ISA_EXT_NONE = 0, + ISA_EXT_FPU32 = 1, + ISA_EXT_FPU64 = 2, + N_ISA_EXT_FPU_TYPES = 3, + ISA_EXT_SIMD_LSX = 3, + ISA_EXT_SIMD_LASX = 4, + N_ISA_EXT_TYPES = 5 +}; + extern loongarch_def_array loongarch_isa_ext_strings; -/* enum abi_base */ -#define ABI_BASE_LP64D 0 -#define ABI_BASE_LP64F 1 -#define ABI_BASE_LP64S 2 -#define N_ABI_BASE_TYPES 3 + +/* Base ABI */ +enum { + ABI_BASE_LP64D = 0, + ABI_BASE_LP64F = 1, + ABI_BASE_LP64S = 2, + N_ABI_BASE_TYPES = 3 +}; + extern loongarch_def_array loongarch_abi_base_strings; @@ -90,28 +98,38 @@ extern loongarch_def_array (abi_base == ABI_BASE_LP64S) -/* enum abi_ext */ -#define ABI_EXT_BASE 0 -#define N_ABI_EXT_TYPES 1 +/* ABI Extension */ +enum { + ABI_EXT_BASE = 0, + N_ABI_EXT_TYPES = 1 +}; + extern loongarch_def_array loongarch_abi_ext_strings; -/* enum cmodel */ -#define CMODEL_NORMAL 0 -#define CMODEL_TINY 1 -#define CMODEL_TINY_STATIC 2 -#define CMODEL_MEDIUM 3 -#define CMODEL_LARGE 4 -#define CMODEL_EXTREME 5 -#define N_CMODEL_TYPES 6 + +/* Code Model */ +enum { + CMODEL_NORMAL = 0, + CMODEL_TINY = 1, + CMODEL_TINY_STATIC = 2, + CMODEL_MEDIUM = 3, + CMODEL_LARGE = 4, + CMODEL_EXTREME = 5, + N_CMODEL_TYPES = 6 +}; + extern loongarch_def_array loongarch_cmodel_strings; -/* enum explicit_relocs */ -#define EXPLICIT_RELOCS_AUTO 0 -#define EXPLICIT_RELOCS_NONE 1 -#define EXPLICIT_RELOCS_ALWAYS 2 -#define N_EXPLICIT_RELOCS_TYPES 3 + +/* Explicit Reloc Type */ +enum { + EXPLICIT_RELOCS_AUTO = 0, + EXPLICIT_RELOCS_NONE = 1, + EXPLICIT_RELOCS_ALWAYS = 2, + N_EXPLICIT_RELOCS_TYPES = 3 +}; /* The common default value for variables whose assignments are triggered by command-line options. */ @@ -159,17 +177,18 @@ struct loongarch_target int cmodel; /* CMODEL_ */ }; -/* CPU properties. */ -/* index */ -#define CPU_NATIVE 0 -#define CPU_ABI_DEFAULT 1 -#define CPU_LOONGARCH64 2 -#define CPU_LA464 3 -#define CPU_LA664 4 -#define N_ARCH_TYPES 5 -#define N_TUNE_TYPES 5 - -/* parallel tables. */ +/* CPU model */ +enum { + CPU_NATIVE = 0, + CPU_ABI_DEFAULT = 1, + CPU_LOONGARCH64 = 2, + CPU_LA464 = 3, + CPU_LA664 = 4, + N_ARCH_TYPES = 5, + N_TUNE_TYPES = 5 +}; + +/* CPU model properties */ extern loongarch_def_array loongarch_cpu_strings; extern loongarch_def_array From patchwork Fri Jan 5 06:55:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yang Yujie X-Patchwork-Id: 1882750 Return-Path: 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b=wGp+ZyJ8uZ77nvGVQ6Pac+vq28zmwkHibt1XBgCfL+mhLXJGXXZaCtnEXqsACphRwf/WcH57b9A9W9v8GhTxr5QJcREPP4YmNtrQllPzxdvvRTkafAx3bJph5wpt2zyWsD+WjUmWPlVic8rOgxinDeHa7O4ZoSDPE+42gNSXPek= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from loongson.cn (unknown [114.243.106.119]) by gateway (Coremail) with SMTP id _____8CxrutbqZdl8jgCAA--.8415S3; Fri, 05 Jan 2024 15:01:47 +0800 (CST) Received: from localhost.localdomain (unknown [114.243.106.119]) by localhost.localdomain (Coremail) with SMTP id AQAAf8AxjodPqZdlggMDAA--.318S6; Fri, 05 Jan 2024 15:01:46 +0800 (CST) From: Yang Yujie To: gcc-patches@gcc.gnu.org Cc: chenglulu@loongson.cn, xry111@xry111.site, xuchenghua@loongson.cn, Yang Yujie Subject: [PATCH 4/4] LoongArch: Simplify -mexplicit-reloc definitions Date: Fri, 5 Jan 2024 14:55:35 +0800 Message-ID: <20240105065535.1364530-5-yangyujie@loongson.cn> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240105065535.1364530-1-yangyujie@loongson.cn> References: <20240105065535.1364530-1-yangyujie@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf8AxjodPqZdlggMDAA--.318S6 X-CM-SenderInfo: 51dqw5pxmlvqxorr0wxvrqhubq/1tbiAQAHAGWXVSgHNwAAs5 X-Coremail-Antispam: 1Uk129KBj93XoW3JrWrGw4rtr4DJr1kuFWUJrc_yoW7WF4Dp3 43Zwnxtr48KFs7Kw1DtFyfWw1UA347Gr12qa1aqry8ua17GryFvFn5tr9xXFy7Wa1rt3yI qF1Fga1jv3W5G3cCm3ZEXasCq-sJn29KB7ZKAUJUUUU8529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUkFb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r1Y6r17M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Gr0_Cr1l84ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x0267AK xVW8Jr0_Cr1UM2AIxVAIcxkEcVAq07x20xvEncxIr21l57IF6xkI12xvs2x26I8E6xACxx 1l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r1q6rW5McIj6I8E87Iv 67AKxVW8JVWxJwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41l42xK82IYc2 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attributes to be supported later) it can be handled in the .opt file framework. gcc/ChangeLog: * config/loongarch/genopts/loongarch-strings: Remove explicit-reloc argument string definitions. * config/loongarch/loongarch-str.h: Same. * config/loongarch/genopts/loongarch.opt.in: Mark -m[no-]explicit-relocs as aliases to -mexplicit-relocs={always,none} * config/loongarch/genopts/loongarch.opt: Same. * config/loongarch/loongarch.cc: Same. --- gcc/config/loongarch/genopts/loongarch-strings | 6 ------ gcc/config/loongarch/genopts/loongarch.opt.in | 8 ++++---- gcc/config/loongarch/loongarch-str.h | 5 ----- gcc/config/loongarch/loongarch.cc | 12 ------------ gcc/config/loongarch/loongarch.opt | 2 +- 5 files changed, 5 insertions(+), 28 deletions(-) diff --git a/gcc/config/loongarch/genopts/loongarch-strings b/gcc/config/loongarch/genopts/loongarch-strings index ba47be31227..e434a89c9ee 100644 --- a/gcc/config/loongarch/genopts/loongarch-strings +++ b/gcc/config/loongarch/genopts/loongarch-strings @@ -64,9 +64,3 @@ STR_CMODEL_TS tiny-static STR_CMODEL_MEDIUM medium STR_CMODEL_LARGE large STR_CMODEL_EXTREME extreme - -# -mexplicit-relocs -OPTSTR_EXPLICIT_RELOCS explicit-relocs -STR_EXPLICIT_RELOCS_AUTO auto -STR_EXPLICIT_RELOCS_NONE none -STR_EXPLICIT_RELOCS_ALWAYS always diff --git a/gcc/config/loongarch/genopts/loongarch.opt.in b/gcc/config/loongarch/genopts/loongarch.opt.in index 38ac347c660..1dbd3ad1e3f 100644 --- a/gcc/config/loongarch/genopts/loongarch.opt.in +++ b/gcc/config/loongarch/genopts/loongarch.opt.in @@ -181,20 +181,20 @@ Name(explicit_relocs) Type(int) The code model option names for -mexplicit-relocs: EnumValue -Enum(explicit_relocs) String(@@STR_EXPLICIT_RELOCS_AUTO@@) Value(EXPLICIT_RELOCS_AUTO) +Enum(explicit_relocs) String(auto) Value(EXPLICIT_RELOCS_AUTO) EnumValue -Enum(explicit_relocs) String(@@STR_EXPLICIT_RELOCS_NONE@@) Value(EXPLICIT_RELOCS_NONE) +Enum(explicit_relocs) String(none) Value(EXPLICIT_RELOCS_NONE) EnumValue -Enum(explicit_relocs) String(@@STR_EXPLICIT_RELOCS_ALWAYS@@) Value(EXPLICIT_RELOCS_ALWAYS) +Enum(explicit_relocs) String(always) Value(EXPLICIT_RELOCS_ALWAYS) mexplicit-relocs= Target RejectNegative Joined Enum(explicit_relocs) Var(la_opt_explicit_relocs) Init(M_OPT_UNSET) Use %reloc() assembly operators. mexplicit-relocs -Target Var(la_opt_explicit_relocs_backward) Init(M_OPT_UNSET) +Target Alias(mexplicit-relocs=, always, none) Use %reloc() assembly operators (for backward compatibility). mrecip diff --git a/gcc/config/loongarch/loongarch-str.h b/gcc/config/loongarch/loongarch-str.h index 0a6a36c5783..20da2b169ed 100644 --- a/gcc/config/loongarch/loongarch-str.h +++ b/gcc/config/loongarch/loongarch-str.h @@ -63,11 +63,6 @@ along with GCC; see the file COPYING3. If not see #define STR_CMODEL_LARGE "large" #define STR_CMODEL_EXTREME "extreme" -#define OPTSTR_EXPLICIT_RELOCS "explicit-relocs" -#define STR_EXPLICIT_RELOCS_AUTO "auto" -#define STR_EXPLICIT_RELOCS_NONE "none" -#define STR_EXPLICIT_RELOCS_ALWAYS "always" - #define OPTSTR_FRECIPE "frecipe" #define OPTSTR_DIV32 "div32" #define OPTSTR_LAM_BH "lam-bh" diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc index ce760fda009..8379ae28606 100644 --- a/gcc/config/loongarch/loongarch.cc +++ b/gcc/config/loongarch/loongarch.cc @@ -7533,18 +7533,6 @@ loongarch_option_override_internal (struct gcc_options *opts, loongarch_update_gcc_opt_status (&la_target, opts, opts_set); loongarch_cpu_option_override (&la_target, opts, opts_set); - if (la_opt_explicit_relocs != M_OPT_UNSET - && la_opt_explicit_relocs_backward != M_OPT_UNSET) - error ("do not use %qs (with %qs) and %qs (without %qs) together", - "-mexplicit-relocs=", "=", - la_opt_explicit_relocs_backward ? "-mexplicit-relocs" - : "-mno-explicit-relocs", "="); - - if (la_opt_explicit_relocs_backward != M_OPT_UNSET) - la_opt_explicit_relocs = (la_opt_explicit_relocs_backward - ? EXPLICIT_RELOCS_ALWAYS - : EXPLICIT_RELOCS_NONE); - if (la_opt_explicit_relocs == M_OPT_UNSET) la_opt_explicit_relocs = (HAVE_AS_EXPLICIT_RELOCS ? (loongarch_mrelax diff --git a/gcc/config/loongarch/loongarch.opt b/gcc/config/loongarch/loongarch.opt index 76b42d51d09..adb2304fbd5 100644 --- a/gcc/config/loongarch/loongarch.opt +++ b/gcc/config/loongarch/loongarch.opt @@ -202,7 +202,7 @@ Target RejectNegative Joined Enum(explicit_relocs) Var(la_opt_explicit_relocs) I Use %reloc() assembly operators. mexplicit-relocs -Target Var(la_opt_explicit_relocs_backward) Init(M_OPT_UNSET) +Target Alias(mexplicit-relocs=, always, none) Use %reloc() assembly operators (for backward compatibility). mrecip