From patchwork Fri Dec 22 23:07:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?6ZKf5bGF5ZOy?= X-Patchwork-Id: 1879811 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SxjdT1HZcz20R5 for ; Sat, 23 Dec 2023 10:08:10 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9BC043858433 for ; Fri, 22 Dec 2023 23:08:07 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbg153.qq.com (smtpbg153.qq.com [13.245.218.24]) by sourceware.org (Postfix) with ESMTPS id 750F43858408 for ; Fri, 22 Dec 2023 23:07:50 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 750F43858408 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 750F43858408 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=13.245.218.24 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1703286475; cv=none; b=cgeQpVdhI68WsFefbj24tMjYOH1JkmTaNPUSzPmONy7tCZvMUNr3X0YFsnrLadcMLzdDueP8UKrK7GBbMpXnf/Q9p8UAcq6CwsxkFjHmRdHrmJjY0Nlx7Mq5f4oGQDNFgFG6fwhG7YJK4N4PGgOaz6ntoremiW6a6wF52ZBw7ag= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1703286475; c=relaxed/simple; bh=jmnar3Qk5/hIf1hiDdCm+Y+yD1gIewaQnL0pLQz6QHs=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=ZovysINB7FygAex46oC5LnULxbNldNEY+IYC0xFj2sw24y4CB/Ph0Z3fNcN4dCaq4VvXZ9g+8K62fJ/NR9/YN6n1OH8HblIa01AKRl0o2wX+gHhUa2fXc4zn/6zF5usPM9EQEbVRVJ98KpQsC0C+KCJxlpYosGgeeQekeM0mvAg= ARC-Authentication-Results: i=1; server2.sourceware.org X-QQ-mid: bizesmtp83t1703286464ts06qg38 Received: from rios-cad121.hadoop.rioslab.org ( [58.60.1.9]) by bizesmtp.qq.com (ESMTP) with id ; Sat, 23 Dec 2023 07:07:43 +0800 (CST) X-QQ-SSF: 01400000002000G0V000B00A0000000 X-QQ-FEAT: ERSZEewZJunRMHQ1NU2AG73mJeLpnyYh0ulBwKXI2WRdnzt67F3Rp9bZgBj6c 8HBBNkhNz1mcuuDXTBLZ9f/lVGY3ZSdjJmG4aIoTX2chut+FpVyYED2T6LYQ2ljISVhu6Bl +dFHGvQydz/yyxjiltENrxhQDGfqGCXbASEmWQWJHjIwnI4y2+RZ9ZfIJ6WXm4orDYeKZ8+ Eecg975o0TsOe/h9KYgrMTBb0aaJobEXrsrOGzjD+Uszdtv9u+B+FN9gyIOLxR0U79soIwY Hs9Yp3C4YlKlNLG2IIFJL9Mj3nWQ4TUNYsjx/cfTuauIOvDBoRNBuSqFsVciKVCeKkzTTpw fnlOxWrZWeoJ7PSbcXNn9aBDptYuuEubmfdt0PF1GGImu1MD6PV0zfoqcTVCtYiA5aPf6Z6 X-QQ-GoodBg: 2 X-BIZMAIL-ID: 10612553563296226989 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: Juzhe-Zhong Subject: [Committed] RISC-V: Make PHI initial value occupy live V_REG in dynamic LMUL cost model analysis Date: Sat, 23 Dec 2023 07:07:42 +0800 Message-Id: <20231222230742.1807755-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SCC_5_SHORT_WORD_LINES, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Consider this following case: foo: ble a0,zero,.L11 lui a2,%hi(.LANCHOR0) addi sp,sp,-128 addi a2,a2,%lo(.LANCHOR0) mv a1,a0 vsetvli a6,zero,e32,m8,ta,ma vid.v v8 vs8r.v v8,0(sp) ---> spill .L3: vl8re32.v v16,0(sp) ---> reload vsetvli a4,a1,e8,m2,ta,ma li a3,0 vsetvli a5,zero,e32,m8,ta,ma vmv8r.v v0,v16 vmv.v.x v8,a4 vmv.v.i v24,0 vadd.vv v8,v16,v8 vmv8r.v v16,v24 vs8r.v v8,0(sp) ---> spill .L4: addiw a3,a3,1 vadd.vv v8,v0,v16 vadd.vi v16,v16,1 vadd.vv v24,v24,v8 bne a0,a3,.L4 vsetvli zero,a4,e32,m8,ta,ma sub a1,a1,a4 vse32.v v24,0(a2) slli a4,a4,2 add a2,a2,a4 bne a1,zero,.L3 li a0,0 addi sp,sp,128 jr ra .L11: li a0,0 ret Pick unexpected LMUL = 8. The root cause is we didn't involve PHI initial value in the dynamic LMUL calculation: # j_17 = PHI ---> # vect_vec_iv_.8_24 = PHI <_25(9), { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }(5)> We didn't count { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } in consuming vector register but it does allocate an vector register group for it. This patch fixes this missing count. Then after this patch we pick up perfect LMUL (LMUL = M4) foo: ble a0,zero,.L9 lui a4,%hi(.LANCHOR0) addi a4,a4,%lo(.LANCHOR0) mv a2,a0 vsetivli zero,16,e32,m4,ta,ma vid.v v20 .L3: vsetvli a3,a2,e8,m1,ta,ma li a5,0 vsetivli zero,16,e32,m4,ta,ma vmv4r.v v16,v20 vmv.v.i v12,0 vmv.v.x v4,a3 vmv4r.v v8,v12 vadd.vv v20,v20,v4 .L4: addiw a5,a5,1 vmv4r.v v4,v8 vadd.vi v8,v8,1 vadd.vv v4,v16,v4 vadd.vv v12,v12,v4 bne a0,a5,.L4 slli a5,a3,2 vsetvli zero,a3,e32,m4,ta,ma sub a2,a2,a3 vse32.v v12,0(a4) add a4,a4,a5 bne a2,zero,.L3 .L9: li a0,0 ret Tested on --with-arch=gcv no regression. PR target/113112 gcc/ChangeLog: * config/riscv/riscv-vector-costs.cc (max_number_of_live_regs): Refine dump information. (preferred_new_lmul_p): Make PHI initial value into live regs calculation. gcc/testsuite/ChangeLog: * gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.c: New test. --- gcc/config/riscv/riscv-vector-costs.cc | 45 ++++++++++++++++--- .../vect/costmodel/riscv/rvv/pr113112-1.c | 31 +++++++++++++ 2 files changed, 71 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.c diff --git a/gcc/config/riscv/riscv-vector-costs.cc b/gcc/config/riscv/riscv-vector-costs.cc index a316603e207..946eb4a9fc6 100644 --- a/gcc/config/riscv/riscv-vector-costs.cc +++ b/gcc/config/riscv/riscv-vector-costs.cc @@ -355,10 +355,11 @@ max_number_of_live_regs (const basic_block bb, } if (dump_enabled_p ()) - dump_printf_loc (MSG_NOTE, vect_location, - "Maximum lmul = %d, %d number of live V_REG at program " - "point %d for bb %d\n", - lmul, max_nregs, live_point, bb->index); + dump_printf_loc ( + MSG_NOTE, vect_location, + "Maximum lmul = %d, At most %d number of live V_REG at program " + "point %d for bb %d\n", + lmul, max_nregs, live_point, bb->index); return max_nregs; } @@ -472,6 +473,41 @@ update_local_live_ranges ( tree def = gimple_phi_arg_def (phi, j); auto *live_ranges = live_ranges_per_bb.get (bb); auto *live_range = live_ranges->get (def); + if (poly_int_tree_p (def)) + { + /* Insert live range of INTEGER_CST or POLY_CST since we will + need to allocate a vector register for it. + + E.g. # j_17 = PHI will be transformed + into # vect_vec_iv_.8_24 = PHI <_25(9), { 0, ... }(5)> + + The live range for such value is short which only lives + from program point 0 to 1. */ + if (live_range) + { + unsigned int start = (*live_range).first; + (*live_range).first = 0; + if (dump_enabled_p ()) + dump_printf_loc ( + MSG_NOTE, vect_location, + "Update %T start point from %d to 0:\n", def, start); + } + else + { + live_ranges->put (def, pair (0, 1)); + auto &program_points = (*program_points_per_bb.get (bb)); + if (program_points.is_empty ()) + { + stmt_point info = {1, phi}; + program_points.safe_push (info); + } + if (dump_enabled_p ()) + dump_printf_loc (MSG_NOTE, vect_location, + "Add %T start point from 0 to 1:\n", + def); + } + continue; + } if (live_range && flow_bb_inside_loop_p (loop, e->src)) { unsigned int start = (*live_range).first; @@ -580,7 +616,6 @@ preferred_new_lmul_p (loop_vec_info other_loop_vinfo) biggest_mode, lmul); if (nregs > max_nregs) max_nregs = nregs; - live_ranges_per_bb.empty (); } live_ranges_per_bb.empty (); return max_nregs > V_REG_NUM; diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.c new file mode 100644 index 00000000000..a44a1c041af --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */ + +#define N 40 + +int a[N]; + +__attribute__ ((noinline)) int +foo (int n){ + int i,j; + int sum,x; + + for (i = 0; i < n; i++) { + sum = 0; + for (j = 0; j < n; j++) { + sum += (i + j); + } + a[i] = sum; + } + return 0; +} + +/* { dg-final { scan-assembler-not {jr} } } */ +/* { dg-final { scan-assembler-times {ret} 1 } } */ +/* { dg-final { scan-tree-dump "Maximum lmul = 8" "vect" } } */ +/* { dg-final { scan-tree-dump "Maximum lmul = 4" "vect" } } */ +/* { dg-final { scan-tree-dump-not "Maximum lmul = 2" "vect" } } */ +/* { dg-final { scan-tree-dump-not "Maximum lmul = 1" "vect" } } */ +/* { dg-final { scan-tree-dump "At most 8 number of live V_REG at program point 0 for bb 4" "vect" } } */ +/* { dg-final { scan-tree-dump "At most 40 number of live V_REG at program point 0 for bb 3" "vect" } } */ +/* { dg-final { scan-tree-dump "At most 8 number of live V_REG at program point 0 for bb 5" "vect" } } */