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(unknown [IPv6:240e:358:11ec:9900:dc73:854d:832e:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (Client did not present a certificate) (Authenticated sender: xry111@xry111.site) by xry111.site (Postfix) with ESMTPSA id 04FA466DDD; Sun, 17 Dec 2023 10:17:21 -0500 (EST) From: Xi Ruoyao To: gcc-patches@gcc.gnu.org Cc: chenglulu , i@xen0n.name, xuchenghua@loongson.cn, Xi Ruoyao Subject: [PATCH] LoongArch: Add sign_extend pattern for 32-bit rotate shift Date: Sun, 17 Dec 2023 23:16:37 +0800 Message-ID: <20231217151713.4959-1-xry111@xry111.site> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-Spam-Status: No, score=-9.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, LIKELY_SPAM_FROM, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Remove a redundant sign extension. gcc/ChangeLog: * config/loongarch/loongarch.md (rotrsi3_extend): New define_insn. gcc/testsuite/ChangeLog: * gcc.target/loongarch/rotrw.c: New test. --- Bootstrapped and regtested on loongarch64-linux-gnu. Ok for trunk? gcc/config/loongarch/loongarch.md | 10 ++++++++++ gcc/testsuite/gcc.target/loongarch/rotrw.c | 17 +++++++++++++++++ 2 files changed, 27 insertions(+) create mode 100644 gcc/testsuite/gcc.target/loongarch/rotrw.c diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md index c7058282a21..30025bf1908 100644 --- a/gcc/config/loongarch/loongarch.md +++ b/gcc/config/loongarch/loongarch.md @@ -2893,6 +2893,16 @@ (define_insn "rotr3" [(set_attr "type" "shift,shift") (set_attr "mode" "")]) +(define_insn "rotrsi3_extend" + [(set (match_operand:DI 0 "register_operand" "=r,r") + (sign_extend:DI + (rotatert:SI (match_operand:SI 1 "register_operand" "r,r") + (match_operand:SI 2 "arith_operand" "r,I"))))] + "TARGET_64BIT" + "rotr%i2.w\t%0,%1,%2" + [(set_attr "type" "shift,shift") + (set_attr "mode" "SI")]) + ;; The following templates were added to generate "bstrpick.d + alsl.d" ;; instruction pairs. ;; It is required that the values of const_immalsl_operand and diff --git a/gcc/testsuite/gcc.target/loongarch/rotrw.c b/gcc/testsuite/gcc.target/loongarch/rotrw.c new file mode 100644 index 00000000000..6ed45e8b86c --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/rotrw.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { scan-assembler "rotr\\.w\t\\\$r4,\\\$r4,\\\$r5" } } */ +/* { dg-final { scan-assembler "rotri\\.w\t\\\$r4,\\\$r4,5" } } */ +/* { dg-final { scan-assembler-not "slli\\.w" } } */ + +unsigned +rotr (unsigned a, unsigned b) +{ + return a >> b | a << 32 - b; +} + +unsigned +rotri (unsigned a) +{ + return a >> 5 | a << 27; +}