From patchwork Thu Dec 14 21:07:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Thomas Schwinge X-Patchwork-Id: 1876387 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SrlLV17rJz23nF for ; Fri, 15 Dec 2023 08:08:00 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 8A5C038618B0 for ; Thu, 14 Dec 2023 21:07:58 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from esa2.mentor.iphmx.com (esa2.mentor.iphmx.com [68.232.141.98]) by sourceware.org (Postfix) with ESMTPS id A72D73858D20 for ; Thu, 14 Dec 2023 21:07:44 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A72D73858D20 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=codesourcery.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=mentor.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org A72D73858D20 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=68.232.141.98 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1702588067; cv=none; b=SjaontTQlbylonck6m7DOtY6yTVv0ssF6+pf22LBUqILllVVD9nNzfGXazLfcl6LpiGZf6oljInNfR22EGPLcmqFkfrum/VhvqHDM4accddl7a1gh7BtlZzxH96XnruuhHm4uO2zRtV+LUflLPTKnbxvsiRfaDFHxtx6QCiAb5c= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1702588067; c=relaxed/simple; bh=rG8LrZp8XCmDOEG/OIDrFXy3qUessowWzvGvfq65Ptg=; h=From:To:Subject:Date:Message-ID:MIME-Version; b=TGa0h0eyqzuFa/zAUQWlx2qsylkCvPOaJXTY4RXxx0zELFb3JA4dSfKybtTk7e+0f8BuJmpChKOOAr3hl4dPbKDJU15wm5fFAlQp9YWWGmmB1kUuXb/X5RkDCj1k6VoydDAjG1Nq+4CV/IkqyXM+g/IzIyLiwEeE5i/XkK3tDto= ARC-Authentication-Results: i=1; server2.sourceware.org X-CSE-ConnectionGUID: 1gVdsfkbT+S7ppAhjVhXNQ== X-CSE-MsgGUID: BzTw33RuSTCSgldjtoEPAg== X-IronPort-AV: E=Sophos;i="6.04,276,1695715200"; d="scan'208,223";a="28304315" Received: from orw-gwy-02-in.mentorg.com ([192.94.38.167]) by esa2.mentor.iphmx.com with ESMTP; 14 Dec 2023 13:07:43 -0800 IronPort-SDR: qIXD1NDl5AMveVvBfP9hkXlElRe+IpX0mjTj/PqzTaziY7pm1jXdNaiEL2umXwF13jIVDoImsv NeU1eWj5R9wyvURmP5tIhYE6fyuydsz7Bq8pTsT8Muowj319stbS90w+g1hoxIy04E7QMN6W6e +5gHc5VkZDsJ1arPl+YBf4rCovIHQjQMy+vge+r6mipOL94lz6N/DiSC2Chrh023PuCEM8q98E X96MAUyIIEiKq/nGQVFte1Zje8HD1CMs/N18cS52LcGjScNeqKVmfDIGiTsOkvlO1kaTjX5kRk FT0= From: Thomas Schwinge To: "Andre Vieira (lists)" , , Andrew Stubbs , "Julian Brown" CC: Jakub Jelinek , Kyrylo Tkachov , Subject: Update 'gcc.dg/vect/vect-simd-clone-*.c' GCN 'dg-warning's (was: [PATCH] aarch64: enable mixed-types for aarch64 simdclones) In-Reply-To: <6d99ea34-78df-4807-8e83-00695d729517@arm.com> References: <9322d3d7-5188-fd49-7902-74efa5d65da7@arm.com> <48784e1a-b3b3-4b89-8d59-9c25cb943856@arm.com> <6d99ea34-78df-4807-8e83-00695d729517@arm.com> User-Agent: Notmuch/0.29.3+94~g74c3f1b (https://notmuchmail.org) Emacs/28.2 (x86_64-pc-linux-gnu) Date: Thu, 14 Dec 2023 22:07:36 +0100 Message-ID: <87il504hnr.fsf@euler.schwinge.homeip.net> MIME-Version: 1.0 X-Originating-IP: [137.202.0.90] X-ClientProxiedBy: svr-ies-mbx-12.mgc.mentorg.com (139.181.222.12) To svr-ies-mbx-10.mgc.mentorg.com (139.181.222.10) X-Spam-Status: No, score=-11.8 required=5.0 tests=BAYES_00, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Hi! On 2023-10-16T16:03:26+0100, "Andre Vieira (lists)" wrote: > --- a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-1.c > +++ b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-1.c > @@ -12,8 +12,13 @@ int array[N]; > > #pragma omp declare simd simdlen(4) notinbranch > #pragma omp declare simd simdlen(4) notinbranch uniform(b) linear(c:3) > +#ifdef __aarch64__ > +#pragma omp declare simd simdlen(2) notinbranch > +#pragma omp declare simd simdlen(2) notinbranch uniform(b) linear(c:3) > +#else > #pragma omp declare simd simdlen(8) notinbranch > #pragma omp declare simd simdlen(8) notinbranch uniform(b) linear(c:3) > +#endif > __attribute__((noinline)) int > foo (int a, int b, int c) > { These added lines run afoul with end-of-file GCN-specific DejaGnu directives: [...] /* { dg-warning {unsupported simdlen 8 \(amdgcn\)} "" { target amdgcn*-*-* } 18 } */ /* { dg-warning {unsupported simdlen 4 \(amdgcn\)} "" { target amdgcn*-*-* } 18 } */ That, indeed, also has been suboptimal, to use absolute lines numbers here. (..., and maybe, like aarch64 have now done, GCN also should suitably parameterize the 'simdlen', to resolve this altogether? Until then, to resolve regressions, I've pushed to master branch commit 7b15959f8e35b821ebfe832a36e5e712b708dae1 "Update 'gcc.dg/vect/vect-simd-clone-*.c' GCN 'dg-warning's", see attached. Grüße Thomas > --- a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-2.c > +++ b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-2.c > @@ -12,8 +12,13 @@ int array[N] __attribute__((aligned (32))); > > #pragma omp declare simd simdlen(4) notinbranch aligned(a:16) uniform(a) linear(b) > #pragma omp declare simd simdlen(4) notinbranch aligned(a:32) uniform(a) linear(b) > +#ifdef __aarch64__ > +#pragma omp declare simd simdlen(2) notinbranch aligned(a:16) uniform(a) linear(b) > +#pragma omp declare simd simdlen(2) notinbranch aligned(a:32) uniform(a) linear(b) > +#else > #pragma omp declare simd simdlen(8) notinbranch aligned(a:16) uniform(a) linear(b) > #pragma omp declare simd simdlen(8) notinbranch aligned(a:32) uniform(a) linear(b) > +#endif > __attribute__((noinline)) void > foo (int *a, int b, int c) > { > --- a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-4.c > +++ b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-4.c > @@ -12,7 +12,11 @@ float d[N]; > int e[N]; > unsigned short f[N]; > > +#ifdef __aarch64__ > +#pragma omp declare simd simdlen(4) notinbranch uniform(b) > +#else > #pragma omp declare simd simdlen(8) notinbranch uniform(b) > +#endif > __attribute__((noinline)) float > foo (float a, float b, float c) > { > --- a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-5.c > +++ b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-5.c > @@ -10,7 +10,11 @@ > > int d[N], e[N]; > > +#ifdef __aarch64__ > +#pragma omp declare simd simdlen(2) notinbranch uniform(b) linear(c:3) > +#else > #pragma omp declare simd simdlen(4) notinbranch uniform(b) linear(c:3) > +#endif > __attribute__((noinline)) long long int > foo (int a, int b, int c) > { > --- a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-8.c > +++ b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-8.c > @@ -12,14 +12,22 @@ int a[N], b[N]; > long int c[N]; > unsigned char d[N]; > > +#ifdef __aarch64__ > +#pragma omp declare simd simdlen(2) notinbranch > +#else > #pragma omp declare simd simdlen(8) notinbranch > +#endif > __attribute__((noinline)) int > foo (long int a, int b, int c) > { > return a + b + c; > } > > +#ifdef __aarch64__ > +#pragma omp declare simd simdlen(2) notinbranch > +#else > #pragma omp declare simd simdlen(8) notinbranch > +#endif > __attribute__((noinline)) long int > bar (int a, int b, long int c) > { ----------------- Siemens Electronic Design Automation GmbH; Anschrift: Arnulfstraße 201, 80634 München; Gesellschaft mit beschränkter Haftung; Geschäftsführer: Thomas Heurung, Frank Thürauf; Sitz der Gesellschaft: München; Registergericht München, HRB 106955 From 7b15959f8e35b821ebfe832a36e5e712b708dae1 Mon Sep 17 00:00:00 2001 From: Thomas Schwinge Date: Thu, 14 Dec 2023 10:47:35 +0100 Subject: [PATCH] Update 'gcc.dg/vect/vect-simd-clone-*.c' GCN 'dg-warning's Recent commit f5fc001a84a7dbb942a6252b3162dd38b4aae311 "aarch64: enable mixed-types for aarch64 simdclones" added lines to those test cases and GCN-specific line numbers got out of sync, which had originally gotten added in commit b73c49f6f88dd7f7569f9a72c8ceb04598d4c15c "amdgcn: OpenMP SIMD routine support". gcc/testsuite/ * gcc.dg/vect/vect-simd-clone-1.c: Update GCN 'dg-warning's. * gcc.dg/vect/vect-simd-clone-2.c: Likewise. * gcc.dg/vect/vect-simd-clone-3.c: Likewise. * gcc.dg/vect/vect-simd-clone-4.c: Likewise. * gcc.dg/vect/vect-simd-clone-5.c: Likewise. * gcc.dg/vect/vect-simd-clone-8.c: Likewise. --- gcc/testsuite/gcc.dg/vect/vect-simd-clone-1.c | 5 ++--- gcc/testsuite/gcc.dg/vect/vect-simd-clone-2.c | 5 ++--- gcc/testsuite/gcc.dg/vect/vect-simd-clone-3.c | 3 +-- gcc/testsuite/gcc.dg/vect/vect-simd-clone-4.c | 3 +-- gcc/testsuite/gcc.dg/vect/vect-simd-clone-5.c | 3 +-- gcc/testsuite/gcc.dg/vect/vect-simd-clone-8.c | 5 ++--- 6 files changed, 9 insertions(+), 15 deletions(-) diff --git a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-1.c b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-1.c index ec6d2daaa29..6bd4af36710 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-1.c +++ b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-1.c @@ -21,6 +21,8 @@ int array[N]; #endif __attribute__((noinline)) int foo (int a, int b, int c) +/* { dg-warning {unsupported simdlen 8 \(amdgcn\)} "" { target amdgcn*-*-* } .-1 } */ +/* { dg-warning {unsupported simdlen 4 \(amdgcn\)} "" { target amdgcn*-*-* } .-2 } */ { if (a < 30) return 5; @@ -62,6 +64,3 @@ main () abort (); return 0; } - -/* { dg-warning {unsupported simdlen 8 \(amdgcn\)} "" { target amdgcn*-*-* } 18 } */ -/* { dg-warning {unsupported simdlen 4 \(amdgcn\)} "" { target amdgcn*-*-* } 18 } */ diff --git a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-2.c b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-2.c index 13fc93614b4..e31280ad15d 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-2.c +++ b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-2.c @@ -21,6 +21,8 @@ int array[N] __attribute__((aligned (32))); #endif __attribute__((noinline)) void foo (int *a, int b, int c) +/* { dg-warning {unsupported simdlen 8 \(amdgcn\)} "" { target amdgcn*-*-* } .-1 } */ +/* { dg-warning {unsupported simdlen 4 \(amdgcn\)} "" { target amdgcn*-*-* } .-2 } */ { a[b] = c; } @@ -55,6 +57,3 @@ main () abort (); return 0; } - -/* { dg-warning {unsupported simdlen 8 \(amdgcn\)} "" { target amdgcn*-*-* } 18 } */ -/* { dg-warning {unsupported simdlen 4 \(amdgcn\)} "" { target amdgcn*-*-* } 18 } */ diff --git a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-3.c b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-3.c index fef48c50669..45f0fb6125f 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-3.c +++ b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-3.c @@ -13,6 +13,7 @@ int d[N], e[N]; #pragma omp declare simd simdlen(4) notinbranch uniform(b) linear(c:3) __attribute__((noinline)) int foo (int a, int b, int c) +/* { dg-warning {unsupported simdlen 4 \(amdgcn\)} "" { target amdgcn*-*-* } .-1 } */ { if (a < 30) return 5; @@ -43,5 +44,3 @@ main () abort (); return 0; } - -/* { dg-warning {unsupported simdlen 4 \(amdgcn\)} "" { target amdgcn*-*-* } 15 } */ diff --git a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-4.c b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-4.c index 2f9f8306d67..320ac7e6c2e 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-4.c +++ b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-4.c @@ -19,6 +19,7 @@ unsigned short f[N]; #endif __attribute__((noinline)) float foo (float a, float b, float c) +/* { dg-warning {unsupported simdlen 8 \(amdgcn\)} "" { target amdgcn*-*-* } .-1 } */ { if (a < 30) return 5.0f; @@ -50,5 +51,3 @@ main () abort (); return 0; } - -/* { dg-warning {unsupported simdlen 8 \(amdgcn\)} "" { target amdgcn*-*-* } 17 } */ diff --git a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-5.c b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-5.c index 09708189720..b927f6e7698 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-5.c +++ b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-5.c @@ -17,6 +17,7 @@ int d[N], e[N]; #endif __attribute__((noinline)) long long int foo (int a, int b, int c) +/* { dg-warning {unsupported simdlen 4 \(amdgcn\)} "" { target amdgcn*-*-* } .-1 } */ { return a + b + c; } @@ -45,5 +46,3 @@ main () abort (); return 0; } - -/* { dg-warning {unsupported simdlen 4 \(amdgcn\)} "" { target amdgcn*-*-* } 15 } */ diff --git a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-8.c b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-8.c index 29842825584..8d7448f7cb3 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-8.c +++ b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-8.c @@ -19,6 +19,7 @@ unsigned char d[N]; #endif __attribute__((noinline)) int foo (long int a, int b, int c) +/* { dg-warning {unsupported simdlen 8 \(amdgcn\)} "" { target amdgcn*-*-* } .-1 } */ { return a + b + c; } @@ -30,6 +31,7 @@ foo (long int a, int b, int c) #endif __attribute__((noinline)) long int bar (int a, int b, long int c) +/* { dg-warning {unsupported simdlen 8 \(amdgcn\)} "" { target amdgcn*-*-* } .-1 } */ { return a + b + c; } @@ -101,6 +103,3 @@ main () abort (); return 0; } - -/* { dg-warning {unsupported simdlen 8 \(amdgcn\)} "" { target amdgcn*-*-* } 17 } */ -/* { dg-warning {unsupported simdlen 8 \(amdgcn\)} "" { target amdgcn*-*-* } 24 } */ -- 2.34.1