From patchwork Tue Dec 5 15:13:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robin Dapp X-Patchwork-Id: 1872185 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20230601 header.b=fQiIMtnA; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Sl3vp2tykz1ySd for ; Wed, 6 Dec 2023 02:13:42 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 5FF63386186D for ; Tue, 5 Dec 2023 15:13:40 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-wm1-x330.google.com (mail-wm1-x330.google.com [IPv6:2a00:1450:4864:20::330]) by sourceware.org (Postfix) with ESMTPS id 5FFDF385782F for ; Tue, 5 Dec 2023 15:13:25 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 5FFDF385782F Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 5FFDF385782F Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2a00:1450:4864:20::330 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701789209; cv=none; b=tcJlTQy9RebQrz+E9JVIU66OmQNPh8R2SKENr944CqvnZfkcf0ZQplqO1mL8ATYWRj+PK1p9YoG7BZ/zl6lDdOoeuKKdlnQZ3JPiYRzZOxEgE6wEqjIxT81XY2XDHqbYRRHZTA6P0ORNt/pGnaEl+ZzjtTlHgW3vTn5/Zhq3CYg= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701789209; c=relaxed/simple; bh=omMUbYGLeonkfNjyJxEBWTPMO185WMvR35aN0FMVV30=; h=DKIM-Signature:Message-ID:Date:MIME-Version:To:From:Subject; b=MdE9vPAlQxyRRs8+kaFZO9Wdibw+AJQk7B/NMtFLjsFrVkLYe5AQWxbNbvFAn747gI5ZnWsLeivUb5s39q03RvuijmXsroXXLZ8/t1aVLng7pcel1hga9FAsSGLKIbF58SE2N5Ws54GlHDD3QKleXm962el0IUcRo+FLuBEgQBk= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-40bd5eaa66cso46802095e9.2 for ; Tue, 05 Dec 2023 07:13:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1701789204; x=1702394004; darn=gcc.gnu.org; h=content-transfer-encoding:subject:from:to:content-language:cc :user-agent:mime-version:date:message-id:from:to:cc:subject:date :message-id:reply-to; bh=GytthN2Ef7IQl5oAphpQ/M1Wmm8Q8QYyYUsq80vyysU=; b=fQiIMtnA5+QaZ2FKlYjNAqdCdm9/AjsQTllpyZTN3g1VIulMms8IILNxQEFE5uiY+S 2xR+T042R0L1oI/A+rjxq4oiol6Rmle3ukhhwTv+Gk3xvBnqaV1+MdnCmOrbQax3RaPF pxMAKL9e1xN9xnyrJZHgktBYIJOf8XMla/XKHB7kdTPcGSKLwZLbTa1YO5oSVX21Jh9M oGj8/lcUR61rwZE8/AsyZhaNjpcoFfKs6okTN5Nohe39rhY2m/Sft2/UIL75z9WY8Ddi wXO58iGTOawbJLxR35bImgwzETgWGoHaunK1v7AGPWquEJtl1zA7BhLWd7dlTf6Po/WZ pdZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701789204; x=1702394004; h=content-transfer-encoding:subject:from:to:content-language:cc :user-agent:mime-version:date:message-id:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=GytthN2Ef7IQl5oAphpQ/M1Wmm8Q8QYyYUsq80vyysU=; b=jSsyRNpexoEK+BpGgM3Lwe4raEGBfcquik9FAiV1VDAUAdGaHLl2krXBCo4z/blu98 yrNwA90GP1z4C68aOQCLipaKJlWtOJD/v3Xxih3g4CN0/sSi49aMOX37T4nBDcXu3Izq iSggvzFaFX+qAPOFhSV9LHuQ6darNBCNYBX0lDITx4D6fZ50a+Qe6/BrHNfLnMFFjl2T S1YIVlZSjgXrSHkk5zeL1j4YUnER5pUdht7JwyRQ5VoqYffcw3oGR9R7lXVVa3rYqjl/ ucMUhyZiLUnofZx4M+/wvBsk0cIuGtgYloL17X+GC78vJG4imnOYlUg7uyLLLq7Aj/d+ YD0Q== X-Gm-Message-State: AOJu0Yx8tImzv88f7W2am2QUx2W7xx6Qg+GMdj5xVcwXbx8iZLxIv2LV 12Na7OAlnhq8rbsN4JkdjjyqTH5eGNg= X-Google-Smtp-Source: AGHT+IGhbAI88Piu/3ZOOE/q6kXQFTuvKbzbyC4gTVZ0iOkwzzIweuPBhFgqVLK7KwgdQ598eAKMwA== X-Received: by 2002:a1c:7218:0:b0:40b:5e21:dd16 with SMTP id n24-20020a1c7218000000b0040b5e21dd16mr674457wmc.68.1701789203505; Tue, 05 Dec 2023 07:13:23 -0800 (PST) Received: from [192.168.1.23] (ip-149-172-150-237.um42.pools.vodafone-ip.de. [149.172.150.237]) by smtp.gmail.com with ESMTPSA id v20-20020a170906489400b009adc77fe164sm6833759ejq.66.2023.12.05.07.13.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 05 Dec 2023 07:13:23 -0800 (PST) Message-ID: <6e9a07e9-7b5b-40f7-8a7f-e2abcc37e283@gmail.com> Date: Tue, 5 Dec 2023 16:13:22 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Cc: rdapp.gcc@gmail.com Content-Language: en-US To: gcc-patches , palmer , Kito Cheng , jeffreyalaw , "juzhe.zhong@rivai.ai" From: Robin Dapp Subject: [PATCH] RISC-V: Add vec_init expander for masks [PR112854]. X-Spam-Status: No, score=-9.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Hi, PR112854 shows a problem on rv32 with zvl1024b. During the course of expand_constructor we try to overlay/subreg a 64-element mask by a scalar (Pmode) register. This works for zvle512b and its maximum of 32 elements but fails for rv32 and 64 elements. To circumvent this this patch adds a vec_init expander for vector masks by initializing a QImode vector and comparing that against 0. This also ensures we don't do element initialization of masks. Regards Robin gcc/ChangeLog: PR target/112854 * config/riscv/autovec.md (vec_initqi): New expander. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/pr112854.c: New test. --- gcc/config/riscv/autovec.md | 16 ++++++++++++++++ .../gcc.target/riscv/rvv/autovec/pr112854.c | 12 ++++++++++++ 2 files changed, 28 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112854.c diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index 3c4d68367f0..65ab76b3e0c 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -394,6 +394,22 @@ (define_expand "vec_init" } ) +;; Provide a vec_init for mask registers by initializing +;; a QImode vector and comparing it against 0. +(define_expand "vec_initqi" + [(match_operand:VB 0 "register_operand") + (match_operand 1 "")] + "TARGET_VECTOR" + { + machine_mode qimode = riscv_vector::get_vector_mode + (QImode, GET_MODE_NUNITS (mode)).require (); + rtx tmp = gen_reg_rtx (qimode); + riscv_vector::expand_vec_init (tmp, operands[1]); + riscv_vector::expand_vec_cmp (operands[0], NE, tmp, CONST0_RTX (qimode)); + DONE; + } +) + ;; Slide an RVV vector left and insert a scalar into element 0. (define_expand "vec_shl_insert_" [(match_operand:VI 0 "register_operand") diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112854.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112854.c new file mode 100644 index 00000000000..8f7f13f9dc1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112854.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl1024b -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */ + +short a, b; +void c(int d) { + for (; a; a--) { + b = 0; + for (; b <= 8; b++) + if (d) + break; + } +}