From patchwork Tue Dec 5 08:12:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fei Gao X-Patchwork-Id: 1871867 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Sktbq6bcFz1yST for ; Tue, 5 Dec 2023 19:14:14 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 83032384F987 for ; Tue, 5 Dec 2023 08:14:12 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from zg8tmtu5ljg5lje1ms4xmtka.icoremail.net (zg8tmtu5ljg5lje1ms4xmtka.icoremail.net [159.89.151.119]) by sourceware.org (Postfix) with ESMTP id 46B86385800F for ; Tue, 5 Dec 2023 08:13:49 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 46B86385800F Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=eswincomputing.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 46B86385800F Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=159.89.151.119 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701764032; cv=none; b=DYw5MIbcq/4gQV4pU5M5xohonrFasleyj36vEAt2eYUn2DvBlXfhLR/HiWiSG8QJZkQuhpWQs2m9txDFthcrub7yh4OFi72ALTXzE8Ry+KznZVFMBXV0nZED5yxzcewj5pjunlR3LylR/L9eK0sw5aqKm3ORhGq1PsXDkp8r6gQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701764032; c=relaxed/simple; bh=vllusEaEmaXfeS/dUwr9ATHBbGu3LXpCOhgm6FUaXk0=; h=From:To:Subject:Date:Message-Id; b=XiiU9AdQrRHVdqXT49kNYwwsIpjei3L/rUzD7uLPQJpYEXMz1nVIW2RFKBbV6BuxUXOfGvw/641v/4K0ngdJK4UIAyWzH3yUQSQaaZSbyrXGgiUjjISmQX+Fgdh9gWWFaYGTKGJyX1gK7gbN4GgK0zqpSy4xcEDCRw1NvZ2N6rU= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from localhost.localdomain (unknown [10.12.130.31]) by app2 (Coremail) with SMTP id TQJkCgBH1tR2225lPkgAAA--.4441S4; Tue, 05 Dec 2023 16:12:39 +0800 (CST) From: Fei Gao To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, jeffreyalaw@gmail.com, zengxiao@eswincomputing.com, Fei Gao Subject: [PATCH 1/5][V3][ifcvt] optimize x=c ? (y op z) : y by RISC-V Zicond like insns Date: Tue, 5 Dec 2023 08:12:44 +0000 Message-Id: <20231205081248.2106-1-gaofei@eswincomputing.com> X-Mailer: git-send-email 2.17.1 X-CM-TRANSID: TQJkCgBH1tR2225lPkgAAA--.4441S4 X-Coremail-Antispam: 1UD129KBjvAXoWfGFWfGF47GFWUurW8tF4xWFg_yoW8GF18Co WfZr90qF40gr13Wr1xGr4a9F1jqa1UZ3y5Cr4Yyr1Y9rWqyFyFgw4rWa1DZa48Wr4furyU Aanaqr1Sy3y3Arn8n29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UjIYCTnIWjp_UUUY87AC8VAFwI0_Gr0_Xr1l1xkIjI8I6I8E6xAIw20EY4v20xva j40_Wr0E3s1l1IIY67AEw4v_Jr0_Jr4l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0rcxSw2 x7M28EF7xvwVC0I7IYx2IY67AKxVWDJVCq3wA2z4x0Y4vE2Ix0cI8IcVCY1x0267AKxVW8 Jr0_Cr1UM28EF7xvwVC2z280aVAFwI0_GcCE3s1l84ACjcxK6I8E87Iv6xkF7I0E14v26r xl6s0DM2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj 6xIIjxv20xvE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr 0_Gr1lF7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7MxkIecxEwVCm-wCF 04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r 18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_JF0_Jw1lIxkGc2Ij64vI r41lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Jr0_Gr 1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvE x4A2jsIEc7CjxVAFwI0_Jr0_GrUvcSsGvfC2KfnxnUUI43ZEXa7VUbXdbUUUUUU== X-CM-SenderInfo: xjdrwv3l6h245lqf0zpsxwx03jof0z/ X-Spam-Status: No, score=-11.0 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, LIKELY_SPAM_BODY, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org op=[PLUS, MINUS, IOR, XOR] Conditional op, if zero rd = (rc == 0) ? (rs1 op rs2) : rs1 --> czero.nez rd, rs2, rc op rd, rs1, rd Conditional op, if non-zero rd = (rc != 0) ? (rs1 op rs2) : rs1 --> czero.eqz rd, rs2, rc op rd, rs1, rd Co-authored-by: Xiao Zeng gcc/ChangeLog: * ifcvt.cc (noce_try_cond_zero_arith):handler for condtional zero based ifcvt (noce_emit_czero): helper for noce_try_cond_zero_arith (noce_cond_zero_binary_op_supported): check supported OPs for condtional zero based ifcvt (get_base_reg): get the reg itself or NULL_RTX if not a reg (noce_bbs_ok_for_cond_zero_arith): check if BBs are OK for condtional zero based ifcvt (noce_process_if_block): add noce_try_cond_zero_arith gcc/testsuite/ChangeLog: * gcc.target/riscv/zicond_ifcvt_opt.c: New test. --- gcc/ifcvt.cc | 187 ++++++ .../gcc.target/riscv/zicond_ifcvt_opt.c | 566 ++++++++++++++++++ 2 files changed, 753 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/zicond_ifcvt_opt.c diff --git a/gcc/ifcvt.cc b/gcc/ifcvt.cc index a0af553b9ff..1f0f5414ea1 100644 --- a/gcc/ifcvt.cc +++ b/gcc/ifcvt.cc @@ -787,6 +787,7 @@ static rtx noce_get_alt_condition (struct noce_if_info *, rtx, rtx_insn **); static bool noce_try_minmax (struct noce_if_info *); static bool noce_try_abs (struct noce_if_info *); static bool noce_try_sign_mask (struct noce_if_info *); +static int noce_try_cond_zero_arith (struct noce_if_info *); /* Return the comparison code for reversed condition for IF_INFO, or UNKNOWN if reversing the condition is not possible. */ @@ -1831,6 +1832,35 @@ noce_emit_cmove (struct noce_if_info *if_info, rtx x, enum rtx_code code, return NULL_RTX; } +/* Emit a conditional zero, returning TARGET or NULL_RTX upon failure. + IF_INFO describes the if-conversion scenario under consideration. + CZERO_CODE selects the condition (EQ/NE). + NON_ZERO_OP is the nonzero operand of the conditional move + TARGET is the desired output register. */ + +static rtx +noce_emit_czero (struct noce_if_info *if_info, enum rtx_code czero_code, + rtx non_zero_op, rtx target) +{ + machine_mode mode = GET_MODE (target); + rtx cond_op0 = XEXP (if_info->cond, 0); + rtx czero_cond + = gen_rtx_fmt_ee (czero_code, GET_MODE (cond_op0), cond_op0, const0_rtx); + rtx if_then_else + = gen_rtx_IF_THEN_ELSE (mode, czero_cond, const0_rtx, non_zero_op); + rtx set = gen_rtx_SET (target, if_then_else); + + rtx_insn *insn = make_insn_raw (set); + + if (recog_memoized (insn) >= 0) + { + add_insn (insn); + return target; + } + + return NULL_RTX; +} + /* Try only simple constants and registers here. More complex cases are handled in noce_try_cmove_arith after noce_try_store_flag_arith has had a go at it. */ @@ -2880,6 +2910,160 @@ noce_try_sign_mask (struct noce_if_info *if_info) return true; } +/* Check if OP is supported by conditional zero based if conversion, + returning TRUE if satisfied otherwise FALSE. + + OP is the operation to check. */ + +static bool +noce_cond_zero_binary_op_supported (rtx op) +{ + enum rtx_code opcode = GET_CODE (op); + + if (opcode == PLUS || opcode == MINUS || opcode == IOR || opcode == XOR) + return true; + + return false; +} + +/* Helper function to return REG itself, + otherwise NULL_RTX for other RTX_CODE. */ + +static rtx +get_base_reg (rtx exp) +{ + if (REG_P (exp)) + return exp; + + return NULL_RTX; +} + +/* Check if IF-BB and THEN-BB satisfy the condition for conditional zero + based if conversion, returning TRUE if satisfied otherwise FALSE. + + IF_INFO describes the if-conversion scenario under consideration. + COMMON_PTR points to the common REG of canonicalized IF_INFO->A and + IF_INFO->B. + CZERO_CODE_PTR points to the comparison code to use in czero RTX. + A_PTR points to the A expression of canonicalized IF_INFO->A. + TO_REPLACE points to the RTX to be replaced by czero RTX destnation. */ + +static bool +noce_bbs_ok_for_cond_zero_arith (struct noce_if_info *if_info, rtx *common_ptr, + enum rtx_code *czero_code_ptr, rtx *a_ptr, + rtx **to_replace) +{ + rtx common = NULL_RTX; + rtx cond = if_info->cond; + rtx a = copy_rtx (if_info->a); + rtx b = copy_rtx (if_info->b); + rtx bin_op1 = NULL_RTX; + enum rtx_code czero_code = UNKNOWN; + bool reverse = false; + rtx op0, op1, bin_exp; + + if (!noce_simple_bbs (if_info)) + return false; + + /* COND must be EQ or NE comparision of a reg and 0. */ + if (GET_CODE (cond) != NE && GET_CODE (cond) != EQ) + return false; + if (!REG_P (XEXP (cond, 0)) || !rtx_equal_p (XEXP (cond, 1), const0_rtx)) + return false; + + /* Canonicalize x = y : (y op z) to x = (y op z) : y. */ + if (REG_P (a) && noce_cond_zero_binary_op_supported (b)) + { + std::swap (a, b); + reverse = !reverse; + } + + /* Check if x = (y op z) : y is supported by czero based ifcvt. */ + if (!(noce_cond_zero_binary_op_supported (a) && REG_P (b))) + return false; + + bin_exp = a; + + /* Canonicalize x = (z op y) : y to x = (y op z) : y */ + op1 = get_base_reg (XEXP (bin_exp, 1)); + if (op1 && rtx_equal_p (op1, b) && COMMUTATIVE_ARITH_P (bin_exp)) + std::swap (XEXP (bin_exp, 0), XEXP (bin_exp, 1)); + + op0 = get_base_reg (XEXP (bin_exp, 0)); + if (op0 && rtx_equal_p (op0, b)) + { + common = b; + bin_op1 = XEXP (bin_exp, 1); + czero_code = reverse + ? noce_reversed_cond_code (if_info) + : GET_CODE (cond); + } + else + return false; + + if (czero_code == UNKNOWN) + return false; + + if (REG_P (bin_op1)) + *to_replace = &XEXP (bin_exp, 1); + else + return false; + + *common_ptr = common; + *czero_code_ptr = czero_code; + *a_ptr = a; + + return true; +} + +/* Try to covert if-then-else with conditional zero, + returning TURE on success or FALSE on failure. + IF_INFO describes the if-conversion scenario under consideration. */ + +static int +noce_try_cond_zero_arith (struct noce_if_info *if_info) +{ + rtx target, a; + rtx_insn *seq; + machine_mode mode = GET_MODE (if_info->x); + rtx common = NULL_RTX; + enum rtx_code czero_code = UNKNOWN; + rtx non_zero_op = NULL_RTX; + rtx *to_replace = NULL; + + if (!noce_bbs_ok_for_cond_zero_arith (if_info, &common, &czero_code, &a, + &to_replace)) + return false; + + non_zero_op = *to_replace; + + start_sequence (); + + /* If x is used in both input and out like x = c ? x + z : x, + use a new reg to avoid modifying x */ + if (common && rtx_equal_p (common, if_info->x)) + target = gen_reg_rtx (mode); + else + target = if_info->x; + + target = noce_emit_czero (if_info, czero_code, non_zero_op, target); + if (!target || !to_replace) + { + end_sequence (); + return false; + } + + *to_replace = target; + noce_emit_move_insn (if_info->x, a); + + seq = end_ifcvt_sequence (if_info); + if (!seq || !targetm.noce_conversion_profitable_p (seq, if_info)) + return false; + + emit_insn_before_setloc (seq, if_info->jump, INSN_LOCATION (if_info->insn_a)); + if_info->transform_name = "noce_try_cond_zero_arith"; + return true; +} /* Optimize away "if (x & C) x |= C" and similar bit manipulation transformations. */ @@ -3975,6 +4159,9 @@ noce_process_if_block (struct noce_if_info *if_info) goto success; if (noce_try_store_flag_mask (if_info)) goto success; + if (HAVE_conditional_move + && noce_try_cond_zero_arith (if_info)) + goto success; if (HAVE_conditional_move && noce_try_cmove_arith (if_info)) goto success; diff --git a/gcc/testsuite/gcc.target/riscv/zicond_ifcvt_opt.c b/gcc/testsuite/gcc.target/riscv/zicond_ifcvt_opt.c new file mode 100644 index 00000000000..dcb21c15d1a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zicond_ifcvt_opt.c @@ -0,0 +1,566 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zbb_zicond -mabi=lp64d -O2 " } */ +/* { dg-skip-if "" { *-*-* } {"-O0" "-O1" "-Os" "-Og" "-O3" "-Oz" "-flto"} } */ + +long +test_ADD_ceqz (long x, long y, long z, long c) +{ + if (c) + x = y + z; + else + x = y; + return x; +} + +long +test_ADD_ceqz_x (long x, long z, long c) +{ + if (c) + x = x + z; + + return x; +} + +long +test_ADD_nez (long x, long y, long z, long c) +{ + if (c) + x = y; + else + x = y + z; + return x; +} + +long +test_ADD_nez_x (long x, long z, long c) +{ + if (c) + { + } + else + x = x + z; + return x; +} + +long +test_ADD_nez_2 (long x, long y, long z, long c) +{ + if (!c) + x = y + z; + else + x = y; + return x; +} + +long +test_ADD_nez_x_2 (long x, long z, long c) +{ + if (!c) + x = x + z; + + return x; +} + +long +test_ADD_eqz_2 (long x, long y, long z, long c) +{ + if (!c) + x = y; + else + x = y + z; + return x; +} + +long +test_ADD_eqz_x_2 (long x, long z, long c) +{ + if (!c) + { + } + else + x = x + z; + return x; +} + +long +test_SUB_ceqz (long x, long y, long z, long c) +{ + if (c) + x = y - z; + else + x = y; + return x; +} + +long +test_SUB_ceqz_x (long x, long z, long c) +{ + if (c) + x = x - z; + + return x; +} + +long +test_SUB_nez (long x, long y, long z, long c) +{ + if (c) + x = y; + else + x = y - z; + return x; +} + +long +test_SUB_nez_x (long x, long z, long c) +{ + if (c) + { + } + else + x = x - z; + return x; +} + +long +test_SUB_nez_2 (long x, long y, long z, long c) +{ + if (!c) + x = y - z; + else + x = y; + return x; +} + +long +test_SUB_nez_x_2 (long x, long z, long c) +{ + if (!c) + x = x - z; + + return x; +} + +long +test_SUB_eqz_2 (long x, long y, long z, long c) +{ + if (!c) + x = y; + else + x = y - z; + return x; +} + +long +test_SUB_eqz_x_2 (long x, long z, long c) +{ + if (!c) + { + } + else + x = x - z; + return x; +} + +long +test_IOR_ceqz (long x, long y, long z, long c) +{ + if (c) + x = y | z; + else + x = y; + return x; +} + +long +test_IOR_ceqz_x (long x, long z, long c) +{ + if (c) + x = x | z; + + return x; +} + +long +test_IOR_nez (long x, long y, long z, long c) +{ + if (c) + x = y; + else + x = y | z; + return x; +} + +long +test_IOR_nez_x (long x, long z, long c) +{ + if (c) + { + } + else + x = x | z; + return x; +} + +long +test_IOR_nez_2 (long x, long y, long z, long c) +{ + if (!c) + x = y | z; + else + x = y; + return x; +} + +long +test_IOR_nez_x_2 (long x, long z, long c) +{ + if (!c) + x = x | z; + + return x; +} + +long +test_IOR_eqz_2 (long x, long y, long z, long c) +{ + if (!c) + x = y; + else + x = y | z; + return x; +} + +long +test_IOR_eqz_x_2 (long x, long z, long c) +{ + if (!c) + { + } + else + x = x | z; + return x; +} + +long +test_XOR_ceqz (long x, long y, long z, long c) +{ + if (c) + x = y ^ z; + else + x = y; + return x; +} + +long +test_XOR_ceqz_x (long x, long z, long c) +{ + if (c) + x = x ^ z; + + return x; +} + +long +test_XOR_nez (long x, long y, long z, long c) +{ + if (c) + x = y; + else + x = y ^ z; + return x; +} + +long +test_XOR_nez_x (long x, long z, long c) +{ + if (c) + { + } + else + x = x ^ z; + return x; +} + +long +test_XOR_nez_2 (long x, long y, long z, long c) +{ + if (!c) + x = y ^ z; + else + x = y; + return x; +} + +long +test_XOR_nez_x_2 (long x, long z, long c) +{ + if (!c) + x = x ^ z; + + return x; +} + +long +test_XOR_eqz_2 (long x, long y, long z, long c) +{ + if (!c) + x = y; + else + x = y ^ z; + return x; +} + +long +test_XOR_eqz_x_2 (long x, long z, long c) +{ + if (!c) + { + } + else + x = x ^ z; + return x; +} + +long +test_ADD_ceqz_reverse_bin_oprands (long x, long y, long z, long c) +{ + if (c) + x = z + y; + else + x = y; + return x; +} + +long +test_ADD_ceqz_x_reverse_bin_oprands (long x, long z, long c) +{ + if (c) + x = z + x; + + return x; +} + +long +test_ADD_nez_reverse_bin_oprands (long x, long y, long z, long c) +{ + if (c) + x = y; + else + x = z + y; + return x; +} + +long +test_ADD_nez_x_reverse_bin_oprands (long x, long z, long c) +{ + if (c) + { + } + else + x = z + x; + return x; +} + +long +test_ADD_nez_2_reverse_bin_oprands (long x, long y, long z, long c) +{ + if (!c) + x = z + y; + else + x = y; + return x; +} + +long +test_ADD_nez_x_2_reverse_bin_oprands (long x, long z, long c) +{ + if (!c) + x = z + x; + + return x; +} + +long +test_ADD_eqz_2_reverse_bin_oprands (long x, long y, long z, long c) +{ + if (!c) + x = y; + else + x = z + y; + return x; +} + +long +test_ADD_eqz_x_2_reverse_bin_oprands (long x, long z, long c) +{ + if (!c) + { + } + else + x = z + x; + return x; +} + +long +test_IOR_ceqz_reverse_bin_oprands (long x, long y, long z, long c) +{ + if (c) + x = z | y; + else + x = y; + return x; +} + +long +test_IOR_ceqz_x_reverse_bin_oprands (long x, long z, long c) +{ + if (c) + x = z | x; + + return x; +} + +long +test_IOR_nez_reverse_bin_oprands (long x, long y, long z, long c) +{ + if (c) + x = y; + else + x = z | y; + return x; +} + +long +test_IOR_nez_x_reverse_bin_oprands (long x, long z, long c) +{ + if (c) + { + } + else + x = z | x; + return x; +} + +long +test_IOR_nez_2_reverse_bin_oprands (long x, long y, long z, long c) +{ + if (!c) + x = z | y; + else + x = y; + return x; +} + +long +test_IOR_nez_x_2_reverse_bin_oprands (long x, long z, long c) +{ + if (!c) + x = z | x; + + return x; +} + +long +test_IOR_eqz_2_reverse_bin_oprands (long x, long y, long z, long c) +{ + if (!c) + x = y; + else + x = z | y; + return x; +} + +long +test_IOR_eqz_x_2_reverse_bin_oprands (long x, long z, long c) +{ + if (!c) + { + } + else + x = z | x; + return x; +} + +long +test_XOR_ceqz_reverse_bin_oprands (long x, long y, long z, long c) +{ + if (c) + x = z ^ y; + else + x = y; + return x; +} + +long +test_XOR_ceqz_x_reverse_bin_oprands (long x, long z, long c) +{ + if (c) + x = z ^ x; + + return x; +} + +long +test_XOR_nez_reverse_bin_oprands (long x, long y, long z, long c) +{ + if (c) + x = y; + else + x = z ^ y; + return x; +} + +long +test_XOR_nez_x_reverse_bin_oprands (long x, long z, long c) +{ + if (c) + { + } + else + x = z ^ x; + return x; +} + +long +test_XOR_nez_2_reverse_bin_oprands (long x, long y, long z, long c) +{ + if (!c) + x = z ^ y; + else + x = y; + return x; +} + +long +test_XOR_nez_x_2_reverse_bin_oprands (long x, long z, long c) +{ + if (!c) + x = z ^ x; + + return x; +} + +long +test_XOR_eqz_2_reverse_bin_oprands (long x, long y, long z, long c) +{ + if (!c) + x = y; + else + x = z ^ y; + return x; +} + +long +test_XOR_eqz_x_2_reverse_bin_oprands (long x, long z, long c) +{ + if (!c) + { + } + else + x = z ^ x; + return x; +} + +/* { dg-final { scan-assembler-times {czero\.eqz} 28 } } */ +/* { dg-final { scan-assembler-times {czero\.nez} 28 } } */ From patchwork Tue Dec 5 08:12:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fei Gao X-Patchwork-Id: 1871868 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Sktbs1G3lz1yST for ; Tue, 5 Dec 2023 19:14:15 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 436DE385782B for ; Tue, 5 Dec 2023 08:14:13 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from zg8tmty3ljk5ljewns4xndka.icoremail.net (zg8tmty3ljk5ljewns4xndka.icoremail.net [167.99.105.149]) by sourceware.org (Postfix) with ESMTP id D0B6C3858D33 for ; Tue, 5 Dec 2023 08:13:48 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D0B6C3858D33 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=eswincomputing.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org D0B6C3858D33 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=167.99.105.149 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701764031; cv=none; b=EzYOjvQ+xso/eIR9C9b8MoZ/fXld00GMkZWE730HrSgFbDDyDCl0FaCxB4apxfUGGJcSA/eddPKycbCkewkRfTjscohr5J5xeeoSRiAtVztJtYFCmozmgPEs3xkjQKqlmiJbYf6c+sNW9TsZfFCG/NL4sjj6kdg0KZ7SxL2vwDI= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701764031; c=relaxed/simple; bh=d9X5T9cc0nq3xNUvIA2LURVsfyLRWQGmyC+28dKSSqI=; h=From:To:Subject:Date:Message-Id; b=UI6n8GHcArIiMRuJ8bD5FR6vyzW1dEarHaPP2cAXMgAGdQGi7JA7yzgMHChT27FNantdvG7ONjWpYZsHVRsexABVqs1YxSAGRV8kFa6qsxFAaHyFqsUqOCFYEglJP189+g1fv+exoxYzGeaLH89Cp+mouSrmlFj4iRhAJRAdYt4= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from localhost.localdomain (unknown [10.12.130.31]) by app2 (Coremail) with SMTP id TQJkCgBH1tR2225lPkgAAA--.4441S5; Tue, 05 Dec 2023 16:12:40 +0800 (CST) From: Fei Gao To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, jeffreyalaw@gmail.com, zengxiao@eswincomputing.com, Fei Gao Subject: [PATCH 2/5] [ifcvt] optimize x=c ? (y shift_op z):y by RISC-V Zicond like insns Date: Tue, 5 Dec 2023 08:12:45 +0000 Message-Id: <20231205081248.2106-2-gaofei@eswincomputing.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231205081248.2106-1-gaofei@eswincomputing.com> References: <20231205081248.2106-1-gaofei@eswincomputing.com> X-CM-TRANSID: TQJkCgBH1tR2225lPkgAAA--.4441S5 X-Coremail-Antispam: 1UD129KBjvJXoWxWw4UuryDur4rCr45XFy8Grg_yoW5CryUpa 13G39Fqrs5GFyfKF4xWFy3Xr15Cr43t347K3s7trW0ywnxXFWYqr17twnrtr13JFZYqFy3 Aa9xCFZI9wsrJa7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUB214x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jr4l82xGYIkIc2 x26xkF7I0E14v26r1I6r4UM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_tr0E3s1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F4UJw A2z4x0Y4vEx4A2jsIE14v26rxl6s0DM28EF7xvwVC2z280aVCY1x0267AKxVW0oVCq3wAS 0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2 IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0 Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwCY02Avz4vE-syl42xK82IYc2 Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s02 6x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r126r1DMIIYrxkI7VAKI48JMIIF0x vE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4j6F4UMIIF0xvE 42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6x kF7I0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjfU5iSlUUUUU X-CM-SenderInfo: xjdrwv3l6h245lqf0zpsxwx03jof0z/ X-Spam-Status: No, score=-11.8 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org op=[ASHIFT, ASHIFTRT, LSHIFTRT, ROTATE, ROTATERT] Conditional op, if zero rd = (rc == 0) ? (rs1 op rs2) : rs1 --> czero.nez rd, rs2, rc op rd, rs1, rd Conditional op, if non-zero rd = (rc != 0) ? (rs1 op rs2) : rs1 --> czero.eqz rd, rs2, rc op rd, rs1, rd Co-authored-by: Xiao Zeng gcc/ChangeLog: * ifcvt.cc (noce_cond_zero_binary_op_supported): add support for shift like op. (get_base_reg): add support for subreg to handle shift amount operand. (noce_bbs_ok_for_cond_zero_arith): to replace shift amount operand. gcc/testsuite/ChangeLog: * gcc.target/riscv/zicond_ifcvt_opt.c: add TCs for shift like op. --- gcc/ifcvt.cc | 8 ++- .../gcc.target/riscv/zicond_ifcvt_opt.c | 55 ++++++++++++++++++- 2 files changed, 61 insertions(+), 2 deletions(-) diff --git a/gcc/ifcvt.cc b/gcc/ifcvt.cc index 1f0f5414ea1..2efae21ebfe 100644 --- a/gcc/ifcvt.cc +++ b/gcc/ifcvt.cc @@ -2920,7 +2920,9 @@ noce_cond_zero_binary_op_supported (rtx op) { enum rtx_code opcode = GET_CODE (op); - if (opcode == PLUS || opcode == MINUS || opcode == IOR || opcode == XOR) + if (opcode == PLUS || opcode == MINUS || opcode == IOR || opcode == XOR + || opcode == ASHIFT || opcode == ASHIFTRT || opcode == LSHIFTRT + || opcode == ROTATE || opcode == ROTATERT) return true; return false; @@ -2934,6 +2936,8 @@ get_base_reg (rtx exp) { if (REG_P (exp)) return exp; + else if (SUBREG_P (exp)) + return SUBREG_REG (exp); return NULL_RTX; } @@ -3006,6 +3010,8 @@ noce_bbs_ok_for_cond_zero_arith (struct noce_if_info *if_info, rtx *common_ptr, if (REG_P (bin_op1)) *to_replace = &XEXP (bin_exp, 1); + else if (SUBREG_P (bin_op1)) + *to_replace = &SUBREG_REG (XEXP (bin_exp, 1)); else return false; diff --git a/gcc/testsuite/gcc.target/riscv/zicond_ifcvt_opt.c b/gcc/testsuite/gcc.target/riscv/zicond_ifcvt_opt.c index dcb21c15d1a..ab5a4909b61 100644 --- a/gcc/testsuite/gcc.target/riscv/zicond_ifcvt_opt.c +++ b/gcc/testsuite/gcc.target/riscv/zicond_ifcvt_opt.c @@ -562,5 +562,58 @@ test_XOR_eqz_x_2_reverse_bin_oprands (long x, long z, long c) return x; } -/* { dg-final { scan-assembler-times {czero\.eqz} 28 } } */ +long +test_ShiftLeft_eqz (long x, long y, long z, long c) +{ + if (c) + x = y << z; + else + x = y; + return x; +} + +long +test_ShiftR_eqz (long x, long y, long z, long c) +{ + if (c) + x = y >> z; + else + x = y; + return x; +} + +unsigned long +test_ShiftR_logical_eqz (unsigned long x, unsigned long y, unsigned long z, + unsigned long c) +{ + if (c) + x = y >> z; + else + x = y; + return x; +} + +unsigned long +test_RotateL_eqz (unsigned long x, unsigned long y, unsigned long z, + unsigned long c) +{ + if (c) + x = (y << z) | (y >> (64 - z)); + else + x = y; + return x; +} + +unsigned long +test_RotateR_eqz (unsigned long x, unsigned long y, unsigned long z, + unsigned long c) +{ + if (c) + x = (y >> z) | (y << (64 - z)); + else + x = y; + return x; +} + +/* { dg-final { scan-assembler-times {czero\.eqz} 33 } } */ /* { dg-final { scan-assembler-times {czero\.nez} 28 } } */ From patchwork Tue Dec 5 08:12:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fei Gao X-Patchwork-Id: 1871869 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Sktbz30XGz1yST for ; Tue, 5 Dec 2023 19:14:23 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 6B86B384F02F for ; Tue, 5 Dec 2023 08:14:21 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from azure-sdnproxy.icoremail.net (azure-sdnproxy.icoremail.net [52.237.72.81]) by sourceware.org (Postfix) with ESMTP id 8D68A3858D39 for ; Tue, 5 Dec 2023 08:13:52 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 8D68A3858D39 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=eswincomputing.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 8D68A3858D39 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=52.237.72.81 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701764035; cv=none; b=SQkHrKioGCKWz/aAJl2yIiWZ5nWjl2iQ+mrWEtXLlb2fRM1iDQydmyRkmuIzVOAGa8qdcBQzpyx5ylxIDdfpr5UC3l6rJElPpRm8Vse9XiXqBMOaSjXSp7tjyJLLz+fV9Sjv/E76tumkN38HLQUnWfh/DLVb7j/f1XwchCiBe84= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701764035; c=relaxed/simple; bh=kfOG83ud3Zs+/jFZtUozhCJeD+5pZvBc3ZBbBPjWFNM=; h=From:To:Subject:Date:Message-Id; b=GSvW9/Pqs+aX1iuJpakg/YyeOBssImMKSMAfiUpwIcRF64ZtjRhy0cLHz+ZzI1pZt3sfVmFJMQObxcNqeNgaKcHwkW88Cjp7kyHMUYx70Hg0RTgsQaVwKLNrJRdgAZjqpOmF8XVn2720wFckZr08w+KVV4PceprYtdgK5KpHVYk= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from localhost.localdomain (unknown [10.12.130.31]) by app2 (Coremail) with SMTP id TQJkCgBH1tR2225lPkgAAA--.4441S6; Tue, 05 Dec 2023 16:12:41 +0800 (CST) From: Fei Gao To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, jeffreyalaw@gmail.com, zengxiao@eswincomputing.com, Fei Gao Subject: [PATCH 3/5] [ifcvt] optimize x=c ? (y AND z) : y by RISC-V Zicond like insns Date: Tue, 5 Dec 2023 08:12:46 +0000 Message-Id: <20231205081248.2106-3-gaofei@eswincomputing.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231205081248.2106-1-gaofei@eswincomputing.com> References: <20231205081248.2106-1-gaofei@eswincomputing.com> X-CM-TRANSID: TQJkCgBH1tR2225lPkgAAA--.4441S6 X-Coremail-Antispam: 1UD129KBjvJXoWxKr15XF47Wr1kuw1kAFWDArb_yoWxAF1UpF W3G345Krs3JFyrGF48XFy3JFnI9w1Ygw1UGrn7trWfCwnxZrZYkr18tw12kr13JF4rXF17 CayDAFZFgF17Ja7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUB214x267AKxVW5JVWrJwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jryl82xGYIkIc2 x26xkF7I0E14v26r4j6ryUM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_tr0E3s1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F4UJw A2z4x0Y4vEx4A2jsIE14v26rxl6s0DM28EF7xvwVC2z280aVCY1x0267AKxVW0oVCq3wAS 0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2 IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0 Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwCY02Avz4vE-syl42xK82IYc2 Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s02 6x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r126r1DMIIYrxkI7VAKI48JMIIF0x vE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4j6F4UMIIF0xvE 42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6x kF7I0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjfU873vUUUUU X-CM-SenderInfo: xjdrwv3l6h245lqf0zpsxwx03jof0z/ X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Take the following case for example. CFLAGS: -march=rv64gc_zbb_zicond -mabi=lp64d -O2 long test_AND_ceqz (long x, long y, long z, long c) { if (c) x = y & z; else x = y; return x; } Before patch: and a2,a1,a2 czero.eqz a0,a2,a3 czero.nez a3,a1,a3 or a0,a3,a0 ret After patch: and a0,a1,a2 czero.nez a1,a1,a3 or a0,a1,a0 ret Co-authored-by: Xiao Zeng gcc/ChangeLog: * ifcvt.cc (noce_cond_zero_binary_op_supported): Add support for AND. (noce_bbs_ok_for_cond_zero_arith): Likewise. (noce_try_cond_zero_arith): Likewise. gcc/testsuite/ChangeLog: * gcc.target/riscv/zicond_ifcvt_opt.c: add TCs for AND. --- gcc/ifcvt.cc | 69 ++++++-- .../gcc.target/riscv/zicond_ifcvt_opt.c | 163 +++++++++++++++++- 2 files changed, 211 insertions(+), 21 deletions(-) diff --git a/gcc/ifcvt.cc b/gcc/ifcvt.cc index 2efae21ebfe..29f33f956eb 100644 --- a/gcc/ifcvt.cc +++ b/gcc/ifcvt.cc @@ -2922,7 +2922,7 @@ noce_cond_zero_binary_op_supported (rtx op) if (opcode == PLUS || opcode == MINUS || opcode == IOR || opcode == XOR || opcode == ASHIFT || opcode == ASHIFTRT || opcode == LSHIFTRT - || opcode == ROTATE || opcode == ROTATERT) + || opcode == ROTATE || opcode == ROTATERT || opcode == AND) return true; return false; @@ -2954,6 +2954,7 @@ get_base_reg (rtx exp) static bool noce_bbs_ok_for_cond_zero_arith (struct noce_if_info *if_info, rtx *common_ptr, + rtx *bin_exp_ptr, enum rtx_code *czero_code_ptr, rtx *a_ptr, rtx **to_replace) { @@ -2998,7 +2999,7 @@ noce_bbs_ok_for_cond_zero_arith (struct noce_if_info *if_info, rtx *common_ptr, { common = b; bin_op1 = XEXP (bin_exp, 1); - czero_code = reverse + czero_code = (reverse ^ (GET_CODE (bin_exp) == AND)) ? noce_reversed_cond_code (if_info) : GET_CODE (cond); } @@ -3016,6 +3017,7 @@ noce_bbs_ok_for_cond_zero_arith (struct noce_if_info *if_info, rtx *common_ptr, return false; *common_ptr = common; + *bin_exp_ptr = bin_exp; *czero_code_ptr = czero_code; *a_ptr = a; @@ -3029,38 +3031,67 @@ noce_bbs_ok_for_cond_zero_arith (struct noce_if_info *if_info, rtx *common_ptr, static int noce_try_cond_zero_arith (struct noce_if_info *if_info) { - rtx target, a; + rtx target, rtmp, a; rtx_insn *seq; machine_mode mode = GET_MODE (if_info->x); rtx common = NULL_RTX; enum rtx_code czero_code = UNKNOWN; + rtx bin_exp = NULL_RTX; + enum rtx_code bin_code = UNKNOWN; rtx non_zero_op = NULL_RTX; rtx *to_replace = NULL; - if (!noce_bbs_ok_for_cond_zero_arith (if_info, &common, &czero_code, &a, - &to_replace)) + if (!noce_bbs_ok_for_cond_zero_arith (if_info, &common, &bin_exp, &czero_code, + &a, &to_replace)) return false; - non_zero_op = *to_replace; - start_sequence (); - /* If x is used in both input and out like x = c ? x + z : x, - use a new reg to avoid modifying x */ - if (common && rtx_equal_p (common, if_info->x)) - target = gen_reg_rtx (mode); - else - target = if_info->x; + bin_code = GET_CODE (bin_exp); - target = noce_emit_czero (if_info, czero_code, non_zero_op, target); - if (!target || !to_replace) + if (bin_code == AND) { - end_sequence (); - return false; + rtmp = gen_reg_rtx (mode); + noce_emit_move_insn (rtmp, a); + + target = noce_emit_czero (if_info, czero_code, common, if_info->x); + if (!target) + { + end_sequence (); + return false; + } + + target = expand_simple_binop (mode, IOR, rtmp, target, if_info->x, 0, + OPTAB_WIDEN); + if (!target) + { + end_sequence (); + return false; + } + + if (target != if_info->x) + noce_emit_move_insn (if_info->x, target); } + else + { + non_zero_op = *to_replace; + /* If x is used in both input and out like x = c ? x + z : x, + use a new reg to avoid modifying x */ + if (common && rtx_equal_p (common, if_info->x)) + target = gen_reg_rtx (mode); + else + target = if_info->x; - *to_replace = target; - noce_emit_move_insn (if_info->x, a); + target = noce_emit_czero (if_info, czero_code, non_zero_op, target); + if (!target || !to_replace) + { + end_sequence (); + return false; + } + + *to_replace = target; + noce_emit_move_insn (if_info->x, a); + } seq = end_ifcvt_sequence (if_info); if (!seq || !targetm.noce_conversion_profitable_p (seq, if_info)) diff --git a/gcc/testsuite/gcc.target/riscv/zicond_ifcvt_opt.c b/gcc/testsuite/gcc.target/riscv/zicond_ifcvt_opt.c index ab5a4909b61..d5310690539 100644 --- a/gcc/testsuite/gcc.target/riscv/zicond_ifcvt_opt.c +++ b/gcc/testsuite/gcc.target/riscv/zicond_ifcvt_opt.c @@ -615,5 +615,164 @@ test_RotateR_eqz (unsigned long x, unsigned long y, unsigned long z, return x; } -/* { dg-final { scan-assembler-times {czero\.eqz} 33 } } */ -/* { dg-final { scan-assembler-times {czero\.nez} 28 } } */ +long +test_AND_ceqz (long x, long y, long z, long c) +{ + if (c) + x = y & z; + else + x = y; + return x; +} + +long +test_AND_ceqz_x (long x, long z, long c) +{ + if (c) + x = x & z; + + return x; +} + +long +test_AND_nez (long x, long y, long z, long c) +{ + if (c) + x = y; + else + x = y & z; + return x; +} + +long +test_AND_nez_x (long x, long z, long c) +{ + if (c) + { + } + else + x = x & z; + return x; +} + +long +test_AND_nez_2 (long x, long y, long z, long c) +{ + if (!c) + x = y & z; + else + x = y; + return x; +} + +long +test_AND_nez_x_2 (long x, long z, long c) +{ + if (!c) + x = x & z; + + return x; +} + +long +test_AND_eqz_2 (long x, long y, long z, long c) +{ + if (!c) + x = y; + else + x = y & z; + return x; +} + +long +test_AND_eqz_x_2 (long x, long z, long c) +{ + if (!c) + { + } + else + x = x & z; + return x; +} + +long +test_AND_ceqz_reverse_bin_oprands (long x, long y, long z, long c) +{ + if (c) + x = z & y; + else + x = y; + return x; +} + +long +test_AND_ceqz_x_reverse_bin_oprands (long x, long z, long c) +{ + if (c) + x = z & x; + + return x; +} + +long +test_AND_nez_reverse_bin_oprands (long x, long y, long z, long c) +{ + if (c) + x = y; + else + x = z & y; + return x; +} + +long +test_AND_nez_x_reverse_bin_oprands (long x, long z, long c) +{ + if (c) + { + } + else + x = z & x; + return x; +} + +long +test_AND_nez_2_reverse_bin_oprands (long x, long y, long z, long c) +{ + if (!c) + x = z & y; + else + x = y; + return x; +} + +long +test_AND_nez_x_2_reverse_bin_oprands (long x, long z, long c) +{ + if (!c) + x = z & x; + + return x; +} + +long +test_AND_eqz_2_reverse_bin_oprands (long x, long y, long z, long c) +{ + if (!c) + x = y; + else + x = z & y; + return x; +} + +long +test_AND_eqz_x_2_reverse_bin_oprands (long x, long z, long c) +{ + if (!c) + { + } + else + x = z & x; + return x; +} +/* { dg-final { scan-assembler-times {czero\.eqz} 41 } } */ +/* { dg-final { scan-assembler-times {czero\.nez} 36 } } */ From patchwork Tue Dec 5 08:12:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fei Gao X-Patchwork-Id: 1871870 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SktcM5FDfz1yST for ; Tue, 5 Dec 2023 19:14:43 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A691E3864825 for ; Tue, 5 Dec 2023 08:14:41 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from zg8tmtyylji0my4xnjqumte4.icoremail.net (zg8tmtyylji0my4xnjqumte4.icoremail.net [162.243.164.118]) by sourceware.org (Postfix) with ESMTP id 5A5A638582B6 for ; Tue, 5 Dec 2023 08:13:53 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 5A5A638582B6 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=eswincomputing.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 5A5A638582B6 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=162.243.164.118 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701764035; cv=none; b=HQGjdUQQAC4rE47kYLeoHeHBvETApJROfAIO0kAmnFharz9rAsfanls/i7h6f79a0HmrZnu7eBItAqoZkOIy+Rjh5V+R+wHOhImRT6xo6WcSJDrgVCooxUkdaULSV9zJLx3wLviJcgVDfoi0Xlx4TcSrhyJVQGpNA2kzpdijh9M= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701764035; c=relaxed/simple; bh=0RcTitae9Xipz93GD5vhTkDK0/yTGlBDcgmkjZT6qC4=; h=From:To:Subject:Date:Message-Id; b=k+RYH+DWdLNDyCARMtPpSAf+ADTMKyM+JrRRgVgriTGt7CgrLef8/k/topQX6RAal0QE/jfyMfzSLEDWGvTbFZVK1FtpqW1cfLd0KZUN5xVxpgFEth1Z02Q7JJ1vI/s0fJnpv3Gem1+rxv1Nt+em/GCBYb3bAYmhrphjZRZAuVo= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from localhost.localdomain (unknown [10.12.130.31]) by app2 (Coremail) with SMTP id TQJkCgBH1tR2225lPkgAAA--.4441S7; Tue, 05 Dec 2023 16:12:44 +0800 (CST) From: Fei Gao To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, jeffreyalaw@gmail.com, zengxiao@eswincomputing.com, Fei Gao Subject: [PATCH 4/5] [ifcvt] optimize x=c ? (y op const_int) : y by RISC-V Zicond like insns Date: Tue, 5 Dec 2023 08:12:47 +0000 Message-Id: <20231205081248.2106-4-gaofei@eswincomputing.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231205081248.2106-1-gaofei@eswincomputing.com> References: <20231205081248.2106-1-gaofei@eswincomputing.com> X-CM-TRANSID: TQJkCgBH1tR2225lPkgAAA--.4441S7 X-Coremail-Antispam: 1UD129KBjvAXoWfGFW8JFyUKr13XrWfAF45trb_yoW8JrWkGo WfZr98tF409r13Wr18Gr45Ar1qqF4rZ34DKa4Y9r15ZrWvyr1Sgw48W3WDta4YkFWI9ry7 C3Zaqw1xK3y5Arsxn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UjIYCTnIWjp_UUUYA7AC8VAFwI0_Wr0E3s1l1xkIjI8I6I8E6xAIw20EY4v20xva j40_Wr0E3s1l1IIY67AEw4v_Jr0_Jr4l82xGYIkIc2x26280x7IE14v26r1rM28IrcIa0x kI8VCY1x0267AKxVW8JVW5JwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK021l84AC jcxK6xIIjxv20xvE14v26w1j6s0DM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4UJVWxJr 1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_GcCE3s1l e2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI 8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8JwAC jcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lc2xSY4AK6svPMxAIw28Icx kI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2Iq xVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAVWUtwCIc40Y0x0EwIxGrwCI42 IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwCI42IY 6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aV CY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7VUjw0eJUUUUU== X-CM-SenderInfo: xjdrwv3l6h245lqf0zpsxwx03jof0z/ X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org op=[PLUS, MINUS, IOR, XOR, ASHIFT, ASHIFTRT, LSHIFTRT, ROTATE, ROTATERT, AND] Co-authored-by: Xiao Zeng gcc/ChangeLog: * ifcvt.cc (noce_cond_zero_shift_op_supported): check if OP is shift like operation (noce_cond_zero_binary_op_supported): restructure & call noce_cond_zero_shift_op_supported (noce_bbs_ok_for_cond_zero_arith): add support for const_int (noce_try_cond_zero_arith): add support for x=c ? (y op const_int) gcc/testsuite/ChangeLog: * gcc.target/riscv/zicond_ifcvt_opt.c: add TCs for x=c ? (y op const_int) : y --- gcc/ifcvt.cc | 45 +- .../gcc.target/riscv/zicond_ifcvt_opt.c | 774 +++++++++++++++++- 2 files changed, 811 insertions(+), 8 deletions(-) diff --git a/gcc/ifcvt.cc b/gcc/ifcvt.cc index 29f33f956eb..b84be53ec5c 100644 --- a/gcc/ifcvt.cc +++ b/gcc/ifcvt.cc @@ -2910,6 +2910,20 @@ noce_try_sign_mask (struct noce_if_info *if_info) return true; } +/* Check if OP is shift-like operation supported by conditional zero + based if conversion, returning TRUE if satisfied otherwise FALSE. + + OP is the operation to check. */ +static bool +noce_cond_zero_shift_op_supported (enum rtx_code op) +{ + if (op == ASHIFT || op == ASHIFTRT || op == LSHIFTRT || op == ROTATE + || op == ROTATERT) + return true; + + return false; +} + /* Check if OP is supported by conditional zero based if conversion, returning TRUE if satisfied otherwise FALSE. @@ -2921,8 +2935,7 @@ noce_cond_zero_binary_op_supported (rtx op) enum rtx_code opcode = GET_CODE (op); if (opcode == PLUS || opcode == MINUS || opcode == IOR || opcode == XOR - || opcode == ASHIFT || opcode == ASHIFTRT || opcode == LSHIFTRT - || opcode == ROTATE || opcode == ROTATERT || opcode == AND) + || opcode == AND || noce_cond_zero_shift_op_supported (opcode)) return true; return false; @@ -3009,7 +3022,7 @@ noce_bbs_ok_for_cond_zero_arith (struct noce_if_info *if_info, rtx *common_ptr, if (czero_code == UNKNOWN) return false; - if (REG_P (bin_op1)) + if (CONST_INT_P (bin_op1) || REG_P (bin_op1)) *to_replace = &XEXP (bin_exp, 1); else if (SUBREG_P (bin_op1)) *to_replace = &SUBREG_REG (XEXP (bin_exp, 1)); @@ -3038,6 +3051,7 @@ noce_try_cond_zero_arith (struct noce_if_info *if_info) enum rtx_code czero_code = UNKNOWN; rtx bin_exp = NULL_RTX; enum rtx_code bin_code = UNKNOWN; + rtx bin_op0 = NULL_RTX; rtx non_zero_op = NULL_RTX; rtx *to_replace = NULL; @@ -3048,6 +3062,7 @@ noce_try_cond_zero_arith (struct noce_if_info *if_info) start_sequence (); bin_code = GET_CODE (bin_exp); + bin_op0 = XEXP (bin_exp, 0); if (bin_code == AND) { @@ -3074,9 +3089,16 @@ noce_try_cond_zero_arith (struct noce_if_info *if_info) } else { - non_zero_op = *to_replace; + if (CONST_INT_P (*to_replace)) + { + non_zero_op = gen_reg_rtx (mode); + noce_emit_move_insn (non_zero_op, *to_replace); + } + else + non_zero_op = *to_replace; + /* If x is used in both input and out like x = c ? x + z : x, - use a new reg to avoid modifying x */ + use a new reg to avoid modifying x */ if (common && rtx_equal_p (common, if_info->x)) target = gen_reg_rtx (mode); else @@ -3089,7 +3111,18 @@ noce_try_cond_zero_arith (struct noce_if_info *if_info) return false; } - *to_replace = target; + if (CONST_INT_P (*to_replace)) + { + if (noce_cond_zero_shift_op_supported (bin_code)) + *to_replace = gen_rtx_SUBREG (E_QImode, target, 0); + else if (SUBREG_P (bin_op0)) + *to_replace = gen_rtx_SUBREG (GET_MODE (bin_op0), target, 0); + else + *to_replace = target; + } + else + *to_replace = target; + noce_emit_move_insn (if_info->x, a); } diff --git a/gcc/testsuite/gcc.target/riscv/zicond_ifcvt_opt.c b/gcc/testsuite/gcc.target/riscv/zicond_ifcvt_opt.c index d5310690539..85743e1734c 100644 --- a/gcc/testsuite/gcc.target/riscv/zicond_ifcvt_opt.c +++ b/gcc/testsuite/gcc.target/riscv/zicond_ifcvt_opt.c @@ -615,6 +615,616 @@ test_RotateR_eqz (unsigned long x, unsigned long y, unsigned long z, return x; } +long +test_ADD_ceqz_imm (long x, long y, long c) +{ + if (c) + x = y + 11; + else + x = y; + return x; +} + +long +test_ADD_ceqz_x_imm (long x, long c) +{ + if (c) + x = x + 11; + + return x; +} + +long +test_ADD_nez_imm (long x, long y, long c) +{ + if (c) + x = y; + else + x = y + 11; + return x; +} + +long +test_ADD_nez_x_imm (long x, long c) +{ + if (c) + { + } + else + x = x + 11; + return x; +} + +long +test_ADD_nez_2_imm (long x, long y, long c) +{ + if (!c) + x = y + 11; + else + x = y; + return x; +} + +long +test_ADD_nez_x_2_imm (long x, long c) +{ + if (!c) + x = x + 11; + + return x; +} + +long +test_ADD_eqz_2_imm (long x, long y, long c) +{ + if (!c) + x = y; + else + x = y + 11; + return x; +} + +long +test_ADD_eqz_x_2_imm (long x, long c) +{ + if (!c) + { + } + else + x = x + 11; + return x; +} + +long +test_SUB_ceqz_imm (long x, long y, long c) +{ + if (c) + x = y - 11; + else + x = y; + return x; +} + +long +test_SUB_ceqz_x_imm (long x, long c) +{ + if (c) + x = x - 11; + + return x; +} + +long +test_SUB_nez_imm (long x, long y, long c) +{ + if (c) + x = y; + else + x = y - 11; + return x; +} + +long +test_SUB_nez_x_imm (long x, long c) +{ + if (c) + { + } + else + x = x - 11; + return x; +} + +long +test_SUB_nez_2_imm (long x, long y, long c) +{ + if (!c) + x = y - 11; + else + x = y; + return x; +} + +long +test_SUB_nez_x_2_imm (long x, long c) +{ + if (!c) + x = x - 11; + + return x; +} + +long +test_SUB_eqz_2_imm (long x, long y, long c) +{ + if (!c) + x = y; + else + x = y - 11; + return x; +} + +long +test_SUB_eqz_x_2_imm (long x, long c) +{ + if (!c) + { + } + else + x = x - 11; + return x; +} + +long +test_IOR_ceqz_imm (long x, long y, long c) +{ + if (c) + x = y | 11; + else + x = y; + return x; +} + +long +test_IOR_ceqz_x_imm (long x, long c) +{ + if (c) + x = x | 11; + + return x; +} + +long +test_IOR_nez_imm (long x, long y, long c) +{ + if (c) + x = y; + else + x = y | 11; + return x; +} + +long +test_IOR_nez_x_imm (long x, long c) +{ + if (c) + { + } + else + x = x | 11; + return x; +} + +long +test_IOR_nez_2_imm (long x, long y, long c) +{ + if (!c) + x = y | 11; + else + x = y; + return x; +} + +long +test_IOR_nez_x_2_imm (long x, long c) +{ + if (!c) + x = x | 11; + + return x; +} + +long +test_IOR_eqz_2_imm (long x, long y, long c) +{ + if (!c) + x = y; + else + x = y | 11; + return x; +} + +long +test_IOR_eqz_x_2_imm (long x, long c) +{ + if (!c) + { + } + else + x = x | 11; + return x; +} + +long +test_XOR_ceqz_imm (long x, long y, long c) +{ + if (c) + x = y ^ 11; + else + x = y; + return x; +} + +long +test_XOR_ceqz_x_imm (long x, long c) +{ + if (c) + x = x ^ 11; + + return x; +} + +long +test_XOR_nez_imm (long x, long y, long c) +{ + if (c) + x = y; + else + x = y ^ 11; + return x; +} + +long +test_XOR_nez_x_imm (long x, long c) +{ + if (c) + { + } + else + x = x ^ 11; + return x; +} + +long +test_XOR_nez_2_imm (long x, long y, long c) +{ + if (!c) + x = y ^ 11; + else + x = y; + return x; +} + +long +test_XOR_nez_x_2_imm (long x, long c) +{ + if (!c) + x = x ^ 11; + + return x; +} + +long +test_XOR_eqz_2_imm (long x, long y, long c) +{ + if (!c) + x = y; + else + x = y ^ 11; + return x; +} + +long +test_XOR_eqz_x_2_imm (long x, long c) +{ + if (!c) + { + } + else + x = x ^ 11; + return x; +} + +long +test_ADD_ceqz_imm_reverse_bin_oprands (long x, long y, long c) +{ + if (c) + x = 11 + y; + else + x = y; + return x; +} + +long +test_ADD_ceqz_x_imm_reverse_bin_oprands (long x, long c) +{ + if (c) + x = 11 + x; + + return x; +} + +long +test_ADD_nez_imm_reverse_bin_oprands (long x, long y, long c) +{ + if (c) + x = y; + else + x = 11 + y; + return x; +} + +long +test_ADD_nez_x_imm_reverse_bin_oprands (long x, long c) +{ + if (c) + { + } + else + x = 11 + x; + return x; +} + +long +test_ADD_nez_2_imm_reverse_bin_oprands (long x, long y, long c) +{ + if (!c) + x = 11 + y; + else + x = y; + return x; +} + +long +test_ADD_nez_x_2_imm_reverse_bin_oprands (long x, long c) +{ + if (!c) + x = 11 + x; + + return x; +} + +long +test_ADD_eqz_2_imm_reverse_bin_oprands (long x, long y, long c) +{ + if (!c) + x = y; + else + x = 11 + y; + return x; +} + +long +test_ADD_eqz_x_2_imm_reverse_bin_oprands (long x, long c) +{ + if (!c) + { + } + else + x = 11 + x; + return x; +} + +long +test_IOR_ceqz_imm_reverse_bin_oprands (long x, long y, long c) +{ + if (c) + x = 11 | y; + else + x = y; + return x; +} + +long +test_IOR_ceqz_x_imm_reverse_bin_oprands (long x, long c) +{ + if (c) + x = 11 | x; + + return x; +} + +long +test_IOR_nez_imm_reverse_bin_oprands (long x, long y, long c) +{ + if (c) + x = y; + else + x = 11 | y; + return x; +} + +long +test_IOR_nez_x_imm_reverse_bin_oprands (long x, long c) +{ + if (c) + { + } + else + x = 11 | x; + return x; +} + +long +test_IOR_nez_2_imm_reverse_bin_oprands (long x, long y, long c) +{ + if (!c) + x = 11 | y; + else + x = y; + return x; +} + +long +test_IOR_nez_x_2_imm_reverse_bin_oprands (long x, long c) +{ + if (!c) + x = 11 | x; + + return x; +} + +long +test_IOR_eqz_2_imm_reverse_bin_oprands (long x, long y, long c) +{ + if (!c) + x = y; + else + x = 11 | y; + return x; +} + +long +test_IOR_eqz_x_2_imm_reverse_bin_oprands (long x, long c) +{ + if (!c) + { + } + else + x = 11 | x; + return x; +} + +long +test_XOR_ceqz_imm_reverse_bin_oprands (long x, long y, long c) +{ + if (c) + x = 11 ^ y; + else + x = y; + return x; +} + +long +test_XOR_ceqz_x_imm_reverse_bin_oprands (long x, long c) +{ + if (c) + x = 11 ^ x; + + return x; +} + +long +test_XOR_nez_imm_reverse_bin_oprands (long x, long y, long c) +{ + if (c) + x = y; + else + x = 11 ^ y; + return x; +} + +long +test_XOR_nez_x_imm_reverse_bin_oprands (long x, long c) +{ + if (c) + { + } + else + x = 11 ^ x; + return x; +} + +long +test_XOR_nez_2_imm_reverse_bin_oprands (long x, long y, long c) +{ + if (!c) + x = 11 ^ y; + else + x = y; + return x; +} + +long +test_XOR_nez_x_2_imm_reverse_bin_oprands (long x, long c) +{ + if (!c) + x = 11 ^ x; + + return x; +} + +long +test_XOR_eqz_2_imm_reverse_bin_oprands (long x, long y, long c) +{ + if (!c) + x = y; + else + x = 11 ^ y; + return x; +} + +long +test_XOR_eqz_x_2_imm_reverse_bin_oprands (long x, long c) +{ + if (!c) + { + } + else + x = 11 ^ x; + return x; +} + +long +test_ShiftLeft_eqz_imm (long x, long y, long c) +{ + if (c) + x = y << 11; + else + x = y; + return x; +} + +long +test_ShiftR_eqz_imm (long x, long y, long c) +{ + if (c) + x = y >> 11; + else + x = y; + return x; +} + +unsigned long +test_ShiftR_logical_eqz_imm (unsigned long x, unsigned long y, unsigned long z, + unsigned long c) +{ + if (c) + x = y >> 11; + else + x = y; + return x; +} + +unsigned long +test_RotateL_eqz_imm (unsigned long x, unsigned long y, unsigned long c) +{ + if (c) + x = (y << 11) | (y >> (64 - 11)); + else + x = y; + return x; +} + +unsigned long +test_RotateR_eqz_imm (unsigned long x, unsigned long y, unsigned long c) +{ + if (c) + x = (y >> 11) | (y << (64 - 11)); + else + x = y; + return x; +} long test_AND_ceqz (long x, long y, long z, long c) { @@ -774,5 +1384,165 @@ test_AND_eqz_x_2_reverse_bin_oprands (long x, long z, long c) x = z & x; return x; } -/* { dg-final { scan-assembler-times {czero\.eqz} 41 } } */ -/* { dg-final { scan-assembler-times {czero\.nez} 36 } } */ + +long +test_AND_ceqz_imm (long x, long y, long c) +{ + if (c) + x = y & 11; + else + x = y; + return x; +} + +long +test_AND_ceqz_x_imm (long x, long c) +{ + if (c) + x = x & 11; + + return x; +} + +long +test_AND_nez_imm (long x, long y, long c) +{ + if (c) + x = y; + else + x = y & 11; + return x; +} + +long +test_AND_nez_x_imm (long x, long c) +{ + if (c) + { + } + else + x = x & 11; + return x; +} + +long +test_AND_nez_2_imm (long x, long y, long c) +{ + if (!c) + x = y & 11; + else + x = y; + return x; +} + +long +test_AND_nez_x_2_imm (long x, long c) +{ + if (!c) + x = x & 11; + + return x; +} + +long +test_AND_eqz_2_imm (long x, long y, long c) +{ + if (!c) + x = y; + else + x = y & 11; + return x; +} + +long +test_AND_eqz_x_2_imm (long x, long c) +{ + if (!c) + { + } + else + x = x & 11; + return x; +} + +long +test_AND_ceqz_imm_reverse_bin_oprands (long x, long y, long c) +{ + if (c) + x = 11 & y; + else + x = y; + return x; +} + +long +test_AND_ceqz_x_imm_reverse_bin_oprands (long x, long c) +{ + if (c) + x = 11 & x; + + return x; +} + +long +test_AND_nez_imm_reverse_bin_oprands (long x, long y, long c) +{ + if (c) + x = y; + else + x = 11 & y; + return x; +} + +long +test_AND_nez_x_imm_reverse_bin_oprands (long x, long c) +{ + if (c) + { + } + else + x = 11 & x; + return x; +} + +long +test_AND_nez_2_imm_reverse_bin_oprands (long x, long y, long c) +{ + if (!c) + x = 11 & y; + else + x = y; + return x; +} + +long +test_AND_nez_x_2_imm_reverse_bin_oprands (long x, long c) +{ + if (!c) + x = 11 & x; + + return x; +} + +long +test_AND_eqz_2_imm_reverse_bin_oprands (long x, long y, long c) +{ + if (!c) + x = y; + else + x = 11 & y; + return x; +} + +long +test_AND_eqz_x_2_imm_reverse_bin_oprands (long x, long c) +{ + if (!c) + { + } + else + x = 11 & x; + return x; +} +/* { dg-final { scan-assembler-times {czero\.eqz} 82 } } */ +/* { dg-final { scan-assembler-times {czero\.nez} 72 } } */ From patchwork Tue Dec 5 08:12:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fei Gao X-Patchwork-Id: 1871871 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SktcV16cvz1yST for ; Tue, 5 Dec 2023 19:14:50 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D3E373845770 for ; Tue, 5 Dec 2023 08:14:47 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from azure-sdnproxy.icoremail.net (azure-sdnproxy.icoremail.net [52.237.72.81]) by sourceware.org (Postfix) with ESMTP id 93B35385DC33 for ; Tue, 5 Dec 2023 08:13:54 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 93B35385DC33 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=eswincomputing.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 93B35385DC33 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=52.237.72.81 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701764036; cv=none; b=uaxxCZ/R3k0OSRdcf8HuBG0FL+PhTRrEm99vQ2E+wh4+NW1uK+OdY1C+3gvQ/F8/geZWqtO3Nae9Q8GQ3Po2w6p3hDjh7M51rhv3wu7JvAZ+60xMHOvUdT1eZ+nbtEpc21WIIE+Akyucg4XNQIZ2gHLOyvkWWsh4QTVLEVl1+ME= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701764036; c=relaxed/simple; bh=A5wvQieJiKxnYTEzXfqOmyFDbpiKgbaFEWCNEGR5ols=; h=From:To:Subject:Date:Message-Id; b=ohOR2iXHSjSGKXwFtn6oIGxNNv+IkjyRr4MhKfFncnhMeYXoF23VUQPD2PP7DNDbQybY6r46nCfHYStQzeJB3HrYKFfTl0ZBI894fY65oGYWAsAkaHBhm2gWrj3j3tVt87+KghTB4a8eT1Ww9kv/pAGNMmLlOp4OkhaXkxJ8rQ8= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from localhost.localdomain (unknown [10.12.130.31]) by app2 (Coremail) with SMTP id TQJkCgBH1tR2225lPkgAAA--.4441S8; Tue, 05 Dec 2023 16:12:46 +0800 (CST) From: Fei Gao To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, jeffreyalaw@gmail.com, zengxiao@eswincomputing.com, Fei Gao Subject: [PATCH 5/5] [ifcvt] optimize extension for x=c ? (y op z) : y by RISC-V Zicond like insns Date: Tue, 5 Dec 2023 08:12:48 +0000 Message-Id: <20231205081248.2106-5-gaofei@eswincomputing.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231205081248.2106-1-gaofei@eswincomputing.com> References: <20231205081248.2106-1-gaofei@eswincomputing.com> X-CM-TRANSID: TQJkCgBH1tR2225lPkgAAA--.4441S8 X-Coremail-Antispam: 1UD129KBjvJXoWxXr4xAry5WrW7ur15tF4xZwb_yoWruFWfpF 43Ww1qvrZ8tFyS9FZ3GF43JF43CrW3tas3Xws3JrWrGwn8XFWFqrWSv34aqrW8GFs3uF13 Aa9xZr42gwsrJa7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBS14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_tr0E3s1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F 4UJwA2z4x0Y4vEx4A2jsIE14v26rxl6s0DM28EF7xvwVC2z280aVCY1x0267AKxVW0oVCq 3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7 IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4U M4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwCY02Avz4vE-syl42xK82 IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC2 0s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r126r1DMIIYrxkI7VAKI48JMI IF0xvE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4j6F4UMIIF 0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87 Iv6xkF7I0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjfUOBTYUUUUU X-CM-SenderInfo: xjdrwv3l6h245lqf0zpsxwx03jof0z/ X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org SIGN_EXTEND, ZERO_EXTEND and SUBREG has been considered to support SImode in 64-bit machine. Co-authored-by: Xiao Zeng gcc/ChangeLog: * ifcvt.cc (noce_cond_zero_binary_op_supported): add support for extension (noce_bbs_ok_for_cond_zero_arith): likewise (noce_try_cond_zero_arith): support extension of LSHIFTRT case gcc/testsuite/ChangeLog: * gcc.target/riscv/zicond_ifcvt_opt.c: add TCs for extension --- gcc/ifcvt.cc | 16 ++- .../gcc.target/riscv/zicond_ifcvt_opt.c | 126 +++++++++++++++++- 2 files changed, 139 insertions(+), 3 deletions(-) diff --git a/gcc/ifcvt.cc b/gcc/ifcvt.cc index b84be53ec5c..306497a8e37 100644 --- a/gcc/ifcvt.cc +++ b/gcc/ifcvt.cc @@ -2934,6 +2934,10 @@ noce_cond_zero_binary_op_supported (rtx op) { enum rtx_code opcode = GET_CODE (op); + /* Strip SIGN_EXTEND or ZERO_EXTEND if any. */ + if (opcode == SIGN_EXTEND || opcode == ZERO_EXTEND) + opcode = GET_CODE (XEXP (op, 0)); + if (opcode == PLUS || opcode == MINUS || opcode == IOR || opcode == XOR || opcode == AND || noce_cond_zero_shift_op_supported (opcode)) return true; @@ -3000,7 +3004,11 @@ noce_bbs_ok_for_cond_zero_arith (struct noce_if_info *if_info, rtx *common_ptr, if (!(noce_cond_zero_binary_op_supported (a) && REG_P (b))) return false; - bin_exp = a; + /* Strip sign_extend if any. */ + if (GET_CODE (a) == SIGN_EXTEND || GET_CODE (a) == ZERO_EXTEND) + bin_exp = XEXP (a, 0); + else + bin_exp = a; /* Canonicalize x = (z op y) : y to x = (y op z) : y */ op1 = get_base_reg (XEXP (bin_exp, 1)); @@ -3114,7 +3122,11 @@ noce_try_cond_zero_arith (struct noce_if_info *if_info) if (CONST_INT_P (*to_replace)) { if (noce_cond_zero_shift_op_supported (bin_code)) - *to_replace = gen_rtx_SUBREG (E_QImode, target, 0); + { + *to_replace = gen_rtx_SUBREG (E_QImode, target, 0); + if (GET_CODE (a) == ZERO_EXTEND && bin_code == LSHIFTRT) + PUT_CODE (a, SIGN_EXTEND); + } else if (SUBREG_P (bin_op0)) *to_replace = gen_rtx_SUBREG (GET_MODE (bin_op0), target, 0); else diff --git a/gcc/testsuite/gcc.target/riscv/zicond_ifcvt_opt.c b/gcc/testsuite/gcc.target/riscv/zicond_ifcvt_opt.c index 85743e1734c..53206d76e9f 100644 --- a/gcc/testsuite/gcc.target/riscv/zicond_ifcvt_opt.c +++ b/gcc/testsuite/gcc.target/riscv/zicond_ifcvt_opt.c @@ -615,6 +615,69 @@ test_RotateR_eqz (unsigned long x, unsigned long y, unsigned long z, return x; } +int +test_ADD_ceqz_int (int x, int y, int z, int c) +{ + if (c) + x = y + z; + else + x = y; + return x; +} + +int +test_ShiftLeft_eqz_int (int x, int y, int z, int c) +{ + if (c) + x = y << z; + else + x = y; + return x; +} + +int +test_ShiftR_eqz_int (int x, int y, int z, int c) +{ + if (c) + x = y >> z; + else + x = y; + return x; +} + +unsigned int +test_ShiftR_logical_eqz_int (unsigned int x, unsigned int y, unsigned int z, + unsigned int c) +{ + if (c) + x = y >> z; + else + x = y; + return x; +} + +unsigned int +test_RotateL_eqz_int (unsigned int x, unsigned int y, unsigned int z, + unsigned int c) +{ + if (c) + x = (y << z) | (y >> (32 - z)); + else + x = y; + return x; +} + +unsigned int +test_RotateR_eqz_int (unsigned int x, unsigned int y, unsigned int z, + unsigned int c) +{ + if (c) + x = (y >> z) | (y << (32 - z)); + else + x = y; + return x; +} + long test_ADD_ceqz_imm (long x, long y, long c) { @@ -1225,6 +1288,67 @@ test_RotateR_eqz_imm (unsigned long x, unsigned long y, unsigned long c) x = y; return x; } + +int +test_ADD_ceqz_imm_int (int x, int y, int c) +{ + if (c) + x = y + 11; + else + x = y; + return x; +} + +int +test_ShiftLeft_eqz_imm_int (int x, int y, int c) +{ + if (c) + x = y << 11; + else + x = y; + return x; +} + +int +test_ShiftR_eqz_imm_int (int x, int y, int c) +{ + if (c) + x = y >> 11; + else + x = y; + return x; +} + +unsigned int +test_ShiftR_logical_eqz_imm_int (unsigned int x, unsigned int y, unsigned int c) +{ + if (c) + x = y >> 11; + else + x = y; + return x; +} + +unsigned int +test_RotateL_eqz_imm_int (unsigned int x, unsigned int y, unsigned int c) +{ + if (c) + x = (y << 11) | (y >> (32 - 11)); + else + x = y; + return x; +} + +unsigned int +test_RotateR_eqz_imm_int (unsigned int x, unsigned int y, unsigned int c) +{ + if (c) + x = (y >> 11) | (y << (32 - 11)); + else + x = y; + return x; +} + long test_AND_ceqz (long x, long y, long z, long c) { @@ -1544,5 +1668,5 @@ test_AND_eqz_x_2_imm_reverse_bin_oprands (long x, long c) x = 11 & x; return x; } -/* { dg-final { scan-assembler-times {czero\.eqz} 82 } } */ +/* { dg-final { scan-assembler-times {czero\.eqz} 94 } } */ /* { dg-final { scan-assembler-times {czero\.nez} 72 } } */