From patchwork Wed Nov 29 01:21:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Hu, Lin1" X-Patchwork-Id: 1869542 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=nj1nBuDu; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Sg1n16TYvz1yST for ; Wed, 29 Nov 2023 12:23:49 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D65393858421 for ; Wed, 29 Nov 2023 01:23:46 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.31]) by sourceware.org (Postfix) with ESMTPS id 009933858D3C for ; Wed, 29 Nov 2023 01:23:33 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 009933858D3C Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 009933858D3C Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=134.134.136.31 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701221015; cv=none; b=vHpKtbsU6L6hmnyhy5VKjGTjEXgTbCrwtuQqGjkoimSh6Wetyrr3t/iMkNIyDRvkh4T0LmgZk9RIEYdNdvSzmGrHlocAgsp9xpyysdrOYAQnJHWyNp63zYNVzSx/KFGLcEO4RiSJk1f+ynxwmRsOSwmcG8HRME6v3DoJw4pAPCQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701221015; c=relaxed/simple; bh=8pG1hIoPNNvTxrjoQ9JlqbckwfumVRRSlQASJoa8u5M=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=uFACiK8WVlmuiJppHB5tvw0SW9+JEeFQEBUc4HuUMv9Gl1d/fY+7v5QuvOXPmD/iP0pp+OU6eDpX1Uxy9ohgDhnxtoXc9RJ0W4mKXNS//2TwXKuIqBnnCpcHcPGLqXdvCquuOGzumFBA6WNETHN0JSrCQuFTAldIG1FCG2P1Z7A= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1701221014; x=1732757014; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=8pG1hIoPNNvTxrjoQ9JlqbckwfumVRRSlQASJoa8u5M=; b=nj1nBuDulQyAkmKyJSD5Bz3NkyRrNFJIfIjJFZOMmFF17+Rx5d65g4Ah uUo3YI4P0hSOjtmg7PN9aaDdCr9O21lJSLuIHxOczUv3ypFyuzOmX2fVs FcGf8W8FsBzHHZeLAZpPnGWIQS70XOQlSpxbVvkXwQRQJ3htiReRDV1Mk uST0YoiEsrw1xEgMOb858rMSbvdi7sFrrSGsamFCD5JGzaJG1eI3HHOJW WbWp6ePAlycXrDZfI/mnNOllKvnsrGjrLbXWBhH4bJYEoATjgUZQuWFpO huP3nElegRp/VsxqXQPJPMqr8ALU3bEE87DRn64MC2fC9HSZGeHadI4pW g==; X-IronPort-AV: E=McAfee;i="6600,9927,10908"; a="457405546" X-IronPort-AV: E=Sophos;i="6.04,234,1695711600"; d="scan'208";a="457405546" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Nov 2023 17:23:28 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10908"; a="803117776" X-IronPort-AV: E=Sophos;i="6.04,234,1695711600"; d="scan'208";a="803117776" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga001.jf.intel.com with ESMTP; 28 Nov 2023 17:23:25 -0800 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id C0742100567D; Wed, 29 Nov 2023 09:23:25 +0800 (CST) From: "Hu, Lin1" To: gcc-patches@gcc.gnu.org Cc: hongtao.liu@intel.com, ubizjak@gmail.com Subject: [PATCH] i386: Fix CPUID of USER_MSR. Date: Wed, 29 Nov 2023 09:21:25 +0800 Message-Id: <20231129012125.458224-1-lin1.hu@intel.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-Spam-Status: No, score=-10.5 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Hi, all This patch aims to fix the wrong CPUID of USER_MSR, its correct CPUID is (0x7, 0x1).EDX[15], But I set it as (0x7, 0x0).EDX[15]. And the patch modefied testcase for give the user a better example. It has been bootstrapped and regtested on x86-64-pc-linux-gnu, OK for trunk? BR, Lin gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Move USER_MSR to the correct location. gcc/testsuite/ChangeLog: * gcc.target/i386/user_msr-1.c: Correct the MSR index for give the user an proper example. --- gcc/common/config/i386/cpuinfo.h | 4 ++-- gcc/testsuite/gcc.target/i386/user_msr-1.c | 9 +++++---- 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h index f90fb4d56a2..a1eb285daed 100644 --- a/gcc/common/config/i386/cpuinfo.h +++ b/gcc/common/config/i386/cpuinfo.h @@ -861,8 +861,6 @@ get_available_features (struct __processor_model *cpu_model, set_feature (FEATURE_IBT); if (edx & bit_UINTR) set_feature (FEATURE_UINTR); - if (edx & bit_USER_MSR) - set_feature (FEATURE_USER_MSR); if (amx_usable) { if (edx & bit_AMX_TILE) @@ -921,6 +919,8 @@ get_available_features (struct __processor_model *cpu_model, set_feature (FEATURE_PREFETCHI); if (eax & bit_RAOINT) set_feature (FEATURE_RAOINT); + if (edx & bit_USER_MSR) + set_feature (FEATURE_USER_MSR); if (avx_usable) { if (eax & bit_AVXVNNI) diff --git a/gcc/testsuite/gcc.target/i386/user_msr-1.c b/gcc/testsuite/gcc.target/i386/user_msr-1.c index 447852306df..f315016d088 100644 --- a/gcc/testsuite/gcc.target/i386/user_msr-1.c +++ b/gcc/testsuite/gcc.target/i386/user_msr-1.c @@ -1,9 +1,9 @@ /* { dg-do compile { target { ! ia32 } } } */ /* { dg-options "-musermsr -O2" } */ /* { dg-final { scan-assembler-times "urdmsr\[ \\t\]\\%r\[a-z\]x, \\%r\[a-z\]x" 1 } } */ -/* { dg-final { scan-assembler-times "urdmsr\[ \\t\]\\\$121" 1 } } */ +/* { dg-final { scan-assembler-times "urdmsr\[ \\t\]\\\$6912" 1 } } */ /* { dg-final { scan-assembler-times "uwrmsr\[ \\t\]\\%r\[a-z\]x, \\%r\[a-z\]x" 1 } } */ -/* { dg-final { scan-assembler-times "uwrmsr\[ \\t\]\\%r\[a-z\]x, \\\$121" 1 } } */ +/* { dg-final { scan-assembler-times "uwrmsr\[ \\t\]\\%r\[a-z\]x, \\\$6912" 1 } } */ #include @@ -13,8 +13,9 @@ volatile unsigned long long y; void extern user_msr_test (void) { + y = 6913; x = _urdmsr(y); - x = _urdmsr(121); + x = _urdmsr(6912); _uwrmsr(y, x); - _uwrmsr(121, x); + _uwrmsr(6912, x); }