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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701187182; x=1701791982; h=to:subject:message-id:date:from:mime-version:x-gm-message-state :from:to:cc:subject:date:message-id:reply-to; bh=o0tGZJuMp6Kji4S9cc0zUe9wAj1auE9buwFPAqv2njk=; b=aXgCqisuwSIqpIkGQayoFgONNnHGVXdUUlWGcV+Y/WW0Ck7SdGENbDVlurstYX1pHj GMMmY70XlXqe8/hvTgreyhnYaBciLK3E/l2d5MFqECqvNhgpayRPhOZtiW5weVbNGz2v 6xBfmxPEeMOXkD9FAokOSFBuvf40lHTKDB6IJaqe3fbMGTBrYe3hQIU8ocCq9FLAnbI4 K2ZPZQJ7j9Dq4EjfcUPqVCcouwhgvsstYnVl+0WZSExagle9nnmC/CwYkRAc4fGxLbY3 ADsBWm/Kn3DHJk2CzA0DZpf5a6SQbiLVdpg2TteBahWu0nvKtzB1tUsOhoSR+YirzK41 0j0Q== X-Gm-Message-State: AOJu0YxyOZkIKYFm8Mxn9XLx2wSQy7JDYXCg3R077ZPf0ZLLHRfqhhs+ h5rml0TSBTDtauqIybtFss30DZ2uVXTsKOBP/IUNIrsKf7bPlg== X-Google-Smtp-Source: AGHT+IFjOPwAyqAWaLZJpn5Z22SYtdxxyW9LyW2l5E1HkA86vTPO4RUuzEdvtnUo1QxWE5furB+Grt2LnJHXJPRQ9U4= X-Received: by 2002:a05:6402:33a:b0:54b:922:1f43 with SMTP id q26-20020a056402033a00b0054b09221f43mr9438602edw.7.1701187182371; Tue, 28 Nov 2023 07:59:42 -0800 (PST) MIME-Version: 1.0 From: Uros Bizjak Date: Tue, 28 Nov 2023 16:59:31 +0100 Message-ID: Subject: [committed] i386: Improve cmpstrnqi_1 insn pattern [PR112494] To: "gcc-patches@gcc.gnu.org" X-Spam-Status: No, score=-8.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org REPZ CMPSB instruction does not update FLAGS register when %ecx register equals zero. Improve cmpstrnqi_1 insn pattern to set FLAGS_REG to its previous value instead of (const_int 0) when operand 2 equals zero. PR target/112494 gcc/ChangeLog: * config/i386/i386.md (cmpstrnqi_1): Set FLAGS_REG to its previous value when operand 2 equals zero. (*cmpstrnqi_1): Ditto. (*cmpstrnqi_1 peephole2): Ditto. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Uros. diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index cb32de7fab8..7641b479670 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -23333,9 +23333,8 @@ (define_expand "cmpstrnqi_1" (const_int 0)) (compare:CC (match_operand 4 "memory_operand") (match_operand 5 "memory_operand")) - (const_int 0))) + (reg:CC FLAGS_REG))) (use (match_operand:SI 3 "immediate_operand")) - (use (reg:CC FLAGS_REG)) (clobber (match_operand 0 "register_operand")) (clobber (match_operand 1 "register_operand")) (clobber (match_dup 2))])] @@ -23351,9 +23350,8 @@ (define_insn "*cmpstrnqi_1" (const_int 0)) (compare:CC (mem:BLK (match_operand:P 4 "register_operand" "0")) (mem:BLK (match_operand:P 5 "register_operand" "1"))) - (const_int 0))) + (reg:CC FLAGS_REG))) (use (match_operand:SI 3 "immediate_operand" "i")) - (use (reg:CC FLAGS_REG)) (clobber (match_operand:P 0 "register_operand" "=S")) (clobber (match_operand:P 1 "register_operand" "=D")) (clobber (match_operand:P 2 "register_operand" "=c"))] @@ -23464,9 +23462,8 @@ (define_peephole2 (const_int 0)) (compare:CC (mem:BLK (match_operand 4 "register_operand")) (mem:BLK (match_operand 5 "register_operand"))) - (const_int 0))) + (reg:CC FLAGS_REG))) (use (match_operand:SI 3 "immediate_operand")) - (use (reg:CC FLAGS_REG)) (clobber (match_operand 0 "register_operand")) (clobber (match_operand 1 "register_operand")) (clobber (match_operand 2 "register_operand"))]) @@ -23484,9 +23481,8 @@ (define_peephole2 (const_int 0)) (compare:CC (mem:BLK (match_dup 4)) (mem:BLK (match_dup 5))) - (const_int 0))) + (reg:CC FLAGS_REG))) (use (match_dup 3)) - (use (reg:CC FLAGS_REG)) (clobber (match_dup 0)) (clobber (match_dup 1)) (clobber (match_dup 2))])])