From patchwork Thu Nov 23 17:22:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Davis X-Patchwork-Id: 1867880 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256 header.s=ti-com-17Q1 header.b=K2rKJFF7; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SblL175Bnz1yS0 for ; Fri, 24 Nov 2023 04:22:33 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 8769B86BDB; Thu, 23 Nov 2023 18:22:25 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="K2rKJFF7"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id B1AF987686; Thu, 23 Nov 2023 18:22:22 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.2 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_MSPIKE_H2, SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 801F68765E for ; Thu, 23 Nov 2023 18:22:20 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=afd@ti.com Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 3ANHMHLa056463; Thu, 23 Nov 2023 11:22:17 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1700760137; bh=bwabuxGTrimE+p/UNjPmvW6Jf2NyeoB1I2xVaGQfwjk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=K2rKJFF7vsjTqUS/09Be8hlR1RODOlQ0zP9D1gcdI6EDtCqvSTjsf8fxbdNXq4rfK bYLzsERNXWveSc5LqoqBLHX4HY3h1VvFzsUlFIyADUezP1AV2cXXmeo9O1yJ4DhRKu mocDmwNjeEzUNETHI922+bZ29WjpwFuBMtCuyQmY= Received: from DLEE102.ent.ti.com (dlee102.ent.ti.com [157.170.170.32]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 3ANHMHxW058411 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 23 Nov 2023 11:22:17 -0600 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 23 Nov 2023 11:22:16 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 23 Nov 2023 11:22:16 -0600 Received: from lelv0326.itg.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 3ANHMFvX114031; Thu, 23 Nov 2023 11:22:16 -0600 From: Andrew Davis To: Neha Malcom Francis , Vignesh Raghavendra , Nishanth Menon , Simon Glass , Tom Rini , Apurva Nandan CC: , Andrew Davis Subject: [PATCH 1/3] arm: mach-k3: Let the compiler size the mem_map lists Date: Thu, 23 Nov 2023 11:22:12 -0600 Message-ID: <20231123172214.653268-2-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231123172214.653268-1-afd@ti.com> References: <20231123172214.653268-1-afd@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean NR_MMU_REGIONS is a copy/paste from another platform that extends this list later. We do not do that, so let the list be the size of the initializer list. Signed-off-by: Andrew Davis Reviewed-by: Nishanth Menon Tested-by: Nishanth Menon --- arch/arm/mach-k3/arm64-mmu.c | 35 ++++++----------------------------- 1 file changed, 6 insertions(+), 29 deletions(-) diff --git a/arch/arm/mach-k3/arm64-mmu.c b/arch/arm/mach-k3/arm64-mmu.c index e8db5332ae0..d872ed714c4 100644 --- a/arch/arm/mach-k3/arm64-mmu.c +++ b/arch/arm/mach-k3/arm64-mmu.c @@ -13,11 +13,7 @@ #include #ifdef CONFIG_SOC_K3_AM654 -/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */ -#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 5) - -/* ToDo: Add 64bit IO */ -struct mm_region am654_mem_map[NR_MMU_REGIONS] = { +struct mm_region am654_mem_map[] = { { .virt = 0x0UL, .phys = 0x0UL, @@ -68,10 +64,7 @@ struct mm_region *mem_map = am654_mem_map; #ifdef CONFIG_SOC_K3_J721E #ifdef CONFIG_SOC_K3_J721E_J7200 -#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 5) - -/* ToDo: Add 64bit IO */ -struct mm_region j7200_mem_map[NR_MMU_REGIONS] = { +struct mm_region j7200_mem_map[] = { { .virt = 0x0UL, .phys = 0x0UL, @@ -119,12 +112,7 @@ struct mm_region j7200_mem_map[NR_MMU_REGIONS] = { struct mm_region *mem_map = j7200_mem_map; #else /* CONFIG_SOC_K3_J721E_J7200 */ - -/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */ -#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 6) - -/* ToDo: Add 64bit IO */ -struct mm_region j721e_mem_map[NR_MMU_REGIONS] = { +struct mm_region j721e_mem_map[] = { { .virt = 0x0UL, .phys = 0x0UL, @@ -181,10 +169,7 @@ struct mm_region *mem_map = j721e_mem_map; #endif /* CONFIG_SOC_K3_J721E */ #ifdef CONFIG_SOC_K3_J721S2 -#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 3) - -/* ToDo: Add 64bit IO */ -struct mm_region j721s2_mem_map[NR_MMU_REGIONS] = { +struct mm_region j721s2_mem_map[] = { { .virt = 0x0UL, .phys = 0x0UL, @@ -223,11 +208,7 @@ struct mm_region *mem_map = j721s2_mem_map; #if defined(CONFIG_SOC_K3_AM625) || defined(CONFIG_SOC_K3_AM62A7) -/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */ -#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 4) - -/* ToDo: Add 64bit IO */ -struct mm_region am62_mem_map[NR_MMU_REGIONS] = { +struct mm_region am62_mem_map[] = { { .virt = 0x0UL, .phys = 0x0UL, @@ -272,11 +253,7 @@ struct mm_region *mem_map = am62_mem_map; #ifdef CONFIG_SOC_K3_AM642 -/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */ -#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 4) - -/* ToDo: Add 64bit IO */ -struct mm_region am64_mem_map[NR_MMU_REGIONS] = { +struct mm_region am64_mem_map[] = { { .virt = 0x0UL, .phys = 0x0UL, From patchwork Thu Nov 23 17:22:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Davis X-Patchwork-Id: 1867881 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256 header.s=ti-com-17Q1 header.b=Om5bGgl7; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; 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Thu, 23 Nov 2023 11:22:17 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 23 Nov 2023 11:22:17 -0600 Received: from lelv0326.itg.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 3ANHMFvY114031; Thu, 23 Nov 2023 11:22:16 -0600 From: Andrew Davis To: Neha Malcom Francis , Vignesh Raghavendra , Nishanth Menon , Simon Glass , Tom Rini , Apurva Nandan CC: , Andrew Davis Subject: [PATCH 2/3] arm: mach-k3: Remove non-cached memory map areas Date: Thu, 23 Nov 2023 11:22:13 -0600 Message-ID: <20231123172214.653268-3-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231123172214.653268-1-afd@ti.com> References: <20231123172214.653268-1-afd@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean All normal memory areas should be mapped as such. We added these un-cached holes in our memory map to hack around the remoteproc driver missing the proper cache maintenance operations. The problem is having these non-cached memory map areas causes stability issues later in system operation due to the nature of the K3 coherency architecture. Plus these are board specific carveouts and instead should have been added at the board level, not here in the SoC common code area. Remove these non-cached memory map areas. Signed-off-by: Andrew Davis Reviewed-by: Nishanth Menon Tested-by: Nishanth Menon --- arch/arm/mach-k3/arm64-mmu.c | 65 +++--------------------------------- 1 file changed, 5 insertions(+), 60 deletions(-) diff --git a/arch/arm/mach-k3/arm64-mmu.c b/arch/arm/mach-k3/arm64-mmu.c index d872ed714c4..97a029af13f 100644 --- a/arch/arm/mach-k3/arm64-mmu.c +++ b/arch/arm/mach-k3/arm64-mmu.c @@ -24,19 +24,7 @@ struct mm_region am654_mem_map[] = { }, { .virt = 0x80000000UL, .phys = 0x80000000UL, - .size = 0x20000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0xa0000000UL, - .phys = 0xa0000000UL, - .size = 0x02100000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0xa2100000UL, - .phys = 0xa2100000UL, - .size = 0x5df00000UL, + .size = 0x80000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, { @@ -75,19 +63,7 @@ struct mm_region j7200_mem_map[] = { }, { .virt = 0x80000000UL, .phys = 0x80000000UL, - .size = 0x20000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0xa0000000UL, - .phys = 0xa0000000UL, - .size = 0x04800000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) | - PTE_BLOCK_NON_SHARE - }, { - .virt = 0xa4800000UL, - .phys = 0xa4800000UL, - .size = 0x5b800000UL, + .size = 0x80000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, { @@ -123,19 +99,7 @@ struct mm_region j721e_mem_map[] = { }, { .virt = 0x80000000UL, .phys = 0x80000000UL, - .size = 0x20000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0xa0000000UL, - .phys = 0xa0000000UL, - .size = 0x1bc00000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) | - PTE_BLOCK_NON_SHARE - }, { - .virt = 0xbbc00000UL, - .phys = 0xbbc00000UL, - .size = 0x44400000UL, + .size = 0x80000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, { @@ -151,12 +115,6 @@ struct mm_region j721e_mem_map[] = { .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - .virt = 0x4d80000000UL, - .phys = 0x4d80000000UL, - .size = 0x0002000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) | - PTE_BLOCK_INNER_SHARE }, { /* List terminator */ 0, @@ -219,16 +177,9 @@ struct mm_region am62_mem_map[] = { }, { .virt = 0x80000000UL, .phys = 0x80000000UL, - .size = 0x1E780000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0xA0000000UL, - .phys = 0xA0000000UL, - .size = 0x60000000UL, + .size = 0x80000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE - }, { .virt = 0x880000000UL, .phys = 0x880000000UL, @@ -264,13 +215,7 @@ struct mm_region am64_mem_map[] = { }, { .virt = 0x80000000UL, .phys = 0x80000000UL, - .size = 0x1E800000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0xA0000000UL, - .phys = 0xA0000000UL, - .size = 0x60000000UL, + .size = 0x80000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, { From patchwork Thu Nov 23 17:22:14 2023 Content-Type: text/plain; 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Thu, 23 Nov 2023 11:22:17 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 23 Nov 2023 11:22:18 -0600 Received: from lelv0326.itg.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 3ANHMFvZ114031; Thu, 23 Nov 2023 11:22:17 -0600 From: Andrew Davis To: Neha Malcom Francis , Vignesh Raghavendra , Nishanth Menon , Simon Glass , Tom Rini , Apurva Nandan CC: , Andrew Davis Subject: [PATCH 3/3] arm: mach-k3: Merge initial memory maps Date: Thu, 23 Nov 2023 11:22:14 -0600 Message-ID: <20231123172214.653268-4-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231123172214.653268-1-afd@ti.com> References: <20231123172214.653268-1-afd@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The Device vs Normal memory map is the same for all K3 SoCs. Merge the SoC specific maps into one. Signed-off-by: Andrew Davis Reviewed-by: Nishanth Menon Tested-by: Nishanth Menon --- arch/arm/mach-k3/arm64-mmu.c | 197 +---------------------------------- 1 file changed, 2 insertions(+), 195 deletions(-) diff --git a/arch/arm/mach-k3/arm64-mmu.c b/arch/arm/mach-k3/arm64-mmu.c index 97a029af13f..ccc4161be99 100644 --- a/arch/arm/mach-k3/arm64-mmu.c +++ b/arch/arm/mach-k3/arm64-mmu.c @@ -12,8 +12,7 @@ #include #include -#ifdef CONFIG_SOC_K3_AM654 -struct mm_region am654_mem_map[] = { +struct mm_region k3_mem_map[] = { { .virt = 0x0UL, .phys = 0x0UL, @@ -46,196 +45,4 @@ struct mm_region am654_mem_map[] = { } }; -struct mm_region *mem_map = am654_mem_map; -#endif /* CONFIG_SOC_K3_AM654 */ - -#ifdef CONFIG_SOC_K3_J721E - -#ifdef CONFIG_SOC_K3_J721E_J7200 -struct mm_region j7200_mem_map[] = { - { - .virt = 0x0UL, - .phys = 0x0UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - .virt = 0x80000000UL, - .phys = 0x80000000UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0x880000000UL, - .phys = 0x880000000UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0x500000000UL, - .phys = 0x500000000UL, - .size = 0x400000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - /* List terminator */ - 0, - } -}; - -struct mm_region *mem_map = j7200_mem_map; - -#else /* CONFIG_SOC_K3_J721E_J7200 */ -struct mm_region j721e_mem_map[] = { - { - .virt = 0x0UL, - .phys = 0x0UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - .virt = 0x80000000UL, - .phys = 0x80000000UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0x880000000UL, - .phys = 0x880000000UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0x500000000UL, - .phys = 0x500000000UL, - .size = 0x400000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - /* List terminator */ - 0, - } -}; - -struct mm_region *mem_map = j721e_mem_map; -#endif /* CONFIG_SOC_K3_J721E_J7200 */ - -#endif /* CONFIG_SOC_K3_J721E */ - -#ifdef CONFIG_SOC_K3_J721S2 -struct mm_region j721s2_mem_map[] = { - { - .virt = 0x0UL, - .phys = 0x0UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - .virt = 0x80000000UL, - .phys = 0x80000000UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0x880000000UL, - .phys = 0x880000000UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0x500000000UL, - .phys = 0x500000000UL, - .size = 0x400000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - /* List terminator */ - 0, - } -}; - -struct mm_region *mem_map = j721s2_mem_map; - -#endif /* CONFIG_SOC_K3_J721S2 */ - -#if defined(CONFIG_SOC_K3_AM625) || defined(CONFIG_SOC_K3_AM62A7) - -struct mm_region am62_mem_map[] = { - { - .virt = 0x0UL, - .phys = 0x0UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - .virt = 0x80000000UL, - .phys = 0x80000000UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0x880000000UL, - .phys = 0x880000000UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0x500000000UL, - .phys = 0x500000000UL, - .size = 0x400000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - /* List terminator */ - 0, - } -}; - -struct mm_region *mem_map = am62_mem_map; -#endif /* CONFIG_SOC_K3_AM625 || CONFIG_SOC_K3_AM62A7 */ - -#ifdef CONFIG_SOC_K3_AM642 - -struct mm_region am64_mem_map[] = { - { - .virt = 0x0UL, - .phys = 0x0UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - .virt = 0x80000000UL, - .phys = 0x80000000UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0x880000000UL, - .phys = 0x880000000UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0x500000000UL, - .phys = 0x500000000UL, - .size = 0x400000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - /* List terminator */ - 0, - } -}; - -struct mm_region *mem_map = am64_mem_map; -#endif /* CONFIG_SOC_K3_AM642 */ +struct mm_region *mem_map = k3_mem_map;