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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700061237; x=1700666037; h=to:subject:message-id:date:from:mime-version:x-gm-message-state :from:to:cc:subject:date:message-id:reply-to; bh=V0PG7Du8G0dUBQ1c4vw/M3hQQ6deR4DrSjh4iccpyFI=; b=ZQeUFo/UUS/fSLgDqzNR1jDsqvKKokDwJCOnLryiDWXNaHm8syGKdG8iZOEMNQSTmo Ph01Gi9w2unF+LTjyRbltX0vowQ338Ixx3Eg8c0lTPI2uX7EIENBcb8ELL87jehLUbMl I/Us614pK/8cvy1ue6281yVXaRbnuRtKpdA2B0RhYB18XrCkcxKVq4uunJuBLobrlLqr EiSUTE44bVDqWxaHMWKQ+i6eo/pH9d2Zv+ZrCXUFdBI+sPU0X1ptBTIXKVOalnlrnHec MRubvFnI/dyBLiVfRb27Dz3EPUJqC46QLUfNx71ohteIK+TMgLhSBWsnHyYQgO11ClRL lYVA== X-Gm-Message-State: AOJu0YybTFwoml55I+FiR1OS0KfqHVXeNuQqoqNTz2awE5wExbIYdbAr wlgXSyBaNYNGjiwZuEVWFiKA8eguAya+IeKzPdjph8EhX9B9iA== X-Google-Smtp-Source: AGHT+IGy9QbI/dBq8hsDtquzw4z7apDKZRW0FVzdh7EoumPbetURWude6xzFwOO6SNyEkqQKaJN+t2xHXh7LRXedap0= X-Received: by 2002:a05:6402:4e:b0:543:5dd9:a72 with SMTP id f14-20020a056402004e00b005435dd90a72mr5876483edu.1.1700061236931; Wed, 15 Nov 2023 07:13:56 -0800 (PST) MIME-Version: 1.0 From: Uros Bizjak Date: Wed, 15 Nov 2023 16:13:45 +0100 Message-ID: Subject: [committed] i386: Fix strict_low_part QImode insn with high input register patterns [PR112540] To: "gcc-patches@gcc.gnu.org" X-Spam-Status: No, score=-8.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org PR target/112540 gcc/ChangeLog: * config/i386/i386.md (*addqi_ext_1_slp): Correct operand numbers in split pattern. Replace !Q constraint of operand 1 with !qm. Add insn constrain. (*subqi_ext_1_slp): Ditto. (*qi_ext_1_slp): Ditto. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Uros. diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 6136e46b1bc..29ec9425200 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -6624,9 +6624,9 @@ (define_insn_and_split "*addqi_ext_1_slp" [(match_operand 2 "int248_register_operand" "Q,Q") (const_int 8) (const_int 8)]) 0) - (match_operand:QI 1 "nonimmediate_operand" "0,!Q"))) + (match_operand:QI 1 "nonimmediate_operand" "0,!qm"))) (clobber (reg:CC FLAGS_REG))] - "" + "!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)" "@ add{b}\t{%h2, %0|%0, %h2} #" @@ -6638,8 +6638,8 @@ (define_insn_and_split "*addqi_ext_1_slp" (plus:QI (subreg:QI (match_op_dup 3 - [(match_dup 0) (const_int 8) (const_int 8)]) 0) - (match_dup 1))) + [(match_dup 2) (const_int 8) (const_int 8)]) 0) + (match_dup 0))) (clobber (reg:CC FLAGS_REG))])] "" [(set_attr "type" "alu") @@ -7662,14 +7662,14 @@ (define_insn_and_split "*sub_1_slp" (define_insn_and_split "*subqi_ext_1_slp" [(set (strict_low_part (match_operand:QI 0 "register_operand" "+Q,&Q")) (minus:QI - (match_operand:QI 1 "nonimmediate_operand" "0,!Q") + (match_operand:QI 1 "nonimmediate_operand" "0,!qm") (subreg:QI (match_operator:SWI248 3 "extract_operator" [(match_operand 2 "int248_register_operand" "Q,Q") (const_int 8) (const_int 8)]) 0))) (clobber (reg:CC FLAGS_REG))] - "" + "!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)" "@ sub{b}\t{%h2, %0|%0, %h2} #" @@ -7679,10 +7679,10 @@ (define_insn_and_split "*subqi_ext_1_slp" (parallel [(set (strict_low_part (match_dup 0)) (minus:QI - (match_dup 1) + (match_dup 0) (subreg:QI (match_op_dup 3 - [(match_dup 0) (const_int 8) (const_int 8)]) 0))) + [(match_dup 2) (const_int 8) (const_int 8)]) 0))) (clobber (reg:CC FLAGS_REG))])] "" [(set_attr "type" "alu") @@ -11492,9 +11492,9 @@ (define_insn_and_split "*qi_ext_1_slp" [(match_operand 2 "int248_register_operand" "Q,Q") (const_int 8) (const_int 8)]) 0) - (match_operand:QI 1 "nonimmediate_operand" "0,!Q"))) + (match_operand:QI 1 "nonimmediate_operand" "0,!qm"))) (clobber (reg:CC FLAGS_REG))] - "" + "!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)" "@ {b}\t{%h2, %0|%0, %h2} #" @@ -11504,10 +11504,10 @@ (define_insn_and_split "*qi_ext_1_slp" (parallel [(set (strict_low_part (match_dup 0)) (any_logic:QI - (match_dup 1) (subreg:QI (match_op_dup 3 - [(match_dup 0) (const_int 8) (const_int 8)]) 0))) + [(match_dup 2) (const_int 8) (const_int 8)]) 0))) + (match_dup 0) (clobber (reg:CC FLAGS_REG))])] "" [(set_attr "type" "alu")