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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699630556; x=1700235356; h=to:subject:message-id:date:from:mime-version:x-gm-message-state :from:to:cc:subject:date:message-id:reply-to; bh=o98TDK/EG4cFmUNnju4OCErylCvpjrnrP/1ElxxpoMs=; b=EUHtQ0bUQv7Ui1e/JEOC7VlvE/O4sigCmk3jSNcSH0U7rMA+13PKY3m1pREZkwYNIA AXNrlt2mZTcQUyUKjOxRDVwnL5UxKs78fpNyMG7GQ2CVPFr+BF0QQCaHIDQdrRckkE4M /TE+LqwwArWxUAA79I/PYk25PZbCr2ZQEjROwVeGN3HwiLXej7FkB2SoZWHqdSvMcuyV 0HOwqIwSpkfIovpuaht9SwxpoSVtaVwo0q4xMDZJlV+fSSUJnGVGs8cdbmhUOx7r0YEW QBSFzcmNQnm0zsBzx/aLFdUbJt+Tyn0v5PtY8DbYkef8Tt+Wl6YdXWt12XrUJct6dSp7 zcSg== X-Gm-Message-State: AOJu0YzrQVGuMkidsI5QkPBo7oAs3IjgC+vWt2Xm8ahXjR/K2x0CAEbU uEdktr47V3w+PF73+oSlNV5Lk6G/WHWsPq7xKHVKM8CIh2+3hQ== X-Google-Smtp-Source: AGHT+IEav5uxsZne/2i48HHrglB1p6tm4dEfxTxs7fdmOAUP66+n2uHdKDkxJpltiTcOxdSVpuSV7kcl6gLdx3lModg= X-Received: by 2002:a50:f685:0:b0:544:a153:cd19 with SMTP id d5-20020a50f685000000b00544a153cd19mr5632200edn.41.1699630555967; Fri, 10 Nov 2023 07:35:55 -0800 (PST) MIME-Version: 1.0 From: Uros Bizjak Date: Fri, 10 Nov 2023 16:35:44 +0100 Message-ID: Subject: [committed] i386: Clear stack protector scratch with zero/sign-extend instruction To: "gcc-patches@gcc.gnu.org" X-Spam-Status: No, score=-8.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Use unrelated register initializations using zero/sign-extend instructions to clear stack protector scratch register. Handle only SI -> DImode extensions for 64-bit targets, as this is the only extension that triggers the peephole in a non-negligible number. Also use explicit check for word_mode instead of mode iterator in peephole2 patterns to avoid pattern explosion. gcc/ChangeLog: * config/i386/i386.md (stack_protect_set_1 peephole2): Explicitly check operand 2 for word_mode. (stack_protect_set_1 peephole2 #2): Ditto. (stack_protect_set_2 peephole2): Ditto. (stack_protect_set_3 peephole2): Ditto. (*stack_protect_set_4z__di): New insn pattern. (*stack_protect_set_4s__di): Ditto. (stack_protect_set_4 peephole2): New peephole2 pattern to substitute stack protector scratch register clear with unrelated register initialization involving zero/sign-extend instruction. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Uros. diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 046b6b7919e..01fc6ecc351 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -24335,11 +24335,12 @@ (define_peephole2 [(parallel [(set (match_operand:PTR 0 "memory_operand") (unspec:PTR [(match_operand:PTR 1 "memory_operand")] UNSPEC_SP_SET)) - (set (match_operand:W 2 "general_reg_operand") (const_int 0)) + (set (match_operand 2 "general_reg_operand") (const_int 0)) (clobber (reg:CC FLAGS_REG))]) (set (match_operand 3 "general_reg_operand") (match_operand 4 "const0_operand"))] - "GET_MODE_SIZE (GET_MODE (operands[3])) <= UNITS_PER_WORD + "GET_MODE (operands[2]) == word_mode + && GET_MODE_SIZE (GET_MODE (operands[3])) <= UNITS_PER_WORD && peep2_reg_dead_p (0, operands[3]) && peep2_reg_dead_p (1, operands[2])" [(parallel [(set (match_dup 0) @@ -24395,11 +24396,12 @@ (define_peephole2 [(parallel [(set (match_operand:PTR 0 "memory_operand") (unspec:PTR [(match_operand:PTR 1 "memory_operand")] UNSPEC_SP_SET)) - (set (match_operand:W 2 "general_reg_operand") (const_int 0)) + (set (match_operand 2 "general_reg_operand") (const_int 0)) (clobber (reg:CC FLAGS_REG))]) (set (match_operand:SWI48 3 "general_reg_operand") (match_operand:SWI48 4 "general_gr_operand"))] - "peep2_reg_dead_p (0, operands[3]) + "GET_MODE (operands[2]) == word_mode + && peep2_reg_dead_p (0, operands[3]) && peep2_reg_dead_p (1, operands[2])" [(parallel [(set (match_dup 0) (unspec:PTR [(match_dup 1)] UNSPEC_SP_SET)) @@ -24411,9 +24413,10 @@ (define_peephole2 (parallel [(set (match_operand:PTR 0 "memory_operand") (unspec:PTR [(match_operand:PTR 1 "memory_operand")] UNSPEC_SP_SET)) - (set (match_operand:W 2 "general_reg_operand") (const_int 0)) + (set (match_operand 2 "general_reg_operand") (const_int 0)) (clobber (reg:CC FLAGS_REG))])] - "peep2_reg_dead_p (0, operands[3]) + "GET_MODE (operands[2]) == word_mode + && peep2_reg_dead_p (0, operands[3]) && peep2_reg_dead_p (2, operands[2]) && !reg_mentioned_p (operands[3], operands[0]) && !reg_mentioned_p (operands[3], operands[1])" @@ -24448,16 +24451,71 @@ (define_peephole2 [(parallel [(set (match_operand:PTR 0 "memory_operand") (unspec:PTR [(match_operand:PTR 1 "memory_operand")] UNSPEC_SP_SET)) - (set (match_operand:W 2 "general_reg_operand") (const_int 0)) + (set (match_operand 2 "general_reg_operand") (const_int 0)) (clobber (reg:CC FLAGS_REG))]) (set (match_operand:SWI48 3 "general_reg_operand") (match_operand:SWI48 4 "address_no_seg_operand"))] - "peep2_reg_dead_p (0, operands[3]) + "GET_MODE (operands[2]) == word_mode + && peep2_reg_dead_p (0, operands[3]) && peep2_reg_dead_p (1, operands[2])" [(parallel [(set (match_dup 0) (unspec:PTR [(match_dup 1)] UNSPEC_SP_SET)) (set (match_dup 3) (match_dup 4))])]) +(define_insn "*stack_protect_set_4z__di" + [(set (match_operand:PTR 0 "memory_operand" "=m") + (unspec:PTR [(match_operand:PTR 3 "memory_operand" "m")] + UNSPEC_SP_SET)) + (set (match_operand:DI 1 "register_operand" "=&r") + (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm")))] + "TARGET_64BIT && reload_completed" +{ + output_asm_insn ("mov{}\t{%3, %1|%1, %3}", operands); + output_asm_insn ("mov{}\t{%1, %0|%0, %1}", operands); + if (ix86_use_lea_for_mov (insn, operands + 1)) + return "lea{l}\t{%E2, %k1|%k1, %E2}"; + else + return "mov{l}\t{%2, %k1|%k1, %2}"; +} + [(set_attr "type" "multi") + (set_attr "length" "24")]) + +(define_insn "*stack_protect_set_4s__di" + [(set (match_operand:PTR 0 "memory_operand" "=m,m") + (unspec:PTR [(match_operand:PTR 3 "memory_operand" "m,m")] + UNSPEC_SP_SET)) + (set (match_operand:DI 1 "register_operand" "=&a,&r") + (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "0,rm")))] + "TARGET_64BIT && reload_completed" +{ + output_asm_insn ("mov{}\t{%3, %1|%1, %3}", operands); + output_asm_insn ("mov{}\t{%1, %0|%0, %1}", operands); + if (which_alternative) + return "movs{lq|x}\t{%2, %1|%1, %2}"; + else + return "{cltq|cdqe}"; +} + [(set_attr "type" "multi") + (set_attr "length" "24")]) + +(define_peephole2 + [(parallel [(set (match_operand:PTR 0 "memory_operand") + (unspec:PTR [(match_operand:PTR 1 "memory_operand")] + UNSPEC_SP_SET)) + (set (match_operand 2 "general_reg_operand") (const_int 0)) + (clobber (reg:CC FLAGS_REG))]) + (set (match_operand:DI 3 "general_reg_operand") + (any_extend:DI + (match_operand:SI 4 "nonimmediate_gr_operand")))] + "TARGET_64BIT + && GET_MODE (operands[2]) == word_mode + && peep2_reg_dead_p (0, operands[3]) + && peep2_reg_dead_p (1, operands[2])" + [(parallel [(set (match_dup 0) + (unspec:PTR [(match_dup 1)] UNSPEC_SP_SET)) + (set (match_dup 3) + (any_extend:DI (match_dup 4)))])]) + (define_expand "stack_protect_test" [(match_operand 0 "memory_operand") (match_operand 1 "memory_operand")