From patchwork Mon Nov 6 13:27:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Adhemerval Zanella Netto X-Patchwork-Id: 1860155 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=S7kVDzyB; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=sourceware.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=libc-alpha-bounces+incoming=patchwork.ozlabs.org@sourceware.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SPBwk0B6Yz1yQL for ; Tue, 7 Nov 2023 00:27:33 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 4D6323856DDF for ; Mon, 6 Nov 2023 13:27:30 +0000 (GMT) X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from mail-vk1-xa33.google.com (mail-vk1-xa33.google.com [IPv6:2607:f8b0:4864:20::a33]) by sourceware.org (Postfix) with ESMTPS id 50C5A3858D33 for ; Mon, 6 Nov 2023 13:27:20 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 50C5A3858D33 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linaro.org ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 50C5A3858D33 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::a33 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699277241; cv=none; b=bgkcvils2Nudg77xZDaophXA8XCHf5PmlurAVQRREXsIvd2PZtB4IVtJ3mfEaPlq03eCxj5N4chFpnKJkWAhNylkqxaDrVCPQdGH0jCmzRuhZ+Ei2sIYtUJSKs4a9K+C2MvYsgHq4Xjzci7IDGXgEHNsGffJ5o5fZynPOs4QdSI= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699277241; c=relaxed/simple; bh=BoHvN498rhA/tBAAwfSg43+0rL0NtgPiLxrEzE2+mgk=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=eBdWej3KqMymIOtuh6Ea3waDREZJJbMPkIUDaIDxinL+ePgeggb8MEA7Nml2WGsIxtAmz4Uzo+hJuFPhDCtEBDHwb0f/chEiM38ZfuwJJod/6OovfpfaXLDJHGcTH5A1Yvjk0cd4GY5L0zmbLxt4oEJX5AUKFNNausaRoOnkWhg= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-vk1-xa33.google.com with SMTP id 71dfb90a1353d-4a18f724d47so1397256e0c.3 for ; Mon, 06 Nov 2023 05:27:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699277239; x=1699882039; darn=sourceware.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=NOvdAysXA05qPpMnEVH8JkFq4y3flQAfl9BCWlDaPAI=; b=S7kVDzyBZwkKG3XCrk9FPbmwZTARuihweLzhJfeznNwAE8a0uGlD/Ll1r4BoJ61r2y dy/MlVHk1rbP7ILYX3fyWFkxS62rbw8kr0AcV2+ind5Cm+wW/qvpoi7hjhT1560ZVbxG h3B/t4GkJeXR2o+DgvT9aRpbo6bWZ9G6f5giYo4PmapJhxT7AzdvvOBb0u273KUaCplK WOqYApfcgwgoykQNhRdXHpbTgTqmwAaVshJbQPl1M7AXL4DlA/lDMMBcHiz6hejwYcpJ oTXSclQeMJBz4YQTTHq6Ie4a53HThp50W3frZF85FtaFxUtPbehIFw3AggIDncbDKXuw 5x/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699277239; x=1699882039; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NOvdAysXA05qPpMnEVH8JkFq4y3flQAfl9BCWlDaPAI=; b=Tg6ITE/V9+ndUmY2Ka28VA8J22uVJmu8DUy2eNXJEf0uAb07o78ywUjQ3RGYR6oxwZ DLkRvuqwM6fH/7j2mi5rvoQVQFqnfbxo/3xrcYIj7IO01kOl7d5WYy+lWgQVjCNDiDAU FNJYkn9f4C5W08L3odVKesGVQF7uB811uJAF/xPG/OP1d4N9ZRS7FQHePfaRcmKiFTCL 9WHWQXPi5xdQ5GoY4u1Wgqbyxb88yv3HtOM9AhRwuDB6ZD+XDIgB8yk3pZB9QvzIgZaY DCp/cMFUleZbnostmxFnP0ocR8y47t5HrMsQEWtFt2QtWJhV7XVI4shOumynyYy9G0qL rMDw== X-Gm-Message-State: AOJu0YwtDANd6TBFHT887UbBznIOJLmgPEmI8nyM4BoEgqC5tEad61jU sSem8Z10limTZwqCQyCcuDhi9hJzc1hgN+Gw23hXHQ== X-Google-Smtp-Source: AGHT+IEzLaS7kYPtb96Hh386I7iqdIDvtbgI7jnnBM/ubP9KvkvEQbmv4GNsiq8G+RwWN2HvgX1R1Q== X-Received: by 2002:a1f:9d04:0:b0:4ac:6a9d:c49b with SMTP id g4-20020a1f9d04000000b004ac6a9dc49bmr701679vke.14.1699277238884; Mon, 06 Nov 2023 05:27:18 -0800 (PST) Received: from mandiga.. ([2804:1b3:a7c0:a715:c1a0:7281:6384:2ee9]) by smtp.gmail.com with ESMTPSA id k3-20020a05620a142300b0076f12fcb0easm3272722qkj.2.2023.11.06.05.27.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Nov 2023 05:27:18 -0800 (PST) From: Adhemerval Zanella To: libc-alpha@sourceware.org, Bruno Haible Subject: [PATCH v2 1/7] powerpc: Do not raise exception traps for fesetexcept/fesetexceptflag (BZ 30988) Date: Mon, 6 Nov 2023 10:27:07 -0300 Message-Id: <20231106132713.953501-2-adhemerval.zanella@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231106132713.953501-1-adhemerval.zanella@linaro.org> References: <20231106132713.953501-1-adhemerval.zanella@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: libc-alpha-bounces+incoming=patchwork.ozlabs.org@sourceware.org According to ISO C23 (7.6.4.4), fesetexcept is supposed to set floating-point exception flags without raising a trap (unlike feraiseexcept, which is supposed to raise a trap if feenableexcept was called with the appropriate argument). This is a side-effect of how we implement the GNU extension feenableexcept, where feenableexcept/fesetenv/fesetmode/feupdateenv might issue prctl (PR_SET_FPEXC, PR_FP_EXC_PRECISE) depending of the argument. And on PR_FP_EXC_PRECISE, setting a floating-point exception flag triggers a trap. To make the both functions follow the C23, fesetexcept and fesetexceptflag now fail if the argument may trigger a trap. The math tests now check for an value different than 0, instead of bail out as unsupported for EXCEPTION_SET_FORCES_TRAP. Checked on powerpc64le-linux-gnu. Reviewed-by: Carlos O'Donell --- math/test-fesetexcept-traps.c | 11 ++++------- math/test-fexcept-traps.c | 11 ++++------- sysdeps/powerpc/fpu/fesetexcept.c | 5 +++++ sysdeps/powerpc/fpu/fsetexcptflg.c | 9 ++++++++- 4 files changed, 21 insertions(+), 15 deletions(-) diff --git a/math/test-fesetexcept-traps.c b/math/test-fesetexcept-traps.c index 71b6e45b33..96f6c4752f 100644 --- a/math/test-fesetexcept-traps.c +++ b/math/test-fesetexcept-traps.c @@ -39,16 +39,13 @@ do_test (void) return result; } - if (EXCEPTION_SET_FORCES_TRAP) - { - puts ("setting exceptions traps, cannot test on this architecture"); - return 77; - } - /* Verify fesetexcept does not cause exception traps. */ + /* Verify fesetexcept does not cause exception traps. For architectures + where setting the exception might result in traps the function should + return a nonzero value. */ ret = fesetexcept (FE_ALL_EXCEPT); if (ret == 0) puts ("fesetexcept (FE_ALL_EXCEPT) succeeded"); - else + else if (!EXCEPTION_SET_FORCES_TRAP) { puts ("fesetexcept (FE_ALL_EXCEPT) failed"); if (EXCEPTION_TESTS (float)) diff --git a/math/test-fexcept-traps.c b/math/test-fexcept-traps.c index 9701c3c320..9b8f583ae6 100644 --- a/math/test-fexcept-traps.c +++ b/math/test-fexcept-traps.c @@ -63,14 +63,11 @@ do_test (void) result = 1; } - if (EXCEPTION_SET_FORCES_TRAP) - { - puts ("setting exceptions traps, cannot test on this architecture"); - return 77; - } - /* The test is that this does not cause exception traps. */ + /* The test is that this does not cause exception traps. For architectures + where setting the exception might result in traps the function should + return a nonzero value. */ ret = fesetexceptflag (&saved, FE_ALL_EXCEPT); - if (ret != 0) + if (ret != 0 && !EXCEPTION_SET_FORCES_TRAP) { puts ("fesetexceptflag failed"); result = 1; diff --git a/sysdeps/powerpc/fpu/fesetexcept.c b/sysdeps/powerpc/fpu/fesetexcept.c index 609a148a95..2850156d3a 100644 --- a/sysdeps/powerpc/fpu/fesetexcept.c +++ b/sysdeps/powerpc/fpu/fesetexcept.c @@ -31,6 +31,11 @@ fesetexcept (int excepts) & FE_INVALID_SOFTWARE)); if (n.l != u.l) { + if (n.l & fenv_exceptions_to_reg (excepts)) + /* Setting the exception flags may trigger a trap. ISO C 23 § 7.6.4.4 + does not allow it. */ + return -1; + fesetenv_register (n.fenv); /* Deal with FE_INVALID_SOFTWARE not being implemented on some chips. */ diff --git a/sysdeps/powerpc/fpu/fsetexcptflg.c b/sysdeps/powerpc/fpu/fsetexcptflg.c index 2b22f913c0..6517e8ea03 100644 --- a/sysdeps/powerpc/fpu/fsetexcptflg.c +++ b/sysdeps/powerpc/fpu/fsetexcptflg.c @@ -44,7 +44,14 @@ __fesetexceptflag (const fexcept_t *flagp, int excepts) This may cause floating-point exceptions if the restored state requests it. */ if (n.l != u.l) - fesetenv_register (n.fenv); + { + if (n.l & fenv_exceptions_to_reg (excepts)) + /* Setting the exception flags may trigger a trap. ISO C 23 § 7.6.4.4 + does not allow it. */ + return -1; + + fesetenv_register (n.fenv); + } /* Deal with FE_INVALID_SOFTWARE not being implemented on some chips. */ if (flag & FE_INVALID) From patchwork Mon Nov 6 13:27:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adhemerval Zanella Netto X-Patchwork-Id: 1860156 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=TZ3WPlrx; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=sourceware.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=libc-alpha-bounces+incoming=patchwork.ozlabs.org@sourceware.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SPBwk5w6yz1yQY for ; Tue, 7 Nov 2023 00:27:34 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id B63C53856251 for ; Mon, 6 Nov 2023 13:27:32 +0000 (GMT) X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from mail-qk1-x72b.google.com (mail-qk1-x72b.google.com [IPv6:2607:f8b0:4864:20::72b]) by sourceware.org (Postfix) with ESMTPS id E19C23858C74 for ; Mon, 6 Nov 2023 13:27:21 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org E19C23858C74 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linaro.org ARC-Filter: OpenARC Filter v1.0.0 sourceware.org E19C23858C74 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::72b ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699277243; cv=none; b=EEvEuxJ76pKvAhSQwtuWkaAuvx4+uNSNSA3LHzb3juUrqrHrRLd8dgIe2Xrxl/0MWKSMNXBLubIxh/d+2yjudZgcJvpkaU1mJxIYY6D0SZlAREStPmZsThrLVyLL92i+gvBRLq0YKQQ2l64E4vu1cEGpJUrQvYyziEfyc16CILg= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699277243; c=relaxed/simple; bh=7mPoHnwYiGVBHfD5WnJOfbkhucyqlQLImZn965fw2Y0=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=IW8oPFHIuKlLajGXKbzlLOsivU0dctuvSgNfDsNVj4ccqMUG86OEccIzOJSaSmbLuohdYyfL8GUUUc00tLwwoU+ZyUVaUZ2Wg5DVS3b2uhd3Qtfrge4vw7BeDtN2TiC0LYjg3wzoU7n5GOa9O5VxLtCCtER16AfWZqV0T1rsVb4= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-qk1-x72b.google.com with SMTP id af79cd13be357-7789cb322deso289902485a.3 for ; Mon, 06 Nov 2023 05:27:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699277240; x=1699882040; darn=sourceware.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=DU7GVADg99Hwk54vw+9Jf7Krbt2jfsYfpsChaj/RuNI=; b=TZ3WPlrxG3EA2j4yYmVGqs1r4iY7/xP672Gwpuhffj3rBpcsQWTjrt15jf7UgIwM29 3OtyK3pOyGPhWWoyth6Z5GJ42VZ+XwTdTRheijwhpmxcpRq2RU9kc8U0ZfAJyg0YveNI 8jbTFnqcffnDbVlmcKlAKHSVzB9ufkRaCdNCRjqj/qlWYry/KsjqIVSuPpzhMmE1znVg 7+mjapDHeQgdErAbW92R4dnkychv5S6THWdYbrreXs46taHyZh1vHy7o++vNeqF+DDvO uiZOqk3qOwxWf8CmR+VT2kq6Urk9LOqPRRSS0JSOAFVfjhYs7VznJLz0mUPRZTq8czp5 8xAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699277240; x=1699882040; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DU7GVADg99Hwk54vw+9Jf7Krbt2jfsYfpsChaj/RuNI=; b=GTmp++BhtC6SlY0QMOZMjSb9/89qWyU9GuQ64Ee+b5mHFZc13O+IM2c6YpM5P0+/s8 zEUFAuGOB449ByqQMp5M9/UAozmwzO6W0SknEfzAJ14U3c5nMT+yiIBab7yqweGOsmor I53Otls6DNR4qwyz+JNNnSZrCbSTXKyzTQChhzQ+EZ3GbZkZIUqptUJOwLBgd+di7IwV dMEBnSsHSDVmChUktaT8tNCKbJx9+jX0YMh86XVvq602WizeEMHDXBLxp+lhyOCRA98v 6ZtwMVo2J5LyUAbm/El0SR16kT0/k0uwrzF6Xjkr6sT9uOHwL5+97pdRICAEntjqm3iD 92jA== X-Gm-Message-State: AOJu0YwE6mUlGl7dBLLi+kHi8n6MkR4zelrABjAsuMJmlIRo1Von6BeK N19bm5K8jEYjja1C/noSh0FPG8afpw1lUnE8odUzhg== X-Google-Smtp-Source: AGHT+IGs6INmxsXqDaPAjusf8LIA+m+dK9jHcrE5QQl8vugWDXirzabbgvQZGTopTS+vWY+I4DWn4Q== X-Received: by 2002:a05:620a:2697:b0:77a:4606:7541 with SMTP id c23-20020a05620a269700b0077a46067541mr18079113qkp.56.1699277240473; Mon, 06 Nov 2023 05:27:20 -0800 (PST) Received: from mandiga.. ([2804:1b3:a7c0:a715:c1a0:7281:6384:2ee9]) by smtp.gmail.com with ESMTPSA id k3-20020a05620a142300b0076f12fcb0easm3272722qkj.2.2023.11.06.05.27.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Nov 2023 05:27:19 -0800 (PST) From: Adhemerval Zanella To: libc-alpha@sourceware.org, Bruno Haible Subject: [PATCH v2 2/7] i686: Do not raise exception traps on fesetexcept (BZ 30989) Date: Mon, 6 Nov 2023 10:27:08 -0300 Message-Id: <20231106132713.953501-3-adhemerval.zanella@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231106132713.953501-1-adhemerval.zanella@linaro.org> References: <20231106132713.953501-1-adhemerval.zanella@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: libc-alpha-bounces+incoming=patchwork.ozlabs.org@sourceware.org According to ISO C23 (7.6.4.4), fesetexcept is supposed to set floating-point exception flags without raising a trap (unlike feraiseexcept, which is supposed to raise a trap if feenableexcept was called with the appropriate argument). The flags can be set in the 387 unit or in the SSE unit. To set a flag, it is sufficient to do it in the SSE unit, because that is guaranteed to not trap. However, on i386 CPUs that have only a 387 unit, set the flags in the 387, as long as this cannot trap. Checked on i686-linux-gnu. Reviewed-by: Carlos O'Donell --- math/test-fesetexcept-traps.c | 28 ++++++++++++--- sysdeps/i386/fpu/fesetexcept.c | 46 +++++++++++++++++++++--- sysdeps/i386/fpu/math-tests-trap-force.h | 29 +++++++++++++++ sysdeps/x86/fpu/test-fenv-sse-2.c | 23 +++--------- 4 files changed, 100 insertions(+), 26 deletions(-) create mode 100644 sysdeps/i386/fpu/math-tests-trap-force.h diff --git a/math/test-fesetexcept-traps.c b/math/test-fesetexcept-traps.c index 96f6c4752f..8a5c0bca80 100644 --- a/math/test-fesetexcept-traps.c +++ b/math/test-fesetexcept-traps.c @@ -19,6 +19,7 @@ #include #include #include +#include static int do_test (void) @@ -41,8 +42,28 @@ do_test (void) /* Verify fesetexcept does not cause exception traps. For architectures where setting the exception might result in traps the function should - return a nonzero value. */ - ret = fesetexcept (FE_ALL_EXCEPT); + return a nonzero value. + Also check if the function does not alter the exception mask. */ + { + int exc_before = fegetexcept (); + ret = fesetexcept (FE_ALL_EXCEPT); + int exc_after = fegetexcept (); + if (exc_before != exc_after) + { + puts ("fesetexcept (FE_ALL_EXCEPT) changed the exceptions mask"); + return 1; + } + } + + /* Execute some floating-point operations, since on some CPUs exceptions + triggers a trap only at the next floating-point instruction. */ + volatile double a = 1.0; + volatile double b = a + a; + math_force_eval (b); + volatile long double al = 1.0L; + volatile long double bl = al + al; + math_force_eval (bl); + if (ret == 0) puts ("fesetexcept (FE_ALL_EXCEPT) succeeded"); else if (!EXCEPTION_SET_FORCES_TRAP) @@ -61,5 +82,4 @@ do_test (void) return result; } -#define TEST_FUNCTION do_test () -#include "../test-skeleton.c" +#include diff --git a/sysdeps/i386/fpu/fesetexcept.c b/sysdeps/i386/fpu/fesetexcept.c index 18949e982a..58f577d93d 100644 --- a/sysdeps/i386/fpu/fesetexcept.c +++ b/sysdeps/i386/fpu/fesetexcept.c @@ -17,15 +17,53 @@ . */ #include +#include int fesetexcept (int excepts) { - fenv_t temp; + /* The flags can be set in the 387 unit or in the SSE unit. To set a flag, + it is sufficient to do it in the SSE unit, because that is guaranteed to + not trap. However, on i386 CPUs that have only a 387 unit, set the flags + in the 387, as long as this cannot trap. */ - __asm__ ("fnstenv %0" : "=m" (*&temp)); - temp.__status_word |= excepts & FE_ALL_EXCEPT; - __asm__ ("fldenv %0" : : "m" (*&temp)); + excepts &= FE_ALL_EXCEPT; + + if (CPU_FEATURE_USABLE (SSE)) + { + /* Get the control word of the SSE unit. */ + unsigned int mxcsr; + __asm__ ("stmxcsr %0" : "=m" (*&mxcsr)); + + /* Set relevant flags. */ + mxcsr |= excepts; + + /* Put the new data in effect. */ + __asm__ ("ldmxcsr %0" : : "m" (*&mxcsr)); + } + else + { + fenv_t temp; + + /* Note: fnstenv masks all floating-point exceptions until the fldenv + or fldcw below. */ + __asm__ ("fnstenv %0" : "=m" (*&temp)); + + /* Set relevant flags. */ + temp.__status_word |= excepts; + + if ((~temp.__control_word) & excepts) + { + /* Setting the exception flags may trigger a trap (at the next + floating-point instruction, but that does not matter). + ISO C23 (7.6.4.4) does not allow it. */ + __asm__ volatile ("fldcw %0" : : "m" (*&temp.__control_word)); + return -1; + } + + /* Store the new status word (along with the rest of the environment). */ + __asm__ ("fldenv %0" : : "m" (*&temp)); + } return 0; } diff --git a/sysdeps/i386/fpu/math-tests-trap-force.h b/sysdeps/i386/fpu/math-tests-trap-force.h new file mode 100644 index 0000000000..f41e1ffc2d --- /dev/null +++ b/sysdeps/i386/fpu/math-tests-trap-force.h @@ -0,0 +1,29 @@ +/* Configuration for math tests: support for setting exception flags + without causing enabled traps. i686 version. + Copyright (C) 2023 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#ifndef I386_FPU_MATH_TESTS_TRAP_FORCE_H +#define I386_FPU_MATH_TESTS_TRAP_FORCE_H 1 + +#include + +/* Setting exception flags in FPU Status Register results in enabled traps for + those exceptions being taken. */ +#define EXCEPTION_SET_FORCES_TRAP !CPU_FEATURE_USABLE (SSE) + +#endif /* math-tests-trap-force.h. */ diff --git a/sysdeps/x86/fpu/test-fenv-sse-2.c b/sysdeps/x86/fpu/test-fenv-sse-2.c index f3e820b6ed..7a0503790f 100644 --- a/sysdeps/x86/fpu/test-fenv-sse-2.c +++ b/sysdeps/x86/fpu/test-fenv-sse-2.c @@ -22,17 +22,8 @@ #include #include #include - -static bool -have_sse2 (void) -{ - unsigned int eax, ebx, ecx, edx; - - if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx)) - return false; - - return (edx & bit_SSE2) != 0; -} +#include +#include static uint32_t get_sse_mxcsr (void) @@ -164,13 +155,9 @@ sse_tests (void) static int do_test (void) { - if (!have_sse2 ()) - { - puts ("CPU does not support SSE2, cannot test"); - return 0; - } + if (!CPU_FEATURE_USABLE (SSE2)) + FAIL_UNSUPPORTED ("CPU does not support SSE2"); return sse_tests (); } -#define TEST_FUNCTION do_test () -#include +#include From patchwork Mon Nov 6 13:27:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Adhemerval Zanella Netto X-Patchwork-Id: 1860158 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=VxFuMLfb; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=sourceware.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=libc-alpha-bounces+incoming=patchwork.ozlabs.org@sourceware.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SPBxC3vlkz1yQY for ; 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([2804:1b3:a7c0:a715:c1a0:7281:6384:2ee9]) by smtp.gmail.com with ESMTPSA id k3-20020a05620a142300b0076f12fcb0easm3272722qkj.2.2023.11.06.05.27.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Nov 2023 05:27:22 -0800 (PST) From: Adhemerval Zanella To: libc-alpha@sourceware.org, Bruno Haible Subject: [PATCH v2 3/7] x86: Do not raises floating-point exception traps on fesetexceptflag (BZ 30990) Date: Mon, 6 Nov 2023 10:27:09 -0300 Message-Id: <20231106132713.953501-4-adhemerval.zanella@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231106132713.953501-1-adhemerval.zanella@linaro.org> References: <20231106132713.953501-1-adhemerval.zanella@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: libc-alpha-bounces+incoming=patchwork.ozlabs.org@sourceware.org From: Bruno Haible According to ISO C23 (7.6.4.4), fesetexcept is supposed to set floating-point exception flags without raising a trap (unlike feraiseexcept, which is supposed to raise a trap if feenableexcept was called with the appropriate argument). The flags can be set in the 387 unit or in the SSE unit. When we need to clear a flag, we need to do so in both units, due to the way fetestexcept is implemented. When we need to set a flag, it is sufficient to do it in the SSE unit, because that is guaranteed to not trap. However, on i386 CPUs that have only a 387 unit, set the flags in the 387, as long as this cannot trap. Co-authored-by: Adhemerval Zanella Reviewed-by: Carlos O'Donell --- math/test-fexcept-traps.c | 25 +++++++++++- sysdeps/i386/fpu/fsetexcptflg.c | 63 ++++++++++++++++++++----------- sysdeps/x86_64/fpu/fsetexcptflg.c | 24 +++++++----- 3 files changed, 79 insertions(+), 33 deletions(-) diff --git a/math/test-fexcept-traps.c b/math/test-fexcept-traps.c index 9b8f583ae6..6bfb5124da 100644 --- a/math/test-fexcept-traps.c +++ b/math/test-fexcept-traps.c @@ -19,6 +19,7 @@ #include #include #include +#include static int do_test (void) @@ -65,8 +66,28 @@ do_test (void) /* The test is that this does not cause exception traps. For architectures where setting the exception might result in traps the function should - return a nonzero value. */ - ret = fesetexceptflag (&saved, FE_ALL_EXCEPT); + return a nonzero value. + Also check if the function does not alter the exception mask. */ + { + int exc_before = fegetexcept (); + ret = fesetexceptflag (&saved, FE_ALL_EXCEPT); + int exc_after = fegetexcept (); + if (exc_before != exc_after) + { + puts ("fesetexceptflag (FE_ALL_EXCEPT) changed the exceptions mask"); + return 1; + } + } + + /* Execute some floating-point operations, since on some CPUs exceptions + triggers a trap only at the next floating-point instruction. */ + volatile double a = 1.0; + volatile double b = a + a; + math_force_eval (b); + volatile long double al = 1.0L; + volatile long double bl = al + al; + math_force_eval (bl); + if (ret != 0 && !EXCEPTION_SET_FORCES_TRAP) { puts ("fesetexceptflag failed"); diff --git a/sysdeps/i386/fpu/fsetexcptflg.c b/sysdeps/i386/fpu/fsetexcptflg.c index e724b7d6fd..480165cff9 100644 --- a/sysdeps/i386/fpu/fsetexcptflg.c +++ b/sysdeps/i386/fpu/fsetexcptflg.c @@ -17,42 +17,63 @@ . */ #include -#include -#include #include -#include int __fesetexceptflag (const fexcept_t *flagp, int excepts) { - fenv_t temp; + /* The flags can be set in the 387 unit or in the SSE unit. When we need to + clear a flag, we need to do so in both units, due to the way fetestexcept + is implemented. + When we need to set a flag, it is sufficient to do it in the SSE unit, + because that is guaranteed to not trap. However, on i386 CPUs that have + only a 387 unit, set the flags in the 387, as long as this cannot trap. */ - /* Get the current environment. We have to do this since we cannot - separately set the status word. */ - __asm__ ("fnstenv %0" : "=m" (*&temp)); + fenv_t temp; - temp.__status_word &= ~(excepts & FE_ALL_EXCEPT); - temp.__status_word |= *flagp & excepts & FE_ALL_EXCEPT; + excepts &= FE_ALL_EXCEPT; - /* Store the new status word (along with the rest of the environment. - Possibly new exceptions are set but they won't get executed unless - the next floating-point instruction. */ - __asm__ ("fldenv %0" : : "m" (*&temp)); + /* Get the current x87 FPU environment. We have to do this since we + cannot separately set the status word. + Note: fnstenv masks all floating-point exceptions until the fldenv + or fldcw below. */ + __asm__ ("fnstenv %0" : "=m" (*&temp)); - /* If the CPU supports SSE, we set the MXCSR as well. */ if (CPU_FEATURE_USABLE (SSE)) { - unsigned int xnew_exc; + unsigned int mxcsr; + + /* Clear relevant flags. */ + temp.__status_word &= ~(excepts & ~ *flagp); - /* Get the current MXCSR. */ - __asm__ ("stmxcsr %0" : "=m" (*&xnew_exc)); + /* Store the new status word (along with the rest of the environment). */ + __asm__ ("fldenv %0" : : "m" (*&temp)); - /* Set the relevant bits. */ - xnew_exc &= ~(excepts & FE_ALL_EXCEPT); - xnew_exc |= *flagp & excepts & FE_ALL_EXCEPT; + /* And now similarly for SSE. */ + __asm__ ("stmxcsr %0" : "=m" (*&mxcsr)); + + /* Clear or set relevant flags. */ + mxcsr ^= (mxcsr ^ *flagp) & excepts; /* Put the new data in effect. */ - __asm__ ("ldmxcsr %0" : : "m" (*&xnew_exc)); + __asm__ ("ldmxcsr %0" : : "m" (*&mxcsr)); + } + else + { + /* Clear or set relevant flags. */ + temp.__status_word ^= (temp.__status_word ^ *flagp) & excepts; + + if ((~temp.__control_word) & temp.__status_word & excepts) + { + /* Setting the exception flags may trigger a trap (at the next + floating-point instruction, but that does not matter). + ISO C 23 § 7.6.4.5 does not allow it. */ + __asm__ volatile ("fldcw %0" : : "m" (*&temp.__control_word)); + return -1; + } + + /* Store the new status word (along with the rest of the environment). */ + __asm__ ("fldenv %0" : : "m" (*&temp)); } /* Success. */ diff --git a/sysdeps/x86_64/fpu/fsetexcptflg.c b/sysdeps/x86_64/fpu/fsetexcptflg.c index a3ac1dea01..2ce2b509f2 100644 --- a/sysdeps/x86_64/fpu/fsetexcptflg.c +++ b/sysdeps/x86_64/fpu/fsetexcptflg.c @@ -22,30 +22,34 @@ int fesetexceptflag (const fexcept_t *flagp, int excepts) { + /* The flags can be set in the 387 unit or in the SSE unit. + When we need to clear a flag, we need to do so in both units, + due to the way fetestexcept() is implemented. + When we need to set a flag, it is sufficient to do it in the SSE unit, + because that is guaranteed to not trap. */ + fenv_t temp; unsigned int mxcsr; - /* XXX: Do we really need to set both the exception in both units? - Shouldn't it be enough to set only the SSE unit? */ + excepts &= FE_ALL_EXCEPT; /* Get the current x87 FPU environment. We have to do this since we cannot separately set the status word. */ __asm__ ("fnstenv %0" : "=m" (*&temp)); - temp.__status_word &= ~(excepts & FE_ALL_EXCEPT); - temp.__status_word |= *flagp & excepts & FE_ALL_EXCEPT; + /* Clear relevant flags. */ + temp.__status_word &= ~(excepts & ~ *flagp); - /* Store the new status word (along with the rest of the environment. - Possibly new exceptions are set but they won't get executed unless - the next floating-point instruction. */ + /* Store the new status word (along with the rest of the environment). */ __asm__ ("fldenv %0" : : "m" (*&temp)); - /* And now the same for SSE. */ + /* And now similarly for SSE. */ __asm__ ("stmxcsr %0" : "=m" (*&mxcsr)); - mxcsr &= ~(excepts & FE_ALL_EXCEPT); - mxcsr |= *flagp & excepts & FE_ALL_EXCEPT; + /* Clear or set relevant flags. */ + mxcsr ^= (mxcsr ^ *flagp) & excepts; + /* Put the new data in effect. */ __asm__ ("ldmxcsr %0" : : "m" (*&mxcsr)); /* Success. */ From patchwork Mon Nov 6 13:27:10 2023 Content-Type: text/plain; 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Reviewed-by: Carlos O'Donell --- manual/arith.texi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/manual/arith.texi b/manual/arith.texi index fa7110e992..be24c20493 100644 --- a/manual/arith.texi +++ b/manual/arith.texi @@ -1176,6 +1176,12 @@ enabled, the status of the other exceptions is not changed. The function returns the previous enabled exceptions in case the operation was successful, @code{-1} otherwise. + +Note: Enabling traps for an exception for which the exception flag is +currently already set (@pxref{Status bit operations}) has unspecified +consequences: it may or may not trigger a trap immediately. +@c It triggers a trap immediately on powerpc*, at the next floating- +@c instruction on i386, and not at all on the other CPUs. @end deftypefun @deftypefun int fedisableexcept (int @var{excepts}) From patchwork Mon Nov 6 13:27:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adhemerval Zanella Netto X-Patchwork-Id: 1860159 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=LRzOLYVk; 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([2804:1b3:a7c0:a715:c1a0:7281:6384:2ee9]) by smtp.gmail.com with ESMTPSA id k3-20020a05620a142300b0076f12fcb0easm3272722qkj.2.2023.11.06.05.27.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Nov 2023 05:27:26 -0800 (PST) From: Adhemerval Zanella To: libc-alpha@sourceware.org, Bruno Haible Subject: [PATCH v2 5/7] riscv: Fix feenvupdate with FE_DFL_ENV (BZ 31022) Date: Mon, 6 Nov 2023 10:27:11 -0300 Message-Id: <20231106132713.953501-6-adhemerval.zanella@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231106132713.953501-1-adhemerval.zanella@linaro.org> References: <20231106132713.953501-1-adhemerval.zanella@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: libc-alpha-bounces+incoming=patchwork.ozlabs.org@sourceware.org libc_feupdateenv_riscv should check for FE_DFL_ENV, similar to libc_fesetenv_riscv. Also extend the test-fenv.c to test fenvupdate. Checked on riscv under qemu-system. Reviewed-by: Carlos O'Donell --- math/test-fenv.c | 131 ++++++++++++++++++++++++++++--- sysdeps/riscv/rvf/fenv_private.h | 8 +- 2 files changed, 124 insertions(+), 15 deletions(-) diff --git a/math/test-fenv.c b/math/test-fenv.c index 0af7141ba7..63dceddb10 100644 --- a/math/test-fenv.c +++ b/math/test-fenv.c @@ -196,6 +196,30 @@ set_single_exc (const char *test_name, int fe_exc, fexcept_t exception) feclearexcept (exception); test_exceptions (str, ALL_EXC ^ fe_exc, 0); } + +static void +update_single_exc (const char *test_name, const fenv_t *envp, int fe_exc, + int fe_exc_clear, int exception) +{ + char str[200]; + /* The standard allows the inexact exception to be set together with the + underflow and overflow exceptions. So ignore the inexact flag if the + others are raised. */ + int ignore_inexact = (fe_exc & (UNDERFLOW_EXC | OVERFLOW_EXC)) != 0; + + strcpy (str, test_name); + strcat (str, ": set flag, with rest not set"); + feclearexcept (FE_ALL_EXCEPT); + feraiseexcept (exception); + feupdateenv (envp); + test_exceptions (str, fe_exc, ignore_inexact); + + strcpy (str, test_name); + strcat (str, ": clear flag, rest also unset"); + feclearexcept (exception); + feupdateenv (envp); + test_exceptions (str, fe_exc_clear, ignore_inexact); +} #endif static void @@ -233,22 +257,32 @@ fe_tests (void) } #if FE_ALL_EXCEPT +static const char * +funcname (int (*func)(const fenv_t *)) +{ + if (func == fesetenv) + return "fesetenv"; + else if (func == feupdateenv) + return "feupdateenv"; + __builtin_unreachable (); +} + /* Test that program aborts with no masked interrupts */ static void -feenv_nomask_test (const char *flag_name, int fe_exc) +feenv_nomask_test (const char *flag_name, int fe_exc, int (*func)(const fenv_t *)) { # if defined FE_NOMASK_ENV int status; pid_t pid; if (!EXCEPTION_ENABLE_SUPPORTED (FE_ALL_EXCEPT) - && fesetenv (FE_NOMASK_ENV) != 0) + && func (FE_NOMASK_ENV) != 0) { printf ("Test: not testing FE_NOMASK_ENV, it isn't implemented.\n"); return; } - printf ("Test: after fesetenv (FE_NOMASK_ENV) processes will abort\n"); + printf ("Test: after %s (FE_NOMASK_ENV) processes will abort\n", funcname (func)); printf (" when feraiseexcept (%s) is called.\n", flag_name); pid = fork (); if (pid == 0) @@ -295,12 +329,12 @@ feenv_nomask_test (const char *flag_name, int fe_exc) /* Test that program doesn't abort with default environment */ static void -feenv_mask_test (const char *flag_name, int fe_exc) +feenv_mask_test (const char *flag_name, int fe_exc, int (*func)(const fenv_t *)) { int status; pid_t pid; - printf ("Test: after fesetenv (FE_DFL_ENV) processes will not abort\n"); + printf ("Test: after %s (FE_DFL_ENV) processes will not abort\n", funcname (func)); printf (" when feraiseexcept (%s) is called.\n", flag_name); pid = fork (); if (pid == 0) @@ -313,7 +347,7 @@ feenv_mask_test (const char *flag_name, int fe_exc) setrlimit (RLIMIT_CORE, &core_limit); #endif - fesetenv (FE_DFL_ENV); + func (FE_DFL_ENV); feraiseexcept (fe_exc); exit (2); } @@ -615,10 +649,18 @@ feenable_test (const char *flag_name, int fe_exc) static void fe_single_test (const char *flag_name, int fe_exc) { - feenv_nomask_test (flag_name, fe_exc); - feenv_mask_test (flag_name, fe_exc); + feenv_nomask_test (flag_name, fe_exc, fesetenv); + feenv_mask_test (flag_name, fe_exc, fesetenv); feenable_test (flag_name, fe_exc); } + + +static void +feupdate_single_test (const char *flag_name, int fe_exc) +{ + feenv_nomask_test (flag_name, fe_exc, feupdateenv); + feenv_mask_test (flag_name, fe_exc, feupdateenv); +} #endif @@ -646,6 +688,72 @@ feenv_tests (void) fesetenv (FE_DFL_ENV); } +#if FE_ALL_EXCEPT +static void +feupdateenv_single_test (const char *test_name, int fe_exc, int exception) +{ + char str[100]; + fenv_t env; + int res; + + snprintf (str, sizeof str, "feupdateenv %s and FL_DFL_ENV", test_name); + update_single_exc (str, FE_DFL_ENV, fe_exc, NO_EXC, exception); + + feraiseexcept (FE_ALL_EXCEPT); + res = fegetenv (&env); + if (res != 0) + { + printf ("fegetenv failed: %d\n", res); + ++count_errors; + return; + } + + snprintf (str, sizeof str, "feupdateenv %s and FE_ALL_EXCEPT", test_name); + update_single_exc (str, &env, ALL_EXC, ALL_EXC, exception); +} +#endif + +static void +feupdateenv_tests (void) +{ + /* We might have some exceptions still set. */ + feclearexcept (FE_ALL_EXCEPT); + +#ifdef FE_DIVBYZERO + feupdate_single_test ("FE_DIVBYZERO", FE_DIVBYZERO); +#endif +#ifdef FE_INVALID + feupdate_single_test ("FE_INVALID", FE_INVALID); +#endif +#ifdef FE_INEXACT + feupdate_single_test ("FE_INEXACT", FE_INEXACT); +#endif +#ifdef FE_UNDERFLOW + feupdate_single_test ("FE_UNDERFLOW", FE_UNDERFLOW); +#endif +#ifdef FE_OVERFLOW + feupdate_single_test ("FE_OVERFLOW", FE_OVERFLOW); +#endif + +#ifdef FE_DIVBYZERO + feupdateenv_single_test ("DIVBYZERO", DIVBYZERO_EXC, FE_DIVBYZERO); +#endif +#ifdef FE_INVALID + feupdateenv_single_test ("INVALID", INVALID_EXC, FE_INVALID); +#endif +#ifdef FE_INEXACT + feupdateenv_single_test ("INEXACT", INEXACT_EXC, FE_INEXACT); +#endif +#ifdef FE_UNDERFLOW + feupdateenv_single_test ("UNDERFLOW", UNDERFLOW_EXC, FE_UNDERFLOW); +#endif +#ifdef FE_OVERFLOW + feupdateenv_single_test ("OVERFLOW", OVERFLOW_EXC, FE_OVERFLOW); +#endif + + feupdateenv (FE_DFL_ENV); +} + static void feholdexcept_tests (void) @@ -766,13 +874,14 @@ initial_tests (void) #endif } -int -main (void) +static int +do_test (void) { initial_tests (); fe_tests (); feenv_tests (); feholdexcept_tests (); + feupdateenv_tests (); if (count_errors) { @@ -782,3 +891,5 @@ main (void) printf ("\n All tests passed successfully.\n"); return 0; } + +#include diff --git a/sysdeps/riscv/rvf/fenv_private.h b/sysdeps/riscv/rvf/fenv_private.h index 40e23661b7..d8d65458b2 100644 --- a/sysdeps/riscv/rvf/fenv_private.h +++ b/sysdeps/riscv/rvf/fenv_private.h @@ -93,10 +93,7 @@ libc_fetestexcept_riscv (int ex) static __always_inline void libc_fesetenv_riscv (const fenv_t *envp) { - long int env = (long int) envp - (long int) FE_DFL_ENV; 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It fixes math/test-fexcept on qemu-user. Reviewed-by: Carlos O'Donell --- sysdeps/alpha/fpu/fsetexcptflg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sysdeps/alpha/fpu/fsetexcptflg.c b/sysdeps/alpha/fpu/fsetexcptflg.c index 70f3666a6e..63eb06845d 100644 --- a/sysdeps/alpha/fpu/fsetexcptflg.c +++ b/sysdeps/alpha/fpu/fsetexcptflg.c @@ -27,7 +27,7 @@ __fesetexceptflag (const fexcept_t *flagp, int excepts) tmp = __ieee_get_fp_control (); /* Set all the bits that were called for. */ - tmp = (tmp & ~SWCR_STATUS_MASK) | (*flagp & excepts & SWCR_STATUS_MASK); + tmp ^= (tmp ^ *flagp) & excepts & SWCR_STATUS_MASK; /* And store it back. */ __ieee_set_fp_control (tmp); From patchwork Mon Nov 6 13:27:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adhemerval Zanella Netto X-Patchwork-Id: 1860161 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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([2804:1b3:a7c0:a715:c1a0:7281:6384:2ee9]) by smtp.gmail.com with ESMTPSA id k3-20020a05620a142300b0076f12fcb0easm3272722qkj.2.2023.11.06.05.27.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Nov 2023 05:27:29 -0800 (PST) From: Adhemerval Zanella To: libc-alpha@sourceware.org, Bruno Haible Subject: [PATCH v2 7/7] hppa: Fix undefined behaviour in feclearexcept (BZ 30983) Date: Mon, 6 Nov 2023 10:27:13 -0300 Message-Id: <20231106132713.953501-8-adhemerval.zanella@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231106132713.953501-1-adhemerval.zanella@linaro.org> References: <20231106132713.953501-1-adhemerval.zanella@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: libc-alpha-bounces+incoming=patchwork.ozlabs.org@sourceware.org From: Bruno Haible The expression (excepts & FE_ALL_EXCEPT) << 27 produces a signed integer overflow when 'excepts' is specified as FE_INVALID (= 0x10), because - excepts is of type 'int', - FE_ALL_EXCEPT is of type 'int', - thus (excepts & FE_ALL_EXCEPT) is (int) 0x10, - 'int' is 32 bits wide. The patched code produces the same instruction sequence as previosuly. Reviewed-by: Carlos O'Donell --- sysdeps/hppa/fpu/fclrexcpt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sysdeps/hppa/fpu/fclrexcpt.c b/sysdeps/hppa/fpu/fclrexcpt.c index 055fb04ccc..46caf39ec1 100644 --- a/sysdeps/hppa/fpu/fclrexcpt.c +++ b/sysdeps/hppa/fpu/fclrexcpt.c @@ -26,7 +26,7 @@ feclearexcept (int excepts) /* Get the current status word. */ __asm__ ("fstd %%fr0,0(%1)" : "=m" (s.l) : "r" (&s.l) : "%r0"); /* Clear all the relevant bits. */ - s.sw[0] &= ~((excepts & FE_ALL_EXCEPT) << 27); + s.sw[0] &= ~(((unsigned int) excepts & FE_ALL_EXCEPT) << 27); __asm__ ("fldd 0(%0),%%fr0" : : "r" (&s.l), "m" (s.l) : "%r0"); /* Success. */