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Iglesias" , "Daniel P . Berrange" , Thomas Huth , Kevin Wolf , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 1/5] qdev: Add qdev_prop_set_array() Date: Mon, 30 Oct 2023 15:39:52 +0100 Message-ID: <20231030143957.82988-2-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231030143957.82988-1-philmd@linaro.org> References: <20231030143957.82988-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Kevin Wolf Instead of exposing the ugly hack of how we represent arrays in qdev (a static "foo-len" property and after it is set, dynamically created "foo[i]" properties) to boards, add an interface that allows setting the whole array at once. Once all internal users of devices with array properties have been converted to use this function, we can change the implementation to move away from this hack. Signed-off-by: Kevin Wolf Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Peter Maydell Tested-by: Philippe Mathieu-Daudé Message-ID: <20231030114802.3671871-4-peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé --- include/hw/qdev-properties.h | 3 +++ hw/core/qdev-properties.c | 21 +++++++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/include/hw/qdev-properties.h b/include/hw/qdev-properties.h index e1df08876c..7fa2fdb7c9 100644 --- a/include/hw/qdev-properties.h +++ b/include/hw/qdev-properties.h @@ -206,6 +206,9 @@ void qdev_prop_set_macaddr(DeviceState *dev, const char *name, const uint8_t *value); void qdev_prop_set_enum(DeviceState *dev, const char *name, int value); +/* Takes ownership of @values */ +void qdev_prop_set_array(DeviceState *dev, const char *name, QList *values); + void *object_field_prop_ptr(Object *obj, Property *prop); void qdev_prop_register_global(GlobalProperty *prop); diff --git a/hw/core/qdev-properties.c b/hw/core/qdev-properties.c index 357b8761b5..950ef48e01 100644 --- a/hw/core/qdev-properties.c +++ b/hw/core/qdev-properties.c @@ -3,12 +3,14 @@ #include "qapi/error.h" #include "qapi/qapi-types-misc.h" #include "qapi/qmp/qerror.h" +#include "qapi/qmp/qlist.h" #include "qemu/ctype.h" #include "qemu/error-report.h" #include "qapi/visitor.h" #include "qemu/units.h" #include "qemu/cutils.h" #include "qdev-prop-internal.h" +#include "qom/qom-qobject.h" void qdev_prop_set_after_realize(DeviceState *dev, const char *name, Error **errp) @@ -739,6 +741,25 @@ void qdev_prop_set_enum(DeviceState *dev, const char *name, int value) &error_abort); } +void qdev_prop_set_array(DeviceState *dev, const char *name, QList *values) +{ + const QListEntry *entry; + g_autofree char *prop_len = g_strdup_printf("len-%s", name); + uint32_t i = 0; + + object_property_set_int(OBJECT(dev), prop_len, qlist_size(values), + &error_abort); + + QLIST_FOREACH_ENTRY(values, entry) { + g_autofree char *prop_idx = g_strdup_printf("%s[%u]", name, i); + object_property_set_qobject(OBJECT(dev), prop_idx, entry->value, + &error_abort); + i++; + } + + qobject_unref(values); +} + static GPtrArray *global_props(void) { static GPtrArray *gp; From patchwork Mon Oct 30 14:39:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1857151 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=m94c3oL4; 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Iglesias" , "Daniel P . Berrange" , Thomas Huth , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 2/5] hw/ppc/e500: Declare CPU QOM types using DEFINE_TYPES() macro Date: Mon, 30 Oct 2023 15:39:53 +0100 Message-ID: <20231030143957.82988-3-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231030143957.82988-1-philmd@linaro.org> References: <20231030143957.82988-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org When multiple QOM types are registered in the same file, it is simpler to use the the DEFINE_TYPES() macro. In particular because type array declared with such macro are easier to review. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Daniel Henrique Barboza --- I'm going to do that for each file I modify, so eventually we'll get all converted. --- hw/ppc/ppce500_spin.c | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/hw/ppc/ppce500_spin.c b/hw/ppc/ppce500_spin.c index bbce63e8a4..e3608d8c16 100644 --- a/hw/ppc/ppce500_spin.c +++ b/hw/ppc/ppce500_spin.c @@ -195,17 +195,14 @@ static void ppce500_spin_class_init(ObjectClass *klass, void *data) dc->reset = spin_reset; } -static const TypeInfo ppce500_spin_info = { - .name = TYPE_E500_SPIN, - .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(SpinState), - .instance_init = ppce500_spin_initfn, - .class_init = ppce500_spin_class_init, +static const TypeInfo ppce500_spin_types[] = { + { + .name = TYPE_E500_SPIN, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(SpinState), + .instance_init = ppce500_spin_initfn, + .class_init = ppce500_spin_class_init, + }, }; -static void ppce500_spin_register_types(void) -{ - type_register_static(&ppce500_spin_info); -} - -type_init(ppce500_spin_register_types) +DEFINE_TYPES(ppce500_spin_types) From patchwork Mon Oct 30 14:39:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1857152 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=ECN+3hdz; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SJwvy4tltz1yQW for ; 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Mon, 30 Oct 2023 07:40:22 -0700 (PDT) Received: from m1x-phil.lan ([176.170.212.50]) by smtp.gmail.com with ESMTPSA id j8-20020a5d4528000000b0032f7c563ffasm5790158wra.36.2023.10.30.07.40.20 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 30 Oct 2023 07:40:22 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Peter Maydell , Markus Armbruster Cc: Luc Michel , Daniel Henrique Barboza , Alistair Francis , Paolo Bonzini , Eduardo Habkost , Mark Cave-Ayland , Bernhard Beschow , qemu-ppc@nongnu.org, "Edgar E . Iglesias" , "Daniel P . Berrange" , Thomas Huth , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 3/5] hw/ppc/e500: QOM-attach CPUs to the machine container Date: Mon, 30 Oct 2023 15:39:54 +0100 Message-ID: <20231030143957.82988-4-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231030143957.82988-1-philmd@linaro.org> References: <20231030143957.82988-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=philmd@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Instead of having CPUs dangling in the /unattached/device bucket, attach them to the machine container. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Daniel Henrique Barboza --- hw/ppc/e500.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index e04114fb3c..f8177c0280 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -946,6 +946,7 @@ void ppce500_init(MachineState *machine) exit(1); } + object_property_add_child(OBJECT(machine), "cpu[*]", OBJECT(cs)); /* * Secondary CPU starts in halted state for now. Needs to change * when implementing non-kernel boot. From patchwork Mon Oct 30 14:39:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1857145 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=l9XFofqY; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SJwts35nJz1yQW for ; Tue, 31 Oct 2023 01:41:09 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qxTRa-0001ZA-MM; Mon, 30 Oct 2023 10:40:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qxTRY-0001W9-Up for qemu-ppc@nongnu.org; Mon, 30 Oct 2023 10:40:40 -0400 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qxTRR-0001v0-5G for qemu-ppc@nongnu.org; Mon, 30 Oct 2023 10:40:40 -0400 Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-408002b5b9fso33254285e9.3 for ; Mon, 30 Oct 2023 07:40:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698676829; x=1699281629; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=aVj8Lyu+q9x5vjJruURmWnURg8Bgtfz5nJe1rKfNnjc=; b=l9XFofqY40eX2o22JxQvvb7n/Y1zxtHMOabArZZXMpCsawGVBd0gzZdFGhziwba73s H76CYtofOX9dPmvEUjn2/vcra0cF8zBEOlWzEW+8S9KWjURhAWZSbJc3P/TwmVKh/aNj fG+iCl+GhdbpKeEZIHo1VMExfXQ7AoddZKTGAMumsbZRDGGYXwlhQlhOgC39BGp1wPf9 rNiazZ4YO/syIQsAJybezC/6Ll2WB30zz+IqSpMQ9F5cXVryJ/zgR5UGczTAFDGqxnhH CqKgvF9N3vNLxNwQa3LkcRwaKJqRqfeaXd2miol3hzy2r/RoYMnZb1dh2CVaqQis/0Fq zZSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698676829; x=1699281629; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aVj8Lyu+q9x5vjJruURmWnURg8Bgtfz5nJe1rKfNnjc=; b=es53jKPoLpQhMNuKJ4+KFqxwtcY2mrq9n8AH1AnmxrYj9VCMjptKTgdIXUFRmOQP3F lYt0IVmgZauC9zQXr6Ak65zr6uccpIkbdhVSesZguH3L693XCCBLQMPKBRlyVvqfuYV7 T7MPzcAIb0HR53n0SckFcP24LaQz6o4E3wYyylnkwT6RUNKbW6A57fBJIloN4vTBLjCP o/BSQfU3U4KKNn5r5K+3iFV7+qemCUGJcacc4FtbX3hl2fZ0utZ1Sqs4XptAxabjnMpn tUILv9t8VoiH29czoL9tAL86F5PW0b8oNjCavTDvSkXxMGK2wfYNxikwGOniYVTLI7l4 RX0A== X-Gm-Message-State: AOJu0YwAbCngHjvuhbHR680Q8g6tGgExPJu+s/o2ljacxdPzBEMJHpup zJq2cifklHwjYwQ0lyF7TQoAsQ== X-Google-Smtp-Source: AGHT+IFyovKWaKgklMSqmOkM4ZOwVOwEtx3oRZP4ALic/VmmF4HYc/dmUWLdo9anjMf8cGZq9GAA1A== X-Received: by 2002:a05:600c:a0a:b0:405:3b1f:968b with SMTP id z10-20020a05600c0a0a00b004053b1f968bmr8835285wmp.21.1698676829437; Mon, 30 Oct 2023 07:40:29 -0700 (PDT) Received: from m1x-phil.lan ([176.170.212.50]) by smtp.gmail.com with ESMTPSA id r5-20020a05600c458500b004060f0a0fd5sm9314651wmo.13.2023.10.30.07.40.27 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 30 Oct 2023 07:40:29 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Peter Maydell , Markus Armbruster Cc: Luc Michel , Daniel Henrique Barboza , Alistair Francis , Paolo Bonzini , Eduardo Habkost , Mark Cave-Ayland , Bernhard Beschow , qemu-ppc@nongnu.org, "Edgar E . Iglesias" , "Daniel P . Berrange" , Thomas Huth , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 4/5] hw/ppc/e500: Inline sysbus_create_simple(E500_SPIN) Date: Mon, 30 Oct 2023 15:39:55 +0100 Message-ID: <20231030143957.82988-5-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231030143957.82988-1-philmd@linaro.org> References: <20231030143957.82988-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org In the next commit we'll set properties to the TYPE_E500_SPIN object. In order to ease next commit review, inline the sysbus_create_simple() call first. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Daniel Henrique Barboza --- hw/ppc/e500.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index f8177c0280..e38f46df38 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -1082,7 +1082,9 @@ void ppce500_init(MachineState *machine) } /* Register spinning region */ - sysbus_create_simple("e500-spin", pmc->spin_base, NULL); + dev = qdev_new("e500-spin"); + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, pmc->spin_base); if (pmc->has_mpc8xxx_gpio) { qemu_irq poweroff_irq; From patchwork Mon Oct 30 14:39:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1857148 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=vYkJhsmn; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SJwvN0t2cz1yQW for ; Tue, 31 Oct 2023 01:41:36 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qxTS6-00028Y-MQ; Mon, 30 Oct 2023 10:41:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qxTRx-0001nw-8W for qemu-ppc@nongnu.org; Mon, 30 Oct 2023 10:41:06 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qxTRY-0001vi-7x for qemu-ppc@nongnu.org; Mon, 30 Oct 2023 10:41:05 -0400 Received: by mail-wr1-x42b.google.com with SMTP id ffacd0b85a97d-32df66c691dso2867313f8f.3 for ; Mon, 30 Oct 2023 07:40:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698676836; x=1699281636; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/nhttjW6fGHzpzQpigFGqu2RntvPUsap0hdm5++FEtY=; b=vYkJhsmnG7mN0JZeLeVEKuGkW607fC/g8nfFkBnS2305X4u9HwujX2abRwZSJ8rt0u HQG9Oh9v7fg4SMMjrb6TAIIqIR82Qj+P2HwJhPhvbBDK8+fwhO9N3Z6V6XWkzAyGcbPV B6bs3FZ0Kb3zpCt+vP7/or9GkkBcj/YlXpamEg6OQqXexmw1zed8t5rhUD7c0WatjiNF U8gkI0XWyrLWaCvh+HzAXuhwXMSuhseu1WzmBGoxDJNClRdzUMpt0sBy9Cp8CDurtTR5 AbzCDJ26wotYTYNhMstg3k9FsqT0Y6Z8XcwY36vXenAdVunOpetICftq7RrdBjVmnl64 cQbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698676836; x=1699281636; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/nhttjW6fGHzpzQpigFGqu2RntvPUsap0hdm5++FEtY=; b=ubUCVKV0KV58d6l093B2lfNrlpqHnWIxUMasOoJ7/Lwss3GJoqKT7KNaeDmt39qubl Gz6n3Tnxi4aLMpQcjiqD2T1tLMhVOReCGXI8b+p72ILpbaJrYLBDwjsQERg7SRzqcL5J h3o6mQavmRQ9dnQO1/D9436JNatW1aUTzpz1SnFoh3Sk9ywsmyMSSYDebNwRQ86xmuic NNODHyuItO3/gRF9LK2cZh3/EAEekD9JZpEoD2JQ6zm/FfgwDENfuhC5C42oMvRc/eaS nNpI46qovudNttD8DzynJYyqoiHYBSM4IOZaPKW1FVFIJ7eDMI+uq0L6K4DJXtqlCUYP s7tQ== X-Gm-Message-State: AOJu0Yx8OeAV4etUCClIMVxJLGTrt7x3V9o5w9Xs2sUanJViv6wuVBzm lpEajXqDUCKVcfRQk0HG0t10dg== X-Google-Smtp-Source: AGHT+IGw9Zw4AVLpyPMNpYfQu9hgU/YdqWs9X0eAyGX2njs86nUMWzRYvqTUsWcSj4e5L7KzOkRn4w== X-Received: by 2002:a5d:4ccb:0:b0:32d:a0d9:2124 with SMTP id c11-20020a5d4ccb000000b0032da0d92124mr7575851wrt.35.1698676836704; Mon, 30 Oct 2023 07:40:36 -0700 (PDT) Received: from m1x-phil.lan ([176.170.212.50]) by smtp.gmail.com with ESMTPSA id z8-20020adfe548000000b0031c52e81490sm8432316wrm.72.2023.10.30.07.40.34 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 30 Oct 2023 07:40:36 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Peter Maydell , Markus Armbruster Cc: Luc Michel , Daniel Henrique Barboza , Alistair Francis , Paolo Bonzini , Eduardo Habkost , Mark Cave-Ayland , Bernhard Beschow , qemu-ppc@nongnu.org, "Edgar E . Iglesias" , "Daniel P . Berrange" , Thomas Huth , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [RFC PATCH 5/5] hw/ppc/e500: Pass array of CPUs as array of canonical QOM paths Date: Mon, 30 Oct 2023 15:39:56 +0100 Message-ID: <20231030143957.82988-6-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231030143957.82988-1-philmd@linaro.org> References: <20231030143957.82988-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=philmd@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_PASS=-0.001, T_SPF_HELO_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Devices should avoid calling qemu_get_cpu() because this call doesn't work as expected with heterogeneous machines. Such devices often iterate over a cluster of CPUs, which the device's parent has direct access (when creating the child device). We can pass QOM as 'link' between objects, but we can't pass an array of links. Here we exploits QAPI simplicity, by using DEFINE_PROP_ARRAY and a list of strings, each string being the CPU canonical path in QOM tree (which is constant and unique). When the device realizes itself, the original CPU pointer is recovered via a object_resolve_path() call. Inspired-by: Peter Maydell Inspired-by: Markus Armbruster Signed-off-by: Philippe Mathieu-Daudé --- Tested with: $ make check-qtest-ppc{,64} $ make check-avocado AVOCADO_TAGS='machine:ppce500 machine:mpc8544ds' RFC: See cover FIXME: Should we free spin_cpu_list using g_autoptr(QList)? --- hw/ppc/e500.c | 6 ++++++ hw/ppc/ppce500_spin.c | 48 ++++++++++++++++++++++++++++++++++++------- 2 files changed, 47 insertions(+), 7 deletions(-) diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index e38f46df38..8b31143dca 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -18,6 +18,7 @@ #include "qemu/datadir.h" #include "qemu/units.h" #include "qemu/guest-random.h" +#include "qapi/qmp/qlist.h" #include "qapi/error.h" #include "e500.h" #include "e500-ccsr.h" @@ -930,11 +931,13 @@ void ppce500_init(MachineState *machine) SysBusDevice *s; PPCE500CCSRState *ccsr; I2CBus *i2c; + QList *spin_cpu_list = qlist_new(); irqs = g_new0(IrqLines, smp_cpus); for (i = 0; i < smp_cpus; i++) { PowerPCCPU *cpu; CPUState *cs; + g_autofree char *cpu_qompath; cpu = POWERPC_CPU(object_new(machine->cpu_type)); env = &cpu->env; @@ -954,6 +957,8 @@ void ppce500_init(MachineState *machine) object_property_set_bool(OBJECT(cs), "start-powered-off", i != 0, &error_fatal); qdev_realize_and_unref(DEVICE(cs), NULL, &error_fatal); + cpu_qompath = object_get_canonical_path(OBJECT(cs)); + qlist_append_str(spin_cpu_list, cpu_qompath); if (!firstenv) { firstenv = env; @@ -1083,6 +1088,7 @@ void ppce500_init(MachineState *machine) /* Register spinning region */ dev = qdev_new("e500-spin"); + qdev_prop_set_array(dev, "cpus-qom-path", spin_cpu_list); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, pmc->spin_base); diff --git a/hw/ppc/ppce500_spin.c b/hw/ppc/ppce500_spin.c index e3608d8c16..a67046b2ea 100644 --- a/hw/ppc/ppce500_spin.c +++ b/hw/ppc/ppce500_spin.c @@ -30,11 +30,13 @@ #include "qemu/osdep.h" #include "qemu/module.h" #include "qemu/units.h" +#include "qapi/error.h" #include "hw/hw.h" #include "hw/sysbus.h" #include "sysemu/hw_accel.h" #include "e500.h" #include "qom/object.h" +#include "hw/qdev-properties.h" #define MAX_CPUS 32 @@ -46,6 +48,10 @@ typedef struct spin_info { uint64_t reserved; } QEMU_PACKED SpinInfo; +/* + * QEMU interface: + * + QOM array property "cpus-qom-path": QOM canonical path of each CPU. + */ #define TYPE_E500_SPIN "e500-spin" OBJECT_DECLARE_SIMPLE_TYPE(SpinState, E500_SPIN) @@ -54,6 +60,9 @@ struct SpinState { MemoryRegion iomem; SpinInfo spin[MAX_CPUS]; + uint32_t cpu_count; + char **cpu_canonical_path; + CPUState **cpu; }; static void spin_reset(DeviceState *dev) @@ -121,16 +130,10 @@ static void spin_write(void *opaque, hwaddr addr, uint64_t value, { SpinState *s = opaque; int env_idx = addr / sizeof(SpinInfo); - CPUState *cpu; + CPUState *cpu = s->cpu[env_idx]; SpinInfo *curspin = &s->spin[env_idx]; uint8_t *curspin_p = (uint8_t*)curspin; - cpu = qemu_get_cpu(env_idx); - if (cpu == NULL) { - /* Unknown CPU */ - return; - } - if (cpu->cpu_index == 0) { /* primary CPU doesn't spin */ return; @@ -188,11 +191,42 @@ static void ppce500_spin_initfn(Object *obj) sysbus_init_mmio(dev, &s->iomem); } +static void ppce500_spin_realize(DeviceState *dev, Error **errp) +{ + SpinState *s = E500_SPIN(dev); + + if (s->cpu_count == 0) { + error_setg(errp, "'cpus-qom-path' property array must be set"); + return; + } else if (s->cpu_count > MAX_CPUS) { + error_setg(errp, "at most %d CPUs are supported", MAX_CPUS); + return; + } + + s->cpu = g_new(CPUState *, s->cpu_count); + for (unsigned i = 0; i < s->cpu_count; i++) { + bool ambiguous; + Object *obj; + + obj = object_resolve_path(s->cpu_canonical_path[i], &ambiguous); + assert(!ambiguous); + s->cpu[i] = CPU(obj); + } +} + +static Property ppce500_spin_properties[] = { + DEFINE_PROP_ARRAY("cpus-qom-path", SpinState, cpu_count, + cpu_canonical_path, qdev_prop_string, char *), + DEFINE_PROP_END_OF_LIST(), +}; + static void ppce500_spin_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); dc->reset = spin_reset; + dc->realize = ppce500_spin_realize; + device_class_set_props(dc, ppce500_spin_properties); } static const TypeInfo ppce500_spin_types[] = {