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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698244223; x=1698849023; h=to:subject:message-id:date:from:mime-version:x-gm-message-state :from:to:cc:subject:date:message-id:reply-to; bh=+YTF0aHasTMPisbXLDEcC0fL1x5C110qPt06VKJY9M8=; b=Ey4iYuz8C5kpw3d25Lcy20D/hRmpzwEWc6k7H109RYKVvuG0wdCAfzd3jTWmVFo2vl 2IrnqG+b6afMv/GV+Wj47hR6rX7afh/wvkUd67h3+wVoKEqKTb6cX6isIPRCVOhX+McT SOXuSCi8MVnM+wWCR0lBmK1KjPqda8YQwOxUZbMoS4ijmngmOFZNNhs9bQxr8BAamuVh eMLlD1EioSut+shPmB27B8W/cLf7HwftUmuJ3FknO9QcQ4+u/5YHtUifSjit3De1bayS R+vXC4W7jtqpp9fual64velJk1ysnL5omRO2CcYIcbNhUqOEPp/cN9woqdaCtNSa/DOX KPYQ== X-Gm-Message-State: AOJu0Yw+lteIxMz5MKHwKbNoIFXKgrJkxy3ylLS44oFiXacur7+/NSoH ir8T15biAb74CMFJXgIkHnIkb+5PE89Rmn+dsuza5tDFXORmeQ== X-Google-Smtp-Source: AGHT+IEQriXrtxiwwgOwMxUh97oTavxb8c389L9YWQf9pm3vlELT8lrzuqducigxGjAL0p6gXkWASlzlLvcad0smQt0= X-Received: by 2002:a50:c88c:0:b0:534:6b86:eda2 with SMTP id d12-20020a50c88c000000b005346b86eda2mr13784394edh.21.1698244223310; Wed, 25 Oct 2023 07:30:23 -0700 (PDT) MIME-Version: 1.0 From: Uros Bizjak Date: Wed, 25 Oct 2023 16:30:12 +0200 Message-ID: Subject: [committed] i386: Narrow test instructions with immediate operands [PR111698] To: "gcc-patches@gcc.gnu.org" X-Spam-Status: No, score=-8.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org i386: Narrow test instructions with immediate operands [PR111698] Narrow test instructions with immediate operand that test memory location for zero. E.g. testl $0x00aa0000, mem can be converted to testb $0xaa, mem+2. Reject targets where reading (possibly unaligned) part of memory location after a large write to the same address causes store-to-load forwarding stall. PR target/111698 gcc/ChangeLog: * config/i386/x86-tune.def (X86_TUNE_PARTIAL_MEMORY_READ_STALL): New tune. * config/i386/i386.h (TARGET_PARTIAL_MEMORY_READ_STALL): New macro. * config/i386/i386.md: New peephole pattern to narrow test instructions with immediate operands that test memory locations for zero. gcc/testsuite/ChangeLog: * gcc.target/i386/pr111698.c: New test. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Uros. diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index e4c1fc6eef0..4426b27f4fe 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -311,6 +311,8 @@ extern unsigned char ix86_tune_features[X86_TUNE_LAST]; #define TARGET_USE_SAHF ix86_tune_features[X86_TUNE_USE_SAHF] #define TARGET_MOVX ix86_tune_features[X86_TUNE_MOVX] #define TARGET_PARTIAL_REG_STALL ix86_tune_features[X86_TUNE_PARTIAL_REG_STALL] +#define TARGET_PARTIAL_MEMORY_READ_STALL \ + ix86_tune_features[X86_TUNE_PARTIAL_MEMORY_READ_STALL] #define TARGET_PARTIAL_FLAG_REG_STALL \ ix86_tune_features[X86_TUNE_PARTIAL_FLAG_REG_STALL] #define TARGET_LCP_STALL \ diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index f90cf1ca734..5d8d5b2eae6 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -11100,6 +11100,57 @@ (define_split operands[3] = gen_int_mode (INTVAL (operands[3]), QImode); }) +;; Narrow test instructions with immediate operands that test +;; memory locations for zero. E.g. testl $0x00aa0000, mem can be +;; converted to testb $0xaa, mem+2. Reject volatile locations and +;; targets where reading (possibly unaligned) part of memory +;; location after a large write to the same address causes +;; store-to-load forwarding stall. +(define_peephole2 + [(set (reg:CCZ FLAGS_REG) + (compare:CCZ + (and:SWI248 (match_operand:SWI248 0 "memory_operand") + (match_operand 1 "const_int_operand")) + (const_int 0)))] + "!TARGET_PARTIAL_MEMORY_READ_STALL && !MEM_VOLATILE_P (operands[0])" + [(set (reg:CCZ FLAGS_REG) + (compare:CCZ (match_dup 2) (const_int 0)))] +{ + unsigned HOST_WIDE_INT ival = UINTVAL (operands[1]); + int first_nonzero_byte, bitsize; + rtx new_addr, new_const; + machine_mode new_mode; + + if (ival == 0) + FAIL; + + /* Clear bits outside mode width. */ + ival &= GET_MODE_MASK (mode); + + first_nonzero_byte = ctz_hwi (ival) / BITS_PER_UNIT; + + ival >>= first_nonzero_byte * BITS_PER_UNIT; + + bitsize = sizeof (ival) * BITS_PER_UNIT - clz_hwi (ival); + + if (bitsize <= GET_MODE_BITSIZE (QImode)) + new_mode = QImode; + else if (bitsize <= GET_MODE_BITSIZE (HImode)) + new_mode = HImode; + else if (bitsize <= GET_MODE_BITSIZE (SImode)) + new_mode = SImode; + else + new_mode = DImode; + + if (GET_MODE_SIZE (new_mode) >= GET_MODE_SIZE (mode)) + FAIL; + + new_addr = adjust_address (operands[0], new_mode, first_nonzero_byte); + new_const = gen_int_mode (ival, new_mode); + + operands[2] = gen_rtx_AND (new_mode, new_addr, new_const); +}) + ;; %%% This used to optimize known byte-wide and operations to memory, ;; and sometimes to QImode registers. If this is considered useful, ;; it should be done with splitters. diff --git a/gcc/config/i386/x86-tune.def b/gcc/config/i386/x86-tune.def index 3636a4a95d8..9d0699ff9b9 100644 --- a/gcc/config/i386/x86-tune.def +++ b/gcc/config/i386/x86-tune.def @@ -658,6 +658,14 @@ DEF_TUNE (X86_TUNE_NOT_UNPAIRABLE, "not_unpairable", m_PENT | m_LAKEMONT) and can happen in caller/callee saving sequences. */ DEF_TUNE (X86_TUNE_PARTIAL_REG_STALL, "partial_reg_stall", m_PPRO) +/* X86_TUNE_PARTIAL_MEMORY_READ_STALL: Reading (possible unaligned) part of + memory location after a large write to the same address causes + store-to-load forwarding stall. */ +DEF_TUNE (X86_TUNE_PARTIAL_MEMORY_READ_STALL, "partial_memoy_read_stall", + m_386 | m_486 | m_PENT | m_LAKEMONT | m_PPRO | m_P4_NOCONA | m_CORE2 + | m_SILVERMONT | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT + | m_K6_GEODE | m_ATHLON_K8 | m_AMDFAM10) + /* X86_TUNE_PROMOTE_QIMODE: When it is cheap, turn 8bit arithmetic to corresponding 32bit arithmetic. */ DEF_TUNE (X86_TUNE_PROMOTE_QIMODE, "promote_qimode", diff --git a/gcc/testsuite/gcc.target/i386/pr111698.c b/gcc/testsuite/gcc.target/i386/pr111698.c new file mode 100644 index 00000000000..2da6be531a2 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr111698.c @@ -0,0 +1,19 @@ +/* PR target/111698 */ +/* { dg-options "-O2 -masm=att" } */ +/* { dg-final { scan-assembler-not "testl" } } */ + +int m; + +_Bool foo (void) +{ + return m & 0x0a0000; +} + +/* { dg-final { scan-assembler-times "testb" 1 } } */ + +_Bool bar (void) +{ + return m & 0xa0a000; +} + +/* { dg-final { scan-assembler-times "testw" 1 } } */