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([2804:1b3:a7c3:a647:44d5:84b0:a3f2:fe73]) by smtp.gmail.com with ESMTPSA id k28-20020aa79d1c000000b006bde2480806sm7506663pfp.47.2023.10.24.04.37.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Oct 2023 04:37:24 -0700 (PDT) From: Adhemerval Zanella To: libc-alpha@sourceware.org Cc: Bruno Haible Subject: [PATCH v2 1/3] powerpc: Do not raise exception traps for fesetexcept/fesetexceptflag (BZ 30988) Date: Tue, 24 Oct 2023 08:37:14 -0300 Message-Id: <20231024113716.3911015-2-adhemerval.zanella@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231024113716.3911015-1-adhemerval.zanella@linaro.org> References: <20231024113716.3911015-1-adhemerval.zanella@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: libc-alpha-bounces+incoming=patchwork.ozlabs.org@sourceware.org According to ISO C23 (7.6.4.4), fesetexcept is supposed to set floating-point exception flags without raising a trap (unlike feraiseexcept, which is supposed to raise a trap if feenableexcept was called with the appropriate argument). This is a side-effect of how we implement the GNU extension feenableexcept, where feenableexcept/fesetenv/fesetmode/feupdateenv might issue prctl (PR_SET_FPEXC, PR_FP_EXC_PRECISE) depending of the argument. And on PR_FP_EXC_PRECISE, setting a floating-point exception flag triggers a trap. To make the both functions follow the C23, fesetexcept and fesetexceptflag now fail if the argument may trigger a trap. The math tests now check for an value different than 0, instead of bail out as unsupported for EXCEPTION_SET_FORCES_TRAP. Checked on powerpc64le-linux-gnu. --- math/test-fesetexcept-traps.c | 11 ++++------- math/test-fexcept-traps.c | 11 ++++------- sysdeps/powerpc/fpu/fesetexcept.c | 5 +++++ sysdeps/powerpc/fpu/fsetexcptflg.c | 9 ++++++++- 4 files changed, 21 insertions(+), 15 deletions(-) diff --git a/math/test-fesetexcept-traps.c b/math/test-fesetexcept-traps.c index 71b6e45b33..96f6c4752f 100644 --- a/math/test-fesetexcept-traps.c +++ b/math/test-fesetexcept-traps.c @@ -39,16 +39,13 @@ do_test (void) return result; } - if (EXCEPTION_SET_FORCES_TRAP) - { - puts ("setting exceptions traps, cannot test on this architecture"); - return 77; - } - /* Verify fesetexcept does not cause exception traps. */ + /* Verify fesetexcept does not cause exception traps. For architectures + where setting the exception might result in traps the function should + return a nonzero value. */ ret = fesetexcept (FE_ALL_EXCEPT); if (ret == 0) puts ("fesetexcept (FE_ALL_EXCEPT) succeeded"); - else + else if (!EXCEPTION_SET_FORCES_TRAP) { puts ("fesetexcept (FE_ALL_EXCEPT) failed"); if (EXCEPTION_TESTS (float)) diff --git a/math/test-fexcept-traps.c b/math/test-fexcept-traps.c index 9701c3c320..9b8f583ae6 100644 --- a/math/test-fexcept-traps.c +++ b/math/test-fexcept-traps.c @@ -63,14 +63,11 @@ do_test (void) result = 1; } - if (EXCEPTION_SET_FORCES_TRAP) - { - puts ("setting exceptions traps, cannot test on this architecture"); - return 77; - } - /* The test is that this does not cause exception traps. */ + /* The test is that this does not cause exception traps. For architectures + where setting the exception might result in traps the function should + return a nonzero value. */ ret = fesetexceptflag (&saved, FE_ALL_EXCEPT); - if (ret != 0) + if (ret != 0 && !EXCEPTION_SET_FORCES_TRAP) { puts ("fesetexceptflag failed"); result = 1; diff --git a/sysdeps/powerpc/fpu/fesetexcept.c b/sysdeps/powerpc/fpu/fesetexcept.c index 609a148a95..2850156d3a 100644 --- a/sysdeps/powerpc/fpu/fesetexcept.c +++ b/sysdeps/powerpc/fpu/fesetexcept.c @@ -31,6 +31,11 @@ fesetexcept (int excepts) & FE_INVALID_SOFTWARE)); if (n.l != u.l) { + if (n.l & fenv_exceptions_to_reg (excepts)) + /* Setting the exception flags may trigger a trap. ISO C 23 § 7.6.4.4 + does not allow it. */ + return -1; + fesetenv_register (n.fenv); /* Deal with FE_INVALID_SOFTWARE not being implemented on some chips. */ diff --git a/sysdeps/powerpc/fpu/fsetexcptflg.c b/sysdeps/powerpc/fpu/fsetexcptflg.c index 2b22f913c0..6517e8ea03 100644 --- a/sysdeps/powerpc/fpu/fsetexcptflg.c +++ b/sysdeps/powerpc/fpu/fsetexcptflg.c @@ -44,7 +44,14 @@ __fesetexceptflag (const fexcept_t *flagp, int excepts) This may cause floating-point exceptions if the restored state requests it. */ if (n.l != u.l) - fesetenv_register (n.fenv); + { + if (n.l & fenv_exceptions_to_reg (excepts)) + /* Setting the exception flags may trigger a trap. ISO C 23 § 7.6.4.4 + does not allow it. */ + return -1; + + fesetenv_register (n.fenv); + } /* Deal with FE_INVALID_SOFTWARE not being implemented on some chips. */ if (flag & FE_INVALID) From patchwork Tue Oct 24 11:37:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adhemerval Zanella Netto X-Patchwork-Id: 1854331 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=YZ7vaKTy; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=sourceware.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=libc-alpha-bounces+incoming=patchwork.ozlabs.org@sourceware.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SF95x2ZTVz23jl for ; Tue, 24 Oct 2023 22:37:41 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 6E7523856967 for ; Tue, 24 Oct 2023 11:37:39 +0000 (GMT) X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from mail-pg1-x52e.google.com (mail-pg1-x52e.google.com [IPv6:2607:f8b0:4864:20::52e]) by sourceware.org (Postfix) with ESMTPS id B22A93858C2C for ; Tue, 24 Oct 2023 11:37:28 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B22A93858C2C Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linaro.org ARC-Filter: OpenARC Filter v1.0.0 sourceware.org B22A93858C2C Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::52e ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698147450; cv=none; b=re55Iw+rcc8ITX/ZgqDqfBBsQLw2OIjibeXm1gksWXq4gVZiu6wgeezffZ6hbVyueMm2TASic0fe1n6yZIqPfIdx1wo5UUAVQ2/whMIedLwvEUTqxSOcX4MIIv/jNmR/cXE+2tSoD2+0e0TFS+IfBwumYIkbFfCJ+e/FgvzyCw8= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698147450; c=relaxed/simple; bh=F5dZBtGI0oHO9/8EX6VjjBDGl5NVNM4NeMvraHeIR54=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=Y/895SK40Icb+5HjK8Mjki/NAGwU/GTeriA/iasEoLxGxBRS3CxQxG6mzuoh/JLqp/bzepzeK0aVjmAs0cnv91VETSGP/JatZozpyq0x6kI0RlI+OieRYs6Zknes6JBFXgG2RJNCS8J7rb4gI41zATK015+G5BVU33XPchCVRDE= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-pg1-x52e.google.com with SMTP id 41be03b00d2f7-5ab94fc098cso2522385a12.1 for ; Tue, 24 Oct 2023 04:37:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698147447; x=1698752247; darn=sourceware.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xyN0+MPmXPFjdAwhfIEaZ5KCieYNszKZx9zB2QRUtIw=; b=YZ7vaKTyMmBuiUNCKjknCoYUD+vwgfQss6CooGnYz/CLl8LAh8CVmpDxU3axLr3z1T ghY372hGi5nQs8QeNjtwvIeyiN2yrFjr45U31wHMqtZNo9yeHWvx09nMC+yE8Q/ogL+N N43ann2NiqwXOEhdIc9cNYBPQZJCHFA5Lq0LDvkQWpaTxMUOp15RzUkdjs8coYOcGFeD rvYqcKsPh4pX6PpzVRXDog4rajATnVoBBTECoLBFiqX53fYUNJLKXL4ULiKfZb1BbhAo CH2Ng2ZX1I/oXMGj1nOUGJLiW03m3B1CuNeZ/oxrPVuzEPd/2WHqco4VxXYUrFF/+8X7 Nc+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698147447; x=1698752247; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xyN0+MPmXPFjdAwhfIEaZ5KCieYNszKZx9zB2QRUtIw=; b=nRQnFWr0zB/bQirv7XDe3R9iwHyO6u5BW7/zNZifNwuJ38ULyrx3i2CZyNyMAx8X9R WO9NoYsccLTbyGEXfCH38yk7kbl3/iaeKV7wa/n76eTzTCkTbYdmaR06CW0HOCtk8BfH qQGNnoN/Au8Mz001z5V3FP90ma76LU7IlaDElUc3NoYgtl+t/Ao45bPndQLvau+7/qp+ G5aSk1uRZwtHsLDK0sR3L+LMU68RImFqkPCPC8UOU/4dA3p53QqxzaUq2PwbklnKyxXM v5q66Ec3HVnENOXefi7jJkpRWm/IH9YEV8/9DsohcjgEViZJbfBVcBkO8xG/nSXyPTjM 69Jg== X-Gm-Message-State: AOJu0YwqW8phYrbMMHWuNa6CwOH6kS9QOk64nxNH6APMG7QzLRP72MzI CWSR6OipVkLPeKXLNRLRJ5Wu7GKfQsJ28MOgnz3uwg== X-Google-Smtp-Source: AGHT+IGRMLVlMvZ7wpMVOyssQqGop6nn3tHJCZCoJ31ASMGB0eazKa8jd5uFYiTjKvf/0jCBHpi7uQ== X-Received: by 2002:a05:6a20:258a:b0:161:76a4:4f79 with SMTP id k10-20020a056a20258a00b0016176a44f79mr2379434pzd.23.1698147447128; Tue, 24 Oct 2023 04:37:27 -0700 (PDT) Received: from mandiga.. ([2804:1b3:a7c3:a647:44d5:84b0:a3f2:fe73]) by smtp.gmail.com with ESMTPSA id k28-20020aa79d1c000000b006bde2480806sm7506663pfp.47.2023.10.24.04.37.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Oct 2023 04:37:26 -0700 (PDT) From: Adhemerval Zanella To: libc-alpha@sourceware.org Cc: Bruno Haible Subject: [PATCH v2 2/3] i686: Do not raise exception traps on fesetexcept (BZ 30989) Date: Tue, 24 Oct 2023 08:37:15 -0300 Message-Id: <20231024113716.3911015-3-adhemerval.zanella@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231024113716.3911015-1-adhemerval.zanella@linaro.org> References: <20231024113716.3911015-1-adhemerval.zanella@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: libc-alpha-bounces+incoming=patchwork.ozlabs.org@sourceware.org According to ISO C23 (7.6.4.4), fesetexcept is supposed to set floating-point exception flags without raising a trap (unlike feraiseexcept, which is supposed to raise a trap if feenableexcept was called with the appropriate argument). The flags can be set in the 387 unit or in the SSE unit. To set a flag, it is sufficient to do it in the SSE unit, because that is guaranteed to not trap. However, on i386 CPUs that have only a 387 unit, set the flags in the 387, as long as this cannot trap. Checked on i686-linux-gnu. --- math/test-fesetexcept-traps.c | 11 +++++++ sysdeps/i386/fpu/fesetexcept.c | 41 +++++++++++++++++++++--- sysdeps/i386/fpu/math-tests-trap-force.h | 29 +++++++++++++++++ 3 files changed, 77 insertions(+), 4 deletions(-) create mode 100644 sysdeps/i386/fpu/math-tests-trap-force.h diff --git a/math/test-fesetexcept-traps.c b/math/test-fesetexcept-traps.c index 96f6c4752f..2f63e9ba23 100644 --- a/math/test-fesetexcept-traps.c +++ b/math/test-fesetexcept-traps.c @@ -19,6 +19,7 @@ #include #include #include +#include static int do_test (void) @@ -43,6 +44,16 @@ do_test (void) where setting the exception might result in traps the function should return a nonzero value. */ ret = fesetexcept (FE_ALL_EXCEPT); + + /* Execute some floating-point operations, since on some CPUs exceptions + triggers a trap only at the next floating-point instruction. */ + volatile double a = 1.0; + volatile double b = a + a; + math_force_eval (b); + volatile long double al = 1.0L; + volatile long double bl = al + al; + math_force_eval (bl); + if (ret == 0) puts ("fesetexcept (FE_ALL_EXCEPT) succeeded"); else if (!EXCEPTION_SET_FORCES_TRAP) diff --git a/sysdeps/i386/fpu/fesetexcept.c b/sysdeps/i386/fpu/fesetexcept.c index 18949e982a..6eeb5ab5b0 100644 --- a/sysdeps/i386/fpu/fesetexcept.c +++ b/sysdeps/i386/fpu/fesetexcept.c @@ -17,15 +17,48 @@ . */ #include +#include int fesetexcept (int excepts) { - fenv_t temp; + /* The flags can be set in the 387 unit or in the SSE unit. To set a flag, + it is sufficient to do it in the SSE unit, because that is guaranteed to + not trap. However, on i386 CPUs that have only a 387 unit, set the flags + in the 387, as long as this cannot trap. */ - __asm__ ("fnstenv %0" : "=m" (*&temp)); - temp.__status_word |= excepts & FE_ALL_EXCEPT; - __asm__ ("fldenv %0" : : "m" (*&temp)); + excepts &= FE_ALL_EXCEPT; + + if (CPU_FEATURE_USABLE (SSE)) + { + /* And now similarly for SSE. */ + unsigned int mxcsr; + __asm__ ("stmxcsr %0" : "=m" (*&mxcsr)); + + /* Set relevant flags. */ + mxcsr |= excepts; + + /* Put the new data in effect. */ + __asm__ ("ldmxcsr %0" : : "m" (*&mxcsr)); + } + else + { + fenv_t temp; + + __asm__ ("fnstenv %0" : "=m" (*&temp)); + + /* Clear or set relevant flags. */ + temp.__status_word |= temp.__status_word & excepts; + + if ((~temp.__control_word) & excepts) + /* Setting the exception flags may trigger a trap (at the next + floating-point instruction, but that does not matter). + ISO C23 (7.6.4.4) does not allow it. */ + return -1; + + /* Store the new status word (along with the rest of the environment). */ + __asm__ ("fldenv %0" : : "m" (*&temp)); + } return 0; } diff --git a/sysdeps/i386/fpu/math-tests-trap-force.h b/sysdeps/i386/fpu/math-tests-trap-force.h new file mode 100644 index 0000000000..20f4ead98d --- /dev/null +++ b/sysdeps/i386/fpu/math-tests-trap-force.h @@ -0,0 +1,29 @@ +/* Configuration for math tests: support for setting exception flags + without causing enabled traps. i686 version. + Copyright (C) 2023 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#ifndef I386_FPU_MATH_TESTS_TRAP_FORCE_H +#define I386_FPU_MATH_TESTS_TRAP_FORCE_H 1 + +#include + +/* Setting exception flags in FPU Status Register results in enabled traps for + those exceptions being taken. */ +#define EXCEPTION_SET_FORCES_TRAP (CPU_FEATURE_USABLE (SSE)) + +#endif /* math-tests-trap-force.h. */ From patchwork Tue Oct 24 11:37:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Adhemerval Zanella Netto X-Patchwork-Id: 1854332 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=QhMAr61D; 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([2804:1b3:a7c3:a647:44d5:84b0:a3f2:fe73]) by smtp.gmail.com with ESMTPSA id k28-20020aa79d1c000000b006bde2480806sm7506663pfp.47.2023.10.24.04.38.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Oct 2023 04:38:49 -0700 (PDT) From: Adhemerval Zanella To: libc-alpha@sourceware.org Cc: Bruno Haible Subject: [PATCH v2 3/3] x86: Do not raises floating-point exception traps on fesetexceptflag (BZ 30990) Date: Tue, 24 Oct 2023 08:37:16 -0300 Message-Id: <20231024113716.3911015-4-adhemerval.zanella@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231024113716.3911015-1-adhemerval.zanella@linaro.org> References: <20231024113716.3911015-1-adhemerval.zanella@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: libc-alpha-bounces+incoming=patchwork.ozlabs.org@sourceware.org From: Bruno Haible According to ISO C23 (7.6.4.4), fesetexcept is supposed to set floating-point exception flags without raising a trap (unlike feraiseexcept, which is supposed to raise a trap if feenableexcept was called with the appropriate argument). The flags can be set in the 387 unit or in the SSE unit. When we need to clear a flag, we need to do so in both units, due to the way fetestexcept is implemented. When we need to set a flag, it is sufficient to do it in the SSE unit, because that is guaranteed to not trap. However, on i386 CPUs that have only a 387 unit, set the flags in the 387, as long as this cannot trap. Co-authored-by: Adhemerval Zanella --- math/test-fexcept-traps.c | 11 ++++++ sysdeps/i386/fpu/fsetexcptflg.c | 58 ++++++++++++++++++++----------- sysdeps/x86_64/fpu/fsetexcptflg.c | 24 +++++++------ 3 files changed, 62 insertions(+), 31 deletions(-) diff --git a/math/test-fexcept-traps.c b/math/test-fexcept-traps.c index 9b8f583ae6..f10bf2d9a3 100644 --- a/math/test-fexcept-traps.c +++ b/math/test-fexcept-traps.c @@ -19,6 +19,7 @@ #include #include #include +#include static int do_test (void) @@ -67,6 +68,16 @@ do_test (void) where setting the exception might result in traps the function should return a nonzero value. */ ret = fesetexceptflag (&saved, FE_ALL_EXCEPT); + + /* Execute some floating-point operations, since on some CPUs exceptions + triggers a trap only at the next floating-point instruction. */ + volatile double a = 1.0; + volatile double b = a + a; + math_force_eval (b); + volatile long double al = 1.0L; + volatile long double bl = al + al; + math_force_eval (bl); + if (ret != 0 && !EXCEPTION_SET_FORCES_TRAP) { puts ("fesetexceptflag failed"); diff --git a/sysdeps/i386/fpu/fsetexcptflg.c b/sysdeps/i386/fpu/fsetexcptflg.c index e724b7d6fd..ccbcf35e8e 100644 --- a/sysdeps/i386/fpu/fsetexcptflg.c +++ b/sysdeps/i386/fpu/fsetexcptflg.c @@ -17,42 +17,58 @@ . */ #include -#include -#include #include -#include int __fesetexceptflag (const fexcept_t *flagp, int excepts) { - fenv_t temp; + /* The flags can be set in the 387 unit or in the SSE unit. When we need to + clear a flag, we need to do so in both units, due to the way fetestexcept + is implemented. + When we need to set a flag, it is sufficient to do it in the SSE unit, + because that is guaranteed to not trap. However, on i386 CPUs that have + only a 387 unit, set the flags in the 387, as long as this cannot trap. */ - /* Get the current environment. We have to do this since we cannot - separately set the status word. */ - __asm__ ("fnstenv %0" : "=m" (*&temp)); + fenv_t temp; - temp.__status_word &= ~(excepts & FE_ALL_EXCEPT); - temp.__status_word |= *flagp & excepts & FE_ALL_EXCEPT; + excepts &= FE_ALL_EXCEPT; - /* Store the new status word (along with the rest of the environment. - Possibly new exceptions are set but they won't get executed unless - the next floating-point instruction. */ - __asm__ ("fldenv %0" : : "m" (*&temp)); + /* Get the current x87 FPU environment. We have to do this since we + cannot separately set the status word. */ + __asm__ ("fnstenv %0" : "=m" (*&temp)); - /* If the CPU supports SSE, we set the MXCSR as well. */ if (CPU_FEATURE_USABLE (SSE)) { - unsigned int xnew_exc; + unsigned int mxcsr; + + /* Clear relevant flags. */ + temp.__status_word &= ~(excepts & ~ *flagp); - /* Get the current MXCSR. */ - __asm__ ("stmxcsr %0" : "=m" (*&xnew_exc)); + /* Store the new status word (along with the rest of the environment). */ + __asm__ ("fldenv %0" : : "m" (*&temp)); - /* Set the relevant bits. */ - xnew_exc &= ~(excepts & FE_ALL_EXCEPT); - xnew_exc |= *flagp & excepts & FE_ALL_EXCEPT; + /* And now similarly for SSE. */ + __asm__ ("stmxcsr %0" : "=m" (*&mxcsr)); + + /* Clear or set relevant flags. */ + mxcsr ^= (mxcsr ^ *flagp) & excepts; /* Put the new data in effect. */ - __asm__ ("ldmxcsr %0" : : "m" (*&xnew_exc)); + __asm__ ("ldmxcsr %0" : : "m" (*&mxcsr)); + } + else + { + /* Clear or set relevant flags. */ + temp.__status_word ^= (temp.__status_word ^ *flagp) & excepts; + + if ((~temp.__control_word) & temp.__status_word & excepts) + /* Setting the exception flags may trigger a trap (at the next + floating-point instruction, but that does not matter). + ISO C 23 § 7.6.4.5 does not allow it. */ + return -1; + + /* Store the new status word (along with the rest of the environment). */ + __asm__ ("fldenv %0" : : "m" (*&temp)); } /* Success. */ diff --git a/sysdeps/x86_64/fpu/fsetexcptflg.c b/sysdeps/x86_64/fpu/fsetexcptflg.c index a3ac1dea01..2ce2b509f2 100644 --- a/sysdeps/x86_64/fpu/fsetexcptflg.c +++ b/sysdeps/x86_64/fpu/fsetexcptflg.c @@ -22,30 +22,34 @@ int fesetexceptflag (const fexcept_t *flagp, int excepts) { + /* The flags can be set in the 387 unit or in the SSE unit. + When we need to clear a flag, we need to do so in both units, + due to the way fetestexcept() is implemented. + When we need to set a flag, it is sufficient to do it in the SSE unit, + because that is guaranteed to not trap. */ + fenv_t temp; unsigned int mxcsr; - /* XXX: Do we really need to set both the exception in both units? - Shouldn't it be enough to set only the SSE unit? */ + excepts &= FE_ALL_EXCEPT; /* Get the current x87 FPU environment. We have to do this since we cannot separately set the status word. */ __asm__ ("fnstenv %0" : "=m" (*&temp)); - temp.__status_word &= ~(excepts & FE_ALL_EXCEPT); - temp.__status_word |= *flagp & excepts & FE_ALL_EXCEPT; + /* Clear relevant flags. */ + temp.__status_word &= ~(excepts & ~ *flagp); - /* Store the new status word (along with the rest of the environment. - Possibly new exceptions are set but they won't get executed unless - the next floating-point instruction. */ + /* Store the new status word (along with the rest of the environment). */ __asm__ ("fldenv %0" : : "m" (*&temp)); - /* And now the same for SSE. */ + /* And now similarly for SSE. */ __asm__ ("stmxcsr %0" : "=m" (*&mxcsr)); - mxcsr &= ~(excepts & FE_ALL_EXCEPT); - mxcsr |= *flagp & excepts & FE_ALL_EXCEPT; + /* Clear or set relevant flags. */ + mxcsr ^= (mxcsr ^ *flagp) & excepts; + /* Put the new data in effect. */ __asm__ ("ldmxcsr %0" : : "m" (*&mxcsr)); /* Success. */