From patchwork Mon Oct 23 07:22:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 1853525 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=irq.a4lg.com header.i=@irq.a4lg.com header.a=rsa-sha256 header.s=2017s01 header.b=f7f3Qi2f; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SDRX003t6z23jV for ; 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charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 1853526 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=irq.a4lg.com header.i=@irq.a4lg.com header.a=rsa-sha256 header.s=2017s01 header.b=DIRBwGXS; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SDRXH2yPDz23jV for ; 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a=rsa-sha256; d=sourceware.org; s=key; t=1698045854; c=relaxed/simple; bh=TPJyI7T6QGh26ngygK2EMlwu0c0W51fIvfuzy4QlDb8=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:Mime-Version; b=cAdB/EoeLxR1IodhXnUyXshWuFFsQRt62SurQwkq6d9C3kdwfvA21EQzv3Zqh8vwmDBGYsq2kZcWuaYjdR5jNxJBSNwhKYsOsCZRDrrDrOE04JTYK4KtqziAwEo++yIiTJnskDXmrgcmYjeYoRbnlAnMov9wLphqWR1uqsGtArI= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 10C63300089; Mon, 23 Oct 2023 07:24:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=irq.a4lg.com; s=2017s01; t=1698045851; bh=/sByrfCqrpew7oPmI2LSfvIOCwoFsZr3LOzXBRvp3Pw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Mime-Version:Content-Transfer-Encoding; b=DIRBwGXSUesomGE6HoT1LGKNp7q4arJ9LJE4UQyHjEh3wAwmhXD0BSvpiBsmwcLOD HlUTQV7jiUkHNl9v339ZjV9OgHeey05ayARbukrumsP23cGpQDokf8J7xk+wkIiNEg Jr5EgmQF+MuLcn7pZUmwhi0/ZRrN/2sbjaHwfAAk= From: Tsukasa OI To: Tsukasa OI , Kito Cheng , Palmer Dabbelt , Andrew Waterman , Jim Wilson , Jeff Law Cc: gcc-patches@gcc.gnu.org Subject: [PATCH 2/4] RISC-V: Remove broken __builtin_riscv_zicbop_cbo_prefetchi Date: Mon, 23 Oct 2023 07:22:53 +0000 Message-ID: <68ebe422ceb2c408006b2acab94de569cf8d0e78.1698045769.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, KAM_MANYTO, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org From: Tsukasa OI __builtin_riscv_zicbop_cbo_prefetchi (corresponding "prefetch.i" instruction from the 'Zicbop' extension) is completely broken (not even functional) and should be removed rather than fixing it because it has no good way to "fix" this built-in function. gcc/ChangeLog: * config/riscv/riscv-cmo.def (__builtin_riscv_zicbop_cbo_prefetchi): Remove since it's broken. * config/riscv/riscv.md (unspecv) Remove UNSPECV_PREI. (riscv_prefetchi_): Remove. gcc/testsuite/ChangeLog: * gcc.target/riscv/cmo-zicbop-1.c: Remove references to __builtin_riscv_zicbop_cbo_prefetchi. * gcc.target/riscv/cmo-zicbop-2.c: Ditto with minor tidying. --- gcc/config/riscv/riscv-cmo.def | 4 ---- gcc/config/riscv/riscv.md | 9 --------- gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c | 6 ------ gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c | 8 +------- 4 files changed, 1 insertion(+), 26 deletions(-) diff --git a/gcc/config/riscv/riscv-cmo.def b/gcc/config/riscv/riscv-cmo.def index 017370d1d0e3..dbd5d2f0d9eb 100644 --- a/gcc/config/riscv/riscv-cmo.def +++ b/gcc/config/riscv/riscv-cmo.def @@ -12,10 +12,6 @@ RISCV_BUILTIN (inval_di, "zicbom_cbo_inval", RISCV_BUILTIN_DIRECT_NO_TARGET, RIS RISCV_BUILTIN (zero_si, "zicboz_cbo_zero", RISCV_BUILTIN_DIRECT_NO_TARGET, RISCV_VOID_FTYPE_VOID_PTR, zero32), RISCV_BUILTIN (zero_di, "zicboz_cbo_zero", RISCV_BUILTIN_DIRECT_NO_TARGET, RISCV_VOID_FTYPE_VOID_PTR, zero64), -// zicbop -RISCV_BUILTIN (prefetchi_si, "zicbop_cbo_prefetchi", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI, prefetch32), -RISCV_BUILTIN (prefetchi_di, "zicbop_cbo_prefetchi", RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UDI, prefetch64), - // zbkc or zbc RISCV_BUILTIN (clmul_si, "clmul", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, clmul_zbkc32_or_zbc32), RISCV_BUILTIN (clmul_di, "clmul", RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UDI_UDI, clmul_zbkc64_or_zbc64), diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 23d91331290b..4b445cb8be9c 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -118,7 +118,6 @@ UNSPECV_FLUSH UNSPECV_INVAL UNSPECV_ZERO - UNSPECV_PREI ;; Zihintpause unspec UNSPECV_PAUSE @@ -3493,14 +3492,6 @@ } [(set_attr "type" "cbo")]) -(define_insn "riscv_prefetchi_" - [(unspec_volatile:X [(match_operand:X 0 "address_operand" "r") - (match_operand:X 1 "imm5_operand" "i")] - UNSPECV_PREI)] - "TARGET_ZICBOP" - "prefetch.i\t%a0" - [(set_attr "type" "cbo")]) - (define_expand "extv" [(set (match_operand:GPR 0 "register_operand" "=r") (sign_extract:GPR (match_operand:GPR 1 "register_operand" "r") diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c index c5d78c1763d3..54b764fb7452 100644 --- a/gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c +++ b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c @@ -13,11 +13,5 @@ void foo (char *p) __builtin_prefetch (p, 1, 3); } -int foo1() -{ - return __builtin_riscv_zicbop_cbo_prefetchi(1); -} - -/* { dg-final { scan-assembler-times "prefetch.i" 1 } } */ /* { dg-final { scan-assembler-times "prefetch.r" 4 } } */ /* { dg-final { scan-assembler-times "prefetch.w" 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c index 6576365b39ca..917adc8f2008 100644 --- a/gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c +++ b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c @@ -13,11 +13,5 @@ void foo (char *p) __builtin_prefetch (p, 1, 3); } -int foo1() -{ - return __builtin_riscv_zicbop_cbo_prefetchi(1); -} - -/* { dg-final { scan-assembler-times "prefetch.i" 1 } } */ /* { dg-final { scan-assembler-times "prefetch.r" 4 } } */ -/* { dg-final { scan-assembler-times "prefetch.w" 4 } } */ +/* { dg-final { scan-assembler-times "prefetch.w" 4 } } */ From patchwork Mon Oct 23 07:22:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 1853527 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=irq.a4lg.com header.i=@irq.a4lg.com header.a=rsa-sha256 header.s=2017s01 header.b=FjhUB2rE; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; 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a=rsa-sha256; c=relaxed/relaxed; d=irq.a4lg.com; s=2017s01; t=1698045862; bh=baZMWkKRMJpeNY03YCW/twmY2XfmpZXdY8XXe8UKWZE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Mime-Version:Content-Transfer-Encoding; b=FjhUB2rE7OE5pgyI61ngIlJSwxOzcjppYBT/rA4AmS29O2RcWcnOjwy2RlCmunp7K 90EFpahyPsxhYlCP6Sn0Y/sSEnikOWSaTfdBtiR/AWER+lT5+TYK2vee6pFe/oJyMo BXlaJ2dUMsbQT85rXUMzjYQCoqV+L6qOu3S+19d0= From: Tsukasa OI To: Tsukasa OI , Kito Cheng , Palmer Dabbelt , Andrew Waterman , Jim Wilson , Jeff Law Cc: gcc-patches@gcc.gnu.org Subject: [PATCH 3/4] RISC-V: Add not broken RW prefetch RTL instructions without offsets Date: Mon, 23 Oct 2023 07:22:54 +0000 Message-ID: <671a5e3bc2ca33b9050c54d2f53dd0580339b858.1698045769.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, KAM_MANYTO, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org From: Tsukasa OI To prepare adding new not broken prefetch built-in functions and fixing an ICE in __builtin_prefetch, this commit adds two new instructions, each corresponding a 'Zicbop' prefetch hint instruction, but with no specifiable offset field for simplicity. This commit also excludes new instruction corresponding "prefetch.i" because it is not needed to fix an ICE (so new instruction corresponding "prefetch.i" is going to be a separate commit). gcc/ChangeLog: * config/riscv/riscv.md (unspecv) Add UNSPECV_PREFETCH_[RW]. (riscv_prefetch_w_, riscv_prefetch_w_): New. --- gcc/config/riscv/riscv.md | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 4b445cb8be9c..e67a6d1f1b81 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -118,6 +118,8 @@ UNSPECV_FLUSH UNSPECV_INVAL UNSPECV_ZERO + UNSPECV_PREFETCH_R + UNSPECV_PREFETCH_W ;; Zihintpause unspec UNSPECV_PAUSE @@ -3492,6 +3494,20 @@ } [(set_attr "type" "cbo")]) +(define_insn "riscv_prefetch_r_" + [(unspec_volatile:X [(match_operand:X 0 "register_operand" "r")] + UNSPECV_PREFETCH_R)] + "TARGET_ZICBOP" + "prefetch.r\t0(%0)" + [(set_attr "type" "cbo")]) + +(define_insn "riscv_prefetch_w_" + [(unspec_volatile:X [(match_operand:X 0 "register_operand" "r")] + UNSPECV_PREFETCH_W)] + "TARGET_ZICBOP" + "prefetch.w\t0(%0)" + [(set_attr "type" "cbo")]) + (define_expand "extv" [(set (match_operand:GPR 0 "register_operand" "=r") (sign_extract:GPR (match_operand:GPR 1 "register_operand" "r") From patchwork Mon Oct 23 07:22:55 2023 Content-Type: text/plain; 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Mon, 23 Oct 2023 18:25:00 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 8DF8C3864862 for ; Mon, 23 Oct 2023 07:24:48 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id A3E6F3861918 for ; Mon, 23 Oct 2023 07:24:34 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A3E6F3861918 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=irq.a4lg.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=irq.a4lg.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org A3E6F3861918 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2401:2500:203:30b:4000:6bfe:4757:0 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698045876; cv=none; b=pG8GQEb1x6NZ+IsRy8y04u2PIA0lEKORBJfKk7OawSUla2PimbdQb1HBofS1Xj9lC1rhc8n+QTMNtDH6yzY3ZoPRbU6TmwSYBWQxkQhfgA3hl+a8kvBYLybIPQVNP6nO26bJ/NGpIk28eh5WErCWaYKt/8gFCV1eDamQENkFMg8= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698045876; c=relaxed/simple; bh=XZVf9qy/8MX4/4GW09e02M0gVhNIo/qJAPoiUXWhoP0=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:Mime-Version; b=BmGUPCAAsoqp7n8x51+gqnyluXPxhskMZr7XOwm2gOzNFqObwXzgmvibOkeaKfMRkSh4f4lef+WmfJtnFgOmsuyz5grXvzv39PFY5QG7uwKfJUiEg1SrF4P0OedXQ7O9hvUQz6nQasN/INrmP5NO+uQCFGb1rC8MK/VEQCg4KG4= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 92791300089; Mon, 23 Oct 2023 07:24:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=irq.a4lg.com; s=2017s01; t=1698045872; bh=wXpO+y3EjFiyaydSnnRbwAJYTwxX7PmnveCKXJbYPU0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Mime-Version:Content-Transfer-Encoding; b=rWEIOCZj60d4ZIN96TVGkt2F3gBHMvXZGUYPQp+0BCtDuz9xp6Mz8K9r2cJRU5Pmo WPEpiqucVD7hfy4nexUMw/bHnqbBUnMxhnNEqHYSyWR2XnknK5pHKSq/najg2u8eVV +iBEn595QGUeshPV+GWxwOUC0ezU8wTIG/v+ehTo= From: Tsukasa OI To: Tsukasa OI , Kito Cheng , Palmer Dabbelt , Andrew Waterman , Jim Wilson , Jeff Law Cc: gcc-patches@gcc.gnu.org Subject: [PATCH 4/4] RISC-V: Fix ICE by expansion and register coercion Date: Mon, 23 Oct 2023 07:22:55 +0000 Message-ID: In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, KAM_MANYTO, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org From: Tsukasa OI A "prefetch" instruction on RISC-V GCC emits a machine hint instruction directly when the 'Zicbop' extension is enabled but it could cause an ICE when the address argument of __builtin_prefetch is an integral constant (such like 0 [NULL] or some other [but possibly not all] fixed addresses). This is caused by the fact that the "r" constraint is not actually checked and something other than a register can be the first argument of the "prefetch" RTL instruction. It fixes the problem by changing "prefetch" from a native instruction to an expansion and coercing the address to a register there. gcc/ChangeLog: * config/riscv/riscv.md (prefetch): Expand to a native prefetch instruction instead of emitting a machine instruction directly. Coerce the address argument into a register. gcc/testsuite/ChangeLog: * gcc.target/riscv/cmo-zicbop-by-common-ice-1.c: New ICE test. * gcc.target/riscv/cmo-zicbop-by-common-ice-2.c: Ditto. --- gcc/config/riscv/riscv.md | 43 ++++++++++++------- .../riscv/cmo-zicbop-by-common-ice-1.c | 13 ++++++ .../riscv/cmo-zicbop-by-common-ice-2.c | 7 +++ 3 files changed, 48 insertions(+), 15 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbop-by-common-ice-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbop-by-common-ice-2.c diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index e67a6d1f1b81..bf232345b1ab 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -3479,21 +3479,6 @@ [(set_attr "type" "cbo")] ) -(define_insn "prefetch" - [(prefetch (match_operand 0 "address_operand" "r") - (match_operand 1 "imm5_operand" "i") - (match_operand 2 "const_int_operand" "n"))] - "TARGET_ZICBOP" -{ - switch (INTVAL (operands[1])) - { - case 0: return "prefetch.r\t%a0"; - case 1: return "prefetch.w\t%a0"; - default: gcc_unreachable (); - } -} - [(set_attr "type" "cbo")]) - (define_insn "riscv_prefetch_r_" [(unspec_volatile:X [(match_operand:X 0 "register_operand" "r")] UNSPECV_PREFETCH_R)] @@ -3508,6 +3493,34 @@ "prefetch.w\t0(%0)" [(set_attr "type" "cbo")]) +(define_expand "prefetch" + [(prefetch (match_operand 0 "address_operand" "") + (match_operand 1 "const_int_operand" "") + (match_operand 2 "const_int_operand" ""))] + "TARGET_ZICBOP" +{ + operands[0] = force_reg (Pmode, operands[0]); + switch (INTVAL (operands[1])) + { + case 0: + if (TARGET_64BIT) + emit_insn (gen_riscv_prefetch_r_di (operands[0])); + else + emit_insn (gen_riscv_prefetch_r_si (operands[0])); + break; + case 1: + if (TARGET_64BIT) + emit_insn (gen_riscv_prefetch_w_di (operands[0])); + else + emit_insn (gen_riscv_prefetch_w_si (operands[0])); + break; + default: + gcc_unreachable (); + } + DONE; +} + [(set_attr "type" "cbo")]) + (define_expand "extv" [(set (match_operand:GPR 0 "register_operand" "=r") (sign_extract:GPR (match_operand:GPR 1 "register_operand" "r") diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicbop-by-common-ice-1.c b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-by-common-ice-1.c new file mode 100644 index 000000000000..47e83f29cc5c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-by-common-ice-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32i_zicbop -mabi=ilp32" } */ + +void foo (void) +{ + /* Second argument defaults to zero (read). */ + __builtin_prefetch (0); + __builtin_prefetch (0, 0); + __builtin_prefetch (0, 1); +} + +/* { dg-final { scan-assembler-times "prefetch\\.r" 2 } } */ +/* { dg-final { scan-assembler-times "prefetch\\.w" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicbop-by-common-ice-2.c b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-by-common-ice-2.c new file mode 100644 index 000000000000..a245b8163c1f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-by-common-ice-2.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64i_zicbop -mabi=lp64" } */ + +#include "cmo-zicbop-by-common-ice-1.c" + +/* { dg-final { scan-assembler-times "prefetch\\.r" 2 } } */ +/* { dg-final { scan-assembler-times "prefetch\\.w" 1 } } */