From patchwork Wed Oct 11 05:15:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?6ZKf5bGF5ZOy?= X-Patchwork-Id: 1846213 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4S51F03mzjz1yq4 for ; Wed, 11 Oct 2023 16:15:32 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 3B2AA3857707 for ; Wed, 11 Oct 2023 05:15:30 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgau1.qq.com (smtpbgau1.qq.com [54.206.16.166]) by sourceware.org (Postfix) with ESMTPS id 5868E3858C41 for ; Wed, 11 Oct 2023 05:15:12 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 5868E3858C41 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp72t1697001305tgk8v0ly Received: from rios-cad121.hadoop.rioslab.org ( [58.60.1.9]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 11 Oct 2023 13:15:04 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: KvvwR/hcPA1oFZzyvtZsOkDriAa1WBZ4ZEQTwjPgduH/Wn8L22N0HUXeWaiW+ zbZ+qP8rbHX/WmgZjRwPKDhBisDs4vkWlvCt+wX5zeVJKhGi6Oi+Nf+qEVSq7rGNDrtba9Y BNFv3M1m/0anhcWlREwXZxEb1U+mwA5W1ApRwDeSFpXNvS/tG+9hFyEf1xDsL9TWQBCmAhm DgfrlWooS5YDeN0JdXOfN9HgobBxEHlOy8wDn7bPFBBKKn5k0vKVZeb8B8hU+Bkis9qAkme fPl2QcR2Z5Yr4PsVj1LMeAYqC8zcrJNOPmI8huy5Q7cJokEdB5rW7A7HLv5oC/fRcanDKoP jSgDCWzNEDr6Pehp/+MKdG5pmtSMSl0zetacAGaKeVSA76Vd43DGtdmfVKwGRnRl4ly1aRF bEjQhdeIkt4= X-QQ-GoodBg: 2 X-BIZMAIL-ID: 1404599850130578282 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, kito.cheng@sifive.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Juzhe-Zhong Subject: [PATCH] RISC-V: Enable full coverage vect tests Date: Wed, 11 Oct 2023 13:15:02 +0800 Message-Id: <20231011051502.1695577-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org I have analyzed all existing FAILs. Except these following FAILs need to be addressed: FAIL: gcc.dg/vect/slp-reduc-7.c -flto -ffat-lto-objects execution test FAIL: gcc.dg/vect/slp-reduc-7.c execution test FAIL: gcc.dg/vect/vect-cond-arith-2.c -flto -ffat-lto-objects scan-tree-dump optimized " = \\.COND_(LEN_)?SUB" FAIL: gcc.dg/vect/vect-cond-arith-2.c scan-tree-dump optimized " = \\.COND_(LEN_)?SUB" All other FAILs are dumple fail can be ignored (Confirm ARM SVE also has such FAILs and didn't fix them on either tests or implementation). Now, It's time to enable full coverage vect tests including vec_unpack, vec_pack, vec_interleave, ... etc. To see what we are still missing: Before this patch: === gcc Summary === # of expected passes 182839 # of unexpected failures 79 # of unexpected successes 11 # of expected failures 1275 # of unresolved testcases 4 # of unsupported tests 4223 After this patch: === gcc Summary === # of expected passes 183411 # of unexpected failures 93 # of unexpected successes 7 # of expected failures 1285 # of unresolved testcases 4 # of unsupported tests 4157 There is an important issue increased that I have noticed after this patch: FAIL: gcc.dg/vect/vect-gather-1.c -flto -ffat-lto-objects scan-tree-dump vect "Loop contains only SLP stmts" FAIL: gcc.dg/vect/vect-gather-1.c scan-tree-dump vect "Loop contains only SLP stmts" FAIL: gcc.dg/vect/vect-gather-3.c -flto -ffat-lto-objects scan-tree-dump vect "Loop contains only SLP stmts" FAIL: gcc.dg/vect/vect-gather-3.c scan-tree-dump vect "Loop contains only SLP stmts" It has a related PR: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111721 I am gonna fix this first in the middle-end after commit this patch. Ok for trunk ? gcc/testsuite/ChangeLog: * lib/target-supports.exp: Add RVV. --- gcc/testsuite/lib/target-supports.exp | 45 ++++++++++++++++++++------- 1 file changed, 33 insertions(+), 12 deletions(-) diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index b454b07359a..8037dbcee53 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -7876,7 +7876,9 @@ proc check_effective_target_vect_sdot_qi { } { || [istarget aarch64*-*-*] || [istarget arm*-*-*] || ([istarget mips*-*-*] - && [et-is-effective-target mips_msa]) }}] + && [et-is-effective-target mips_msa]) + || ([istarget riscv*-*-*] + && [check_effective_target_riscv_v]) }}] } # Return 1 if the target plus current options supports a vector @@ -7891,7 +7893,9 @@ proc check_effective_target_vect_udot_qi { } { || [istarget arm*-*-*] || [istarget ia64-*-*] || ([istarget mips*-*-*] - && [et-is-effective-target mips_msa]) }}] + && [et-is-effective-target mips_msa]) + || ([istarget riscv*-*-*] + && [check_effective_target_riscv_v]) }}] } # Return 1 if the target plus current options supports a vector @@ -7918,7 +7922,9 @@ proc check_effective_target_vect_sdot_hi { } { || [istarget ia64-*-*] || [istarget i?86-*-*] || [istarget x86_64-*-*] || ([istarget mips*-*-*] - && [et-is-effective-target mips_msa]) }}] + && [et-is-effective-target mips_msa]) + || ([istarget riscv*-*-*] + && [check_effective_target_riscv_v]) }}] } # Return 1 if the target plus current options supports a vector @@ -7930,7 +7936,9 @@ proc check_effective_target_vect_udot_hi { } { return [check_cached_effective_target_indexed vect_udot_hi { expr { ([istarget powerpc*-*-*] && ![istarget powerpc-*-linux*paired*]) || ([istarget mips*-*-*] - && [et-is-effective-target mips_msa]) }}] + && [et-is-effective-target mips_msa]) + || ([istarget riscv*-*-*] + && [check_effective_target_riscv_v]) }}] } # Return 1 if the target plus current options supports a vector @@ -7945,7 +7953,9 @@ proc check_effective_target_vect_usad_char { } { || ([istarget aarch64*-*-*] && ![check_effective_target_aarch64_sve]) || ([istarget powerpc*-*-*] - && [check_p9vector_hw_available])}}] + && [check_p9vector_hw_available]) + || ([istarget riscv*-*-*] + && [check_effective_target_riscv_v]) }}] } # Return 1 if the target plus current options supports both signed @@ -7971,8 +7981,10 @@ proc check_effective_target_vect_mulhrs_hi {} { # by power-of-2 operations on vectors of 4-byte integers. proc check_effective_target_vect_sdiv_pow2_si {} { - return [expr { [istarget aarch64*-*-*] - && [check_effective_target_aarch64_sve] }] + return [expr { ([istarget aarch64*-*-*] + && [check_effective_target_aarch64_sve]) + || ([istarget riscv*-*-*] + && [check_effective_target_riscv_v]) }] } # Return 1 if the target plus current options supports a vector @@ -7992,7 +8004,9 @@ proc check_effective_target_vect_pack_trunc { } { && [et-is-effective-target mips_msa]) || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) - || [istarget amdgcn*-*-*] }}] + || [istarget amdgcn*-*-*] + || ([istarget riscv*-*-*] + && [check_effective_target_riscv_v]) }}] } # Return 1 if the target plus current options supports a vector @@ -8012,7 +8026,9 @@ proc check_effective_target_vect_unpack { } { && [check_effective_target_arm_little_endian]) || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) - || [istarget amdgcn*-*-*] }}] + || [istarget amdgcn*-*-*] + || ([istarget riscv*-*-*] + && [check_effective_target_riscv_v]) }}] } # Return 1 if the target plus current options does not guarantee @@ -8662,7 +8678,8 @@ proc check_effective_target_vect_masked_store { } { # Return 1 if the target supports vector gather loads via internal functions. proc check_effective_target_vect_gather_load_ifn { } { - return [expr { [check_effective_target_aarch64_sve] }] + return [expr { [check_effective_target_aarch64_sve] + || [check_effective_target_riscv_v] }] } # Return 1 if the target supports vector scatter stores. @@ -8816,7 +8833,9 @@ proc check_effective_target_vect_extract_even_odd { } { && ([et-is-effective-target mips_msa] || [et-is-effective-target mpaired_single])) || ([istarget s390*-*-*] - && [check_effective_target_s390_vx]) }}] + && [check_effective_target_s390_vx]) + || ([istarget riscv*-*-*] + && [check_effective_target_riscv_v]) }}] } # Return 1 if the target supports vector interleaving, 0 otherwise. @@ -8832,7 +8851,9 @@ proc check_effective_target_vect_interleave { } { && ([et-is-effective-target mpaired_single] || [et-is-effective-target mips_msa])) || ([istarget s390*-*-*] - && [check_effective_target_s390_vx]) }}] + && [check_effective_target_s390_vx]) + || ([istarget riscv*-*-*] + && [check_effective_target_riscv_v]) }}] } foreach N {2 3 4 5 6 7 8} {