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[92.12.225.146]) by smtp.gmail.com with ESMTPSA id t9-20020a5d4609000000b0031f8a59dbeasm2084336wrq.62.2023.10.05.08.57.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Oct 2023 08:57:19 -0700 (PDT) From: Peter Griffin To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, conor+dt@kernel.org, sboyd@kernel.org, tomasz.figa@gmail.com, s.nawrocki@samsung.com, linus.walleij@linaro.org, wim@linux-watchdog.org, linux@roeck-us.net, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, olof@lixom.net, cw00.choi@samsung.com Cc: peter.griffin@linaro.org, tudor.ambarus@linaro.org, andre.draszik@linaro.org, semen.protsenko@linaro.org, soc@kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-watchdog@vger.kernel.org Subject: [PATCH 01/21] dt-bindings: interrupt-controller: Add gs101 interrupt controller Date: Thu, 5 Oct 2023 16:55:58 +0100 Message-ID: <20231005155618.700312-2-peter.griffin@linaro.org> X-Mailer: git-send-email 2.42.0.582.g8ccd20d70d-goog In-Reply-To: <20231005155618.700312-1-peter.griffin@linaro.org> References: <20231005155618.700312-1-peter.griffin@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,UPPERCASE_50_75,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Add the gs101 SoC interrupt header that provides human readable constants for all the IRQs in the SoC. Signed-off-by: Peter Griffin --- .../dt-bindings/interrupt-controller/gs101.h | 758 ++++++++++++++++++ 1 file changed, 758 insertions(+) create mode 100644 include/dt-bindings/interrupt-controller/gs101.h diff --git a/include/dt-bindings/interrupt-controller/gs101.h b/include/dt-bindings/interrupt-controller/gs101.h new file mode 100644 index 000000000000..51c8eb54eca2 --- /dev/null +++ b/include/dt-bindings/interrupt-controller/gs101.h @@ -0,0 +1,758 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * This header provides constants for gs101 interrupt controller. + * + * Copyright 2019-2023 Google LLC + * + */ + +#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_GS101_H +#define _DT_BINDINGS_INTERRUPT_CONTROLLER_GS101_H + +#define ITNO IRQ_TYPE_NONE +#define ITER IRQ_TYPE_EDGE_RISING +#define ITEF IRQ_TYPE_EDGE_FALLING +#define ITEB IRQ_TYPE_EDGE_BOTH +#define ITLH IRQ_TYPE_LEVEL_HIGH +#define ITLL IRQ_TYPE_LEVEL_LOW + +#define IRQ_ALIVE_EINT0 0 +#define IRQ_ALIVE_EINT1 1 +#define IRQ_ALIVE_EINT2 2 +#define IRQ_ALIVE_EINT3 3 +#define IRQ_ALIVE_EINT4 4 +#define IRQ_ALIVE_EINT5 5 +#define IRQ_ALIVE_EINT6 6 +#define IRQ_ALIVE_EINT7 7 +#define IRQ_ALIVE_EINT8 8 +#define IRQ_ALIVE_EINT9 9 +#define IRQ_ALIVE_EINT10 10 +#define IRQ_ALIVE_EINT11 11 +#define IRQ_ALIVE_EINT12 12 +#define IRQ_ALIVE_EINT13 13 +#define IRQ_ALIVE_EINT14 14 +#define IRQ_ALIVE_EINT15 15 +#define IRQ_ALIVE_EINT16 16 +#define IRQ_ALIVE_EINT17 17 +#define IRQ_ALIVE_EINT18 18 +#define IRQ_ALIVE_EINT19 19 +#define IRQ_ALIVE_EINT20 20 +#define IRQ_ALIVE_EINT21 21 +#define IRQ_ALIVE_EINT22 22 +#define IRQ_ALIVE_EINT23 23 +#define IRQ_ALIVE_EINT24 24 +#define IRQ_ALIVE_EINT25 25 +#define IRQ_ALIVE_EINT26 26 +#define IRQ_ALIVE_EINT27 27 +#define IRQ_ALIVE_EINT28 28 +#define IRQ_ALIVE_EINT29 29 +#define IRQ_ALIVE_EINT30 30 +#define IRQ_ALIVE_EINT31 31 +#define IRQ_ALIVE_EINT32 32 +#define IRQ_ALIVE_EINT33 33 +#define IRQ_ALIVE_EINT34 34 +#define IRQ_ALIVE_EINT35 35 +#define IRQ_ALIVE_EINT36 36 +#define IRQ_ALIVE_EINT37 37 +#define IRQ_ALIVE_EINT38 38 +#define IRQ_ALIVE_EINT39 39 +#define IRQ_ALIVE_EINT40 40 +#define IRQ_ALIVE_EINT41 41 +#define IRQ_ALIVE_EINT42 42 +#define IRQ_ALIVE_EINT43 43 +#define IRQ_ALIVE_EINT44 44 +#define IRQ_ALIVE_EINT45 45 +#define IRQ_ALIVE_EINT46 46 +#define IRQ_ALIVE_EINT47 47 +#define IRQ_ALIVE_EINT48 48 +#define IRQ_ALIVE_EINT49 49 +#define IRQ_ALIVE_EINT50 50 +#define IRQ_ALIVE_EINT51 51 +#define IRQ_ALIVE_EINT52 52 +#define IRQ_ALIVE_EINT53 53 +#define IRQ_ALIVE_EINT54 54 +#define IRQ_ALIVE_EINT55 55 +#define IRQ_ALIVE_EINT56 56 +#define IRQ_ALIVE_EINT57 57 +#define IRQ_ALIVE_EINT58 58 +#define IRQ_ALIVE_EINT59 59 +#define IRQ_ALIVE_EINT60 60 +#define IRQ_ALIVE_EINT61 61 +#define IRQ_ALIVE_EINT62 62 +#define IRQ_ALIVE_EINT63 63 +#define IRQ_ALIVE_EINT64 64 +#define IRQ_ALIVE_EINT65 65 +#define IRQ_ALIVE_EINT66 66 +#define IRQ_APM_USI0_UART_ALIVE 67 +#define IRQ_APM_USI0_USI_ALIVE 68 +#define IRQ_APM_USI1_UART_ALIVE 69 +#define IRQ_COMB_SFI_CE_NONSECURE_SYSREG_APM_ALIVE 70 +#define IRQ_COMB_SFI_UCE_NONSECURE_SYSREG_APM_ALIVE 71 +#define IRQ_MAILBOX_AOC2AP_ALIVE 72 +#define IRQ_MAILBOX_APM2AP_ALIVE 73 +#define IRQ_MAILBOX_DBGCORE2AP_ALIVE 74 +#define IRQ_OCP_WARN_CPUCL1_ALIVE 75 +#define IRQ_OCP_WARN_CPUCL2_ALIVE 76 +#define IRQ_OCP_WARN_GPU_ALIVE 77 +#define IRQ_OCP_WARN_TPU_ALIVE 78 +#define IRQ_RTC_ALARM_INT_ALIVE 79 +#define IRQ_RTC_TIC_INT_0_ALIVE 80 +#define IRQ_SMPL_WARN_ALIVE 81 +#define IRQ_SOFT_OCP_WARN_CPUCL1_ALIVE 82 +#define IRQ_SOFT_OCP_WARN_CPUCL2_ALIVE 83 +#define IRQ_SOFT_OCP_WARN_GPU_ALIVE 84 +#define IRQ_SOFT_OCP_WARN_TPU_ALIVE 85 +#define IRQ_SPEEDY_APM_ALIVE 86 +#define IRQ_SPEEDY_SUB_APM_ALIVE 87 +#define IRQ_TRTC_ALARM_INT_ALIVE 88 +#define IRQ_TRTC_TIC_INT_0_ALIVE 89 +#define IRQ_VDROOP1_ALIVE 90 +#define IRQ_VDROOP2_ALIVE 91 +#define IRQ_WDT_APM_ALIVE 92 +#define IRQ_WDT_DBGCORE_ALIVE 93 +#define NONSEQINT__UASC_APM_ALIVE 94 +#define NONSEQINT__UASC_DBGCORE_ALIVE 95 +#define NONSEQINT__UASC_G_SWD_ALIVE 96 +#define NONSEQINT__UASC_P_AOCAPM_ALIVE 97 +#define NONSEQINT__UASC_P_APM_ALIVE 98 +#define O_INTERRUPT_S2__SYSMMU_D_APM_ALIVE 99 +#define TZINT__UASC_APM_ALIVE 100 +#define TZINT__UASC_DBGCORE_ALIVE 101 +#define TZINT__UASC_G_SWD_ALIVE 102 +#define TZINT__UASC_P_AOCAPM_ALIVE 103 +#define TZINT__UASC_P_APM_ALIVE 104 +#define INTR_AOC_PPMU_AOC 105 +#define INTR_AOCUSB_PPMU_AOC 106 +#define IRQ_AOC_TIMER0_AOC 107 +#define IRQ_AOC_Watchdog_CPU_AOC 108 +#define INTREQ_AOCPLL_LOCK_STATUS_AOC 109 +#define IRQ_SYSMMU_AOC_S1_NS_AOC 110 +#define IRQ_SYSMMU_AOC_S1_S_AOC 111 +#define IRQ_SYSMMU_AOC_S2_AOC 112 +#define IRQ_UASC_NS_AOC_AOC 113 +#define IRQ_UASC_S_AOC_AOC 114 +#define IRQ_BO_XINT_BO 115 +#define IRQ_PPMU_UPPER_OR_NORMAL_BO 116 +#define IRQ_SSMT_BO_BO 117 +#define IRQ_SYSMMU_S1_NS_BO_BO 118 +#define IRQ_SYSMMU_S1_S_BO_BO 119 +#define IRQ_SYSMMU_S2_BO_BO 120 +#define IRQ_UASC_NS_BO_BO 121 +#define IRQ_UASC_S_BO_BO 122 +#define IRQ_PPC_CYCLE_AOC_L_BUS0 123 +#define IRQ_PPC_CYCLE_AOC_UON_BUS0 124 +#define IRQ_PPC_EVENT_AOC_L_BUS0 125 +#define IRQ_PPC_EVENT_AOC_UON_BUS0 126 +#define IRQ_TREX_D_BUS0_debugInterrupt_BUS0 127 +#define IRQ_TREX_P_BUS0_debugInterrupt_BUS0 128 +#define IRQ_TREX_PPMU_BUS0M0_BUS0 129 +#define IRQ_TREX_D0_BUS1_debugInterrupt_BUS1 130 +#define IRQ_TREX_P_BUS1_debugInterrupt_BUS1 131 +#define IRQ_TREX_PPMU_BUS1M0_BUS1 132 +#define IRQ_TREX_PPMU_BUS1M1_BUS1 133 +#define IRQ_TREX_PPMU_BUS1M2_BUS1 134 +#define IRQ_TREX_PPMU_BUS1M3_BUS1 135 +#define IRQ_PPC_CYCLE_BUS2_L_BUS2 136 +#define IRQ_PPC_CYCLE_BUS2_UON_BUS2 137 +#define IRQ_PPC_CYCLE_G3D_L_BUS2 138 +#define IRQ_PPC_CYCLE_G3D_UON_BUS2 139 +#define IRQ_PPC_CYCLE_TPU_L_BUS2 140 +#define IRQ_PPC_CYCLE_TPU_UON_BUS2 141 +#define IRQ_PPC_EVENT_BUS2_L_AND_BUS2 142 +#define IRQ_PPC_EVENT_BUS2_L_OR_BUS2 143 +#define IRQ_PPC_EVENT_BUS2_UON_AND_BUS2 144 +#define IRQ_PPC_EVENT_BUS2_UON_OR_BUS2 145 +#define IRQ_PPC_EVENT_G3D_L_AND_BUS2 146 +#define IRQ_PPC_EVENT_G3D_L_OR_BUS2 147 +#define IRQ_PPC_EVENT_G3D_UON_AND_BUS2 148 +#define IRQ_PPC_EVENT_G3D_UON_OR_BUS2 149 +#define IRQ_PPC_EVENT_TPU_L_BUS2 150 +#define IRQ_PPC_EVENT_TPU_UON_BUS2 151 +#define IRQ_PPCFW_G3D_BUS2 152 +#define IRQ_SYSMMU_G3D0_BUS2 153 +#define IRQ_SYSMMU_G3D1_BUS2 154 +#define IRQ_SYSMMU_G3D2_BUS2 155 +#define IRQ_SYSMMU_G3D3_BUS2 156 +#define IRQ_TREX_D_BUS2_debugInterrupt_BUS2 157 +#define IRQ_TREX_P_BUS2_debugInterrupt_BUS2 158 +#define IRQ_TREX_PPMU_BUS2M0_BUS2 159 +#define IRQ_TREX_PPMU_BUS2M1_BUS2 160 +#define IRQ_TREX_PPMU_BUS2M2_BUS2 161 +#define IRQ_TREX_PPMU_BUS2M3_BUS2 162 +#define IRQ_TREX_PPMU_GPU0_BUS2 163 +#define IRQ_TREX_PPMU_GPU1_BUS2 164 +#define IRQ_TREX_PPMU_GPU2_BUS2 165 +#define IRQ_TREX_PPMU_GPU3_BUS2 166 +#define IRQ_BDU_O_INT_CORE 167 +#define IRQ_CCI_nERRIRQ_CORE 168 +#define IRQ_CCI_nEVNTCNTOVERFLOW_0_CORE 169 +#define IRQ_CCI_nEVNTCNTOVERFLOW_1_CORE 170 +#define IRQ_CCI_nEVNTCNTOVERFLOW_2_CORE 171 +#define IRQ_CCI_nEVNTCNTOVERFLOW_3_CORE 172 +#define IRQ_CCI_nEVNTCNTOVERFLOW_4_CORE 173 +#define IRQ_CCI_nEVNTCNTOVERFLOW_5_CORE 174 +#define IRQ_CCI_nEVNTCNTOVERFLOW_6_CORE 175 +#define IRQ_CCI_nEVNTCNTOVERFLOW_7_CORE 176 +#define IRQ_CORE_PPC_CON_O_IL_AND_PPC_BUS2_EVENT_CORE 177 +#define IRQ_CORE_PPC_CON_O_IL_AND_PPC_CCI_EVENT_CORE 178 +#define IRQ_CORE_PPC_CON_O_IL_AND_PPC_CPUCL0_EVENT_CORE 179 +#define IRQ_CORE_PPC_CON_O_IL_OR_PPC_BUS2_EVENT_CORE 180 +#define IRQ_CORE_PPC_CON_O_IL_OR_PPC_CCI_EVENT_CORE 181 +#define IRQ_CORE_PPC_CON_O_IL_OR_PPC_CPUCL0_EVENT_CORE 182 +#define IRQ_CORE_PPC_CON_O_IUON_AND_PPC_BUS2_EVENT_CORE 183 +#define IRQ_CORE_PPC_CON_O_IUON_AND_PPC_CCI_EVENT_CORE 184 +#define IRQ_CORE_PPC_CON_O_IUON_AND_PPC_CPUCL0_EVENT_CORE 185 +#define IRQ_CORE_PPC_CON_O_IUON_OR_PPC_BUS2_EVENT_CORE 186 +#define IRQ_CORE_PPC_CON_O_IUON_OR_PPC_CCI_EVENT_CORE 187 +#define IRQ_CORE_PPC_CON_O_IUON_OR_PPC_CPUCL0_EVENT_CORE 188 +#define IRQ_LD_SLC_CH0_O_APC_NS_IRQ_CORE 189 +#define IRQ_LD_SLC_CH0_O_APC_S_IRQ_CORE 190 +#define IRQ_LD_SLC_CH0_O_PPMPU_IRQ_CORE 191 +#define IRQ_LD_SLC_CH0_O_UASC_GSA_IRQ_CORE 192 +#define IRQ_LD_SLC_CH0_O_UASC_NS_IRQ_CORE 193 +#define IRQ_LD_SLC_CH0_O_UASC_TZ_IRQ_CORE 194 +#define IRQ_LD_SLC_CH1_O_APC_NS_IRQ_CORE 195 +#define IRQ_LD_SLC_CH1_O_APC_S_IRQ_CORE 196 +#define IRQ_LD_SLC_CH1_O_PPMPU_IRQ_CORE 197 +#define IRQ_LD_SLC_CH1_O_UASC_GSA_IRQ_CORE 198 +#define IRQ_LD_SLC_CH1_O_UASC_NS_IRQ_CORE 199 +#define IRQ_LD_SLC_CH1_O_UASC_TZ_IRQ_CORE 200 +#define IRQ_LD_SLC_CH2_O_APC_NS_IRQ_CORE 201 +#define IRQ_LD_SLC_CH2_O_APC_S_IRQ_CORE 202 +#define IRQ_LD_SLC_CH2_O_PPMPU_IRQ_CORE 203 +#define IRQ_LD_SLC_CH2_O_UASC_GSA_IRQ_CORE 204 +#define IRQ_LD_SLC_CH2_O_UASC_NS_IRQ_CORE 205 +#define IRQ_LD_SLC_CH2_O_UASC_TZ_IRQ_CORE 206 +#define IRQ_LD_SLC_CH3_O_APC_NS_IRQ_CORE 207 +#define IRQ_LD_SLC_CH3_O_APC_S_IRQ_CORE 208 +#define IRQ_LD_SLC_CH3_O_PPMPU_IRQ_CORE 209 +#define IRQ_LD_SLC_CH3_O_UASC_GSA_IRQ_CORE 210 +#define IRQ_LD_SLC_CH3_O_UASC_NS_IRQ_CORE 211 +#define IRQ_LD_SLC_CH3_O_UASC_TZ_IRQ_CORE 212 +#define IRQ_PPC_BUS0_M0_CYCLE_O_IL_CORE 213 +#define IRQ_PPC_BUS0_M0_CYCLE_O_IUON_CORE 214 +#define IRQ_PPC_BUS0_M0_EVENT_O_IL_CORE 215 +#define IRQ_PPC_BUS0_M0_EVENT_O_IUON_CORE 216 +#define IRQ_PPC_BUS2_M0_CYCLE_O_IL_CORE 217 +#define IRQ_PPC_BUS2_M0_CYCLE_O_IUON_CORE 218 +#define IRQ_PPC_CCI_M1_CYCLE_O_IL_CORE 219 +#define IRQ_PPC_CCI_M1_CYCLE_O_IUON_CORE 220 +#define IRQ_PPC_CPUCL0_D0_CYCLE_O_IL_CORE 221 +#define INTREQ__SECURE_LOG 224 +#define IRQ_PPC_CPUCL0_D0_CYCLE_O_IUON_CORE 227 +#define IRQ_PPC_DEBUG_O_IL_CORE 228 +#define IRQ_PPC_DEBUG_O_IUON_CORE 229 +#define IRQ_PPC_EH_CYCLE_O_IL_CORE 230 +#define IRQ_PPC_EH_CYCLE_O_IUON_CORE 231 +#define IRQ_PPC_EH_EVENT_O_IL_CORE 232 +#define IRQ_PPC_EH_EVENT_O_IUON_CORE 233 +#define IRQ_PPC_IO_CYCLE_O_IL_CORE 234 +#define IRQ_PPC_IO_CYCLE_O_IUON_CORE 235 +#define IRQ_PPC_IO_EVENT_O_IL_CORE 236 +#define IRQ_PPC_IO_EVENT_O_IUON_CORE 237 +#define IRQ_PPMU_ACE_CPUCL0_O_IL_CORE 238 +#define IRQ_PPMU_ACE_CPUCL0_O_IUON_CORE 239 +#define IRQ_PPMU_ACE_CPUCL1_O_IL_CORE 240 +#define IRQ_PPMU_ACE_CPUCL1_O_IUON_CORE 241 +#define IRQ_TREX_D_CORE_debugInterrupt_CORE 242 +#define IRQ_TREX_D_CORE_ppcInterrupt_CORE_CCI_CORE 243 +#define IRQ_TREX_D_CORE_ppcInterrupt_CORE_DP_CORE 244 +#define IRQ_TREX_D_CORE_ppcInterrupt_CORE_M0_CORE 245 +#define IRQ_TREX_D_CORE_ppcInterrupt_CORE_M1_CORE 246 +#define IRQ_TREX_D_CORE_ppcInterrupt_CORE_M2_CORE 247 +#define IRQ_TREX_D_CORE_ppcInterrupt_CORE_M3_CORE 248 +#define IRQ_TREX_D_CORE_ppcInterrupt_CPU0_CORE 249 +#define IRQ_TREX_D_CORE_ppcInterrupt_CPU1_CORE 250 +#define IRQ_TREX_D_CORE_ppcInterrupt_CPU2_CORE 251 +#define IRQ_TREX_D_CORE_ppcInterrupt_CPU3_CORE 252 +#define IRQ_TREX_P_CORE_debugInterrupt_CORE 253 +#define IRQ_TREX_P_CORE_ppcInterrupt_CCI_CORE 254 +#define IRQ_TREX_P_CORE_ppcInterrupt_CORE_ALIVE_CORE 255 +#define IRQ_TREX_P_CORE_ppcInterrupt_CORE_DP_CORE 256 +#define IRQ_CPUCL0_CLUSTERPMUIRQ_CPUCL0 257 +#define IRQ_CPUCL0_DDD_APBIF0_FAST_PEND_CPUCL0 258 +#define IRQ_CPUCL0_DDD_APBIF0_HIGH_PEND_CPUCL0 259 +#define IRQ_CPUCL0_DDD_APBIF0_LOW_PEND_CPUCL0 260 +#define IRQ_CPUCL0_DDD_APBIF0_SLOW_PEND_CPUCL0 261 +#define IRQ_CPUCL0_DDD_APBIF1_FAST_PEND_CPUCL0 262 +#define IRQ_CPUCL0_DDD_APBIF1_HIGH_PEND_CPUCL0 263 +#define IRQ_CPUCL0_DDD_APBIF1_LOW_PEND_CPUCL0 264 +#define IRQ_CPUCL0_DDD_APBIF1_SLOW_PEND_CPUCL0 265 +#define IRQ_CPUCL0_DDD_APBIF2_FAST_PEND_CPUCL0 266 +#define IRQ_CPUCL0_DDD_APBIF2_HIGH_PEND_CPUCL0 267 +#define IRQ_CPUCL0_DDD_APBIF2_LOW_PEND_CPUCL0 268 +#define IRQ_CPUCL0_DDD_APBIF2_SLOW_PEND_CPUCL0 269 +#define IRQ_CPUCL0_DDD_APBIF3_FAST_PEND_CPUCL0 270 +#define IRQ_CPUCL0_DDD_APBIF3_HIGH_PEND_CPUCL0 271 +#define IRQ_CPUCL0_DDD_APBIF3_LOW_PEND_CPUCL0 272 +#define IRQ_CPUCL0_DDD_APBIF3_SLOW_PEND_CPUCL0 273 +#define IRQ_CPUCL0_ERRIRQ_0_CPUCL0 274 +#define IRQ_CPUCL0_ERRIRQ_1_CPUCL0 275 +#define IRQ_CPUCL0_ERRIRQ_2_CPUCL0 276 +#define IRQ_CPUCL0_ERRIRQ_3_CPUCL0 277 +#define IRQ_CPUCL0_ERRIRQ_4_CPUCL0 278 +#define IRQ_CPUCL0_ERRIRQ_5_CPUCL0 279 +#define IRQ_CPUCL0_ERRIRQ_6_CPUCL0 280 +#define IRQ_CPUCL0_ERRIRQ_7_CPUCL0 281 +#define IRQ_CPUCL0_ERRIRQ_8_CPUCL0 282 +#define IRQ_CPUCL0_FAULTIRQ_0_CPUCL0 283 +#define IRQ_CPUCL0_FAULTIRQ_1_CPUCL0 284 +#define IRQ_CPUCL0_FAULTIRQ_2_CPUCL0 285 +#define IRQ_CPUCL0_FAULTIRQ_3_CPUCL0 286 +#define IRQ_CPUCL0_FAULTIRQ_4_CPUCL0 287 +#define IRQ_CPUCL0_FAULTIRQ_5_CPUCL0 288 +#define IRQ_CPUCL0_FAULTIRQ_6_CPUCL0 289 +#define IRQ_CPUCL0_FAULTIRQ_7_CPUCL0 290 +#define IRQ_CPUCL0_FAULTIRQ_8_CPUCL0 291 +#define O_HPM_IRQ_CPUCL0_CPUCL0 292 +#define IRQ_CPUCL0_S2MPU_IRQ_CPUCL0 293 +#define IRQ_CSIS0_CSIS 294 +#define IRQ_CSIS1_CSIS 295 +#define IRQ_CSIS2_CSIS 296 +#define IRQ_CSIS3_CSIS 297 +#define IRQ_CSIS4_CSIS 298 +#define IRQ_CSIS5_CSIS 299 +#define IRQ_CSIS6_CSIS 300 +#define IRQ_CSIS7_CSIS 301 +#define IRQ_CSIS_DMA0_CSIS 302 +#define IRQ_CSIS_DMA1_CSIS 303 +#define IRQ_CSIS_DMA2_CSIS 304 +#define IRQ_CSIS_DMA3_CSIS 305 +#define IRQ_EBUF_OVERFLOW0_CSIS 306 +#define IRQ_EBUF_OVERFLOW1_CSIS 307 +#define IRQ_EBUF_OVERFLOW2_CSIS 308 +#define IRQ_EBUF_OVERFLOW3_CSIS 309 +#define IRQ_MUTE_CSIS0_CSIS 310 +#define IRQ_MUTE_CSIS1_CSIS 311 +#define IRQ_MUTE_CSIS2_CSIS 312 +#define IRQ_MUTE_CSIS3_CSIS 313 +#define IRQ_MUTE_STRP0_CSIS 314 +#define IRQ_MUTE_STRP1_CSIS 315 +#define IRQ_MUTE_STRP2_CSIS 316 +#define IRQ_MUTE_ZSL0_CSIS 317 +#define IRQ_MUTE_ZSL1_CSIS 318 +#define IRQ_MUTE_ZSL2_CSIS 319 +#define IRQ_PPMU_D0_CSIS_UPPER_OR_NORMAL_CSIS 320 +#define IRQ_PPMU_D1_CSIS_UPPER_OR_NORMAL_CSIS 321 +#define IRQ_STRP_DMA0_CSIS 322 +#define IRQ_STRP_DMA1_CSIS 323 +#define IRQ_STRP_DMA2_CSIS 324 +#define IRQ_SYSMMU_D0_CSIS_S1_NS_CSIS 325 +#define IRQ_SYSMMU_D0_CSIS_S1_S_CSIS 326 +#define IRQ_SYSMMU_D0_CSIS_S2_CSIS 327 +#define IRQ_SYSMMU_D1_CSIS_S1_NS_CSIS 328 +#define IRQ_SYSMMU_D1_CSIS_S1_S_CSIS 329 +#define IRQ_SYSMMU_D1_CSIS_S2_CSIS 330 +#define IRQ_ZSL_DMA0_CSIS 331 +#define IRQ_ZSL_DMA1_CSIS 332 +#define IRQ_ZSL_DMA2_CSIS 333 +#define IRQ_DISP_DECON0_DQE_DIMMING_END_DISP 334 +#define IRQ_DISP_DECON0_DQE_DIMMING_START_DISP 335 +#define IRQ_DISP_DECON0_EXTRA_DISP 336 +#define IRQ_DISP_DECON0_FRAME_DONE_DISP 337 +#define IRQ_DISP_DECON0_FRAME_START_DISP 338 +#define IRQ_DISP_DECON1_EXTRA_DISP 339 +#define IRQ_DISP_DECON1_FRAME_DONE_DISP 340 +#define IRQ_DISP_DECON1_FRAME_START_DISP 341 +#define IRQ_DISP_DECON2_EXTRA_DISP 342 +#define IRQ_DISP_DECON2_FRAME_DONE_DISP 343 +#define IRQ_DISP_DECON2_FRAME_START_DISP 344 +#define IRQ_DISP_DSIM0_DISP 345 +#define IRQ_DISP_DSIM1_DISP 346 +#define IRQ_DNS_0_DNS 347 +#define IRQ_DNS_1_DNS 348 +#define IRQ_DNS_MUTE_DNS 349 +#define IRQ_PPMU_DNS_UPPER_OR_NORMAL_DNS 350 +#define IRQ_SYSMMU_DNS_S1_NS_DNS 351 +#define IRQ_SYSMMU_DNS_S1_S_DNS 352 +#define IRQ_SYSMMU_DNS_S2_DNS 353 +#define IRQ_DPU_DMA_L0_DPU 354 +#define IRQ_DPU_DMA_L1_DPU 355 +#define IRQ_DPU_DMA_L2_DPU 356 +#define IRQ_DPU_DMA_L3_DPU 357 +#define IRQ_DPU_DMA_L4_DPU 358 +#define IRQ_DPU_DMA_L5_DPU 359 +#define IRQ_DPU_DMA_WB_DPU 360 +#define IRQ_DPU_DPP_L0_DPU 361 +#define IRQ_DPU_DPP_L1_DPU 362 +#define IRQ_DPU_DPP_L2_DPU 363 +#define IRQ_DPU_DPP_L3_DPU 364 +#define IRQ_DPU_DPP_L4_DPU 365 +#define IRQ_DPU_DPP_L5_DPU 366 +#define IRQ_PPMU_DPUD0_UPPER_OR_NORMAL_DPU 367 +#define IRQ_PPMU_DPUD1_UPPER_OR_NORMAL_DPU 368 +#define IRQ_PPMU_DPUD2_UPPER_OR_NORMAL_DPU 369 +#define IRQ_SYSMMU_DPUD0_S1_NS_DPU 370 +#define IRQ_SYSMMU_DPUD0_S1_S_DPU 371 +#define IRQ_SYSMMU_DPUD0_S2_DPU 372 +#define IRQ_SYSMMU_DPUD1_S1_NS_DPU 373 +#define IRQ_SYSMMU_DPUD1_S1_S_DPU 374 +#define IRQ_SYSMMU_DPUD1_S2_DPU 375 +#define IRQ_SYSMMU_DPUD2_S1_NS_DPU 376 +#define IRQ_SYSMMU_DPUD2_S1_S_DPU 377 +#define IRQ_SYSMMU_DPUD2_S2_DPU 378 +#define IRQ_EH_0_EH 379 +#define IRQ_EH_1_EH 380 +#define IRQ_EH_2_EH 381 +#define IRQ_EH_3_EH 382 +#define IRQ_EH_4_EH 383 +#define IRQ_EH_5_EH 384 +#define IRQ_EH_6_EH 385 +#define IRQ_EH_7_EH 386 +#define IRQ_EH_8_EH 387 +#define IRQ_EH_9_EH 388 +#define IRQ_PPMU_UPPER_OR_NORMAL_EH 389 +#define IRQ_SSMT_EH_EH 390 +#define IRQ_SYSMMU_S2_EH_EH 391 +#define IRQ_UASC_GSA_EH_EH 392 +#define IRQ_UASC_NS_EH_EH 393 +#define IRQ_UASC_S_EH_EH 394 +#define IRQ_G2D_G2D 395 +#define IRQ_JPEG_G2D 396 +#define IRQ_PPMU_D0_G2D_interrupt_upper_or_normal_G2D 397 +#define IRQ_PPMU_D1_G2D_interrupt_upper_or_normal_G2D 398 +#define IRQ_PPMU_D2_G2D_interrupt_upper_or_normal_G2D 399 +#define IRQ_SSMT_D0_G2D_intreq_G2D 400 +#define IRQ_SSMT_D1_G2D_intreq_G2D 401 +#define IRQ_SSMT_D2_G2D_intreq_G2D 402 +#define IRQ_SYSMMU_D0_G2D_interrupt_s1_ns_G2D 403 +#define IRQ_SYSMMU_D0_G2D_interrupt_s2_G2D 404 +#define IRQ_SYSMMU_D0_G2D_interrupt_s1_s_G2D 405 +#define IRQ_SYSMMU_D1_G2D_interrupt_s1_ns_G2D 406 +#define IRQ_SYSMMU_D1_G2D_interrupt_s2_G2D 407 +#define IRQ_SYSMMU_D1_G2D_interrupt_s1_s_G2D 408 +#define IRQ_SYSMMU_D2_G2D_interrupt_s1_ns_G2D 409 +#define IRQ_SYSMMU_D2_G2D_interrupt_s2_G2D 410 +#define IRQ_SYSMMU_D2_G2D_interrupt_s1_s_G2D 411 +#define IRQ_G3AA_G3AA 412 +#define IRQ_PPMU_G3AA_UPPER_OR_NORMAL_G3AA 413 +#define IRQ_SSMT_G3AA_G3AA 414 +#define IRQ_SYSMMU_G3AA_S1_NS_G3AA 415 +#define IRQ_SYSMMU_G3AA_S1_S_G3AA 416 +#define IRQ_SYSMMU_G3AA_S2_G3AA 417 +#define IRQ_G3D_IRQEVENT_G3D 418 +#define IRQ_G3D_IRQGPU_G3D 419 +#define IRQ_G3D_IRQJOB_G3D 420 +#define IRQ_G3D_IRQMMU_G3D 421 +#define IRQ_UASC_GSA_G3D_G3D 422 +#define IRQ_UASC_NS_G3D_G3D 423 +#define IRQ_UASC_S_G3D_G3D 424 +#define O_ADD_APBIF_G3D_FLAG_IRQ_PEND_G3D 425 +#define O_DDD_APBIF_G3D_DD_ERR_IRQ_FAST_PEND_G3D 426 +#define O_DDD_APBIF_G3D_DD_ERR_IRQ_SLOW_PEND_G3D 427 +#define O_HPM_IRQ_G3D 428 +#define IRQ_GDC0_IRQ_GDC 429 +#define IRQ_GDC0_Mute_IRQ_GDC 430 +#define IRQ_GDC1_IRQ_GDC 431 +#define IRQ_GDC1_Mute_IRQ_GDC 432 +#define IRQ_PPMU_D0_GDC_UPPER_OR_NORMAL_GDC 433 +#define IRQ_PPMU_D1_GDC_UPPER_OR_NORMAL_GDC 434 +#define IRQ_PPMU_D_SCSC_UPPER_OR_NORMAL_GDC 435 +#define IRQ_SCSC_IRQ_GDC 436 +#define IRQ_SCSC_NonSecu_Mute_IRQ_GDC 437 +#define IRQ_SYSMMU_D0_GDC_S1_NS_GDC 438 +#define IRQ_SYSMMU_D0_GDC_S1_S_GDC 439 +#define IRQ_SYSMMU_D0_GDC_S2_GDC 440 +#define IRQ_SYSMMU_D1_GDC_S1_NS_GDC 441 +#define IRQ_SYSMMU_D1_GDC_S1_S_GDC 442 +#define IRQ_SYSMMU_D1_GDC_S2_GDC 443 +#define IRQ_SYSMMU_D2_GDC_S1_NS_GDC 444 +#define IRQ_SYSMMU_D2_GDC_S1_S_GDC 445 +#define IRQ_SYSMMU_D2_GDC_S2_GDC 446 +#define IRQ_MAILBOX_GSA2NONTZ_GSA 447 +#define IRQ_MAILBOX_GSA2OSCAR_GSA 448 +#define IRQ_MAILBOX_GSA2PAINTBOX_GSA 449 +#define IRQ_MAILBOX_GSA2TZ_GSA 450 +#define SYSMMU_NS__INTERRUPT_GSA 451 +#define SYSMMU_S2MPU__INTERRUPT_GSA 452 +#define SYSMMU_S__INTERRUPT_GSA 453 +#define IRQ_DP_LINK_HSI0 454 +#define IRQ_PPMU_HSI0_AOC_UPPER_OR_NORMAL_HSI0 455 +#define IRQ_PPMU_HSI0_BUS0_UPPER_OR_NORMAL_HSI0 456 +#define IRQ_SYSMMU_USB_HSI0 457 +#define IRQ_USB2_REMOTE_CONNECT_GIC_HSI0 458 +#define IRQ_USB2_REMOTE_TIMER_GIC_HSI0 459 +#define IRQ_USB2_REMOTE_WAKEUP_GIC_HSI0 460 +#define IRQ_USB31DRD_FSVMINUS_GIC_HSI0 461 +#define IRQ_USB31DRD_FSVPLUS_GIC_HSI0 462 +#define IRQ_USB31DRD_GIC_0_HSI0 463 +#define IRQ_USB31DRD_GIC_1_HSI0 464 +#define IRQ_USB_UDBG_HSI0 465 +#define IRQ_USB_WAKEUP_HSI0 466 +#define NONSEQINT__UASC_HSI0_CTRL_HSI0 467 +#define NONSEQINT__UASC_HSI0_LINK_HSI0 468 +#define TZINT__UASC_HSI0_CTRL_HSI0 469 +#define TZINT__UASC_HSI0_LINK_HSI0 470 +#define IRQ_GPIO_HSI1_HSI1 471 +#define IRQ_PCIE_GEN4A_0_HSI1 472 +#define IRQ_PCIE_GEN4A_MSI_0_HSI1 473 +#define IRQ_PCIE_GEN4A_MSI_1_HSI1 474 +#define IRQ_PCIE_GEN4A_MSI_2_HSI1 475 +#define IRQ_PCIE_GEN4A_MSI_3_HSI1 476 +#define IRQ_PCIE_GEN4A_MSI_4_HSI1 477 +#define IRQ_PCIE_GEN4B_0_HSI1 478 +#define IRQ_PCIE_GEN4B_MSI_0_HSI1 479 +#define IRQ_PCIE_GEN4B_MSI_1_HSI1 480 +#define IRQ_PCIE_GEN4B_MSI_2_HSI1 481 +#define IRQ_PCIE_GEN4B_MSI_3_HSI1 482 +#define IRQ_PCIE_GEN4B_MSI_4_HSI1 483 +#define IRQ_PCIE_IA_GEN4A_0_HSI1 484 +#define IRQ_PCIE_IA_GEN4B_0_HSI1 485 +#define IRQ_PCIE_PCS_GEN4_0_HSI1 486 +#define IRQ_PCIE_PCS_GEN4B_0_HSI1 487 +#define IRQ_PPMU_HSI1_UPPER_OR_NORMAL_HSI1 488 +#define IRQ_SSMT_HSI1_HSI1 489 +#define IRQ_SYSMMU_HSI1_S2MPU_HSI1 490 +#define IRQ_UASC_GSA_PCIE_GEN4A_DBI_0_HSI1 491 +#define IRQ_UASC_GSA_PCIE_GEN4A_SLV_0_HSI1 492 +#define IRQ_UASC_GSA_PCIE_GEN4B_DBI_0_HSI1 493 +#define IRQ_UASC_GSA_PCIE_GEN4B_SLV_0_HSI1 494 +#define IRQ_UASC_NS_PCIE_GEN4A_DBI_0_HSI1 495 +#define IRQ_UASC_NS_PCIE_GEN4A_SLV_0_HSI1 496 +#define IRQ_UASC_NS_PCIE_GEN4B_DBI_0_HSI1 497 +#define IRQ_UASC_NS_PCIE_GEN4B_SLV_0_HSI1 498 +#define IRQ_UASC_S_PCIE_GEN4A_DBI_0_HSI1 499 +#define IRQ_UASC_S_PCIE_GEN4A_SLV_0_HSI1 500 +#define IRQ_UASC_S_PCIE_GEN4B_DBI_0_HSI1 501 +#define IRQ_UASC_S_PCIE_GEN4B_SLV_0_HSI1 502 +#define IRQ_GPIO_HSI2_HSI2 503 +#define IRQ_MMC_CARD_HSI2 504 +#define IRQ_NONSEQINT_PCIE_GEN4A_DBI_1_HSI2 505 +#define IRQ_NONSEQINT_PCIE_GEN4A_SLV_1_HSI2 506 +#define IRQ_NONSEQINT_PCIE_GEN4B_DBI_1_HSI2 507 +#define IRQ_NONSEQINT_PCIE_GEN4B_SLV_1_HSI2 508 +#define IRQ_PCIE_GEN4A_1_HSI2 509 +#define IRQ_PCIE_GEN4A_1_MSI_0_HSI2 510 +#define IRQ_PCIE_GEN4A_1_MSI_1_HSI2 511 +#define IRQ_PCIE_GEN4A_1_MSI_2_HSI2 512 +#define IRQ_PCIE_GEN4A_1_MSI_3_HSI2 513 +#define IRQ_PCIE_GEN4A_1_MSI_4_HSI2 514 +#define IRQ_PCIE_GEN4B_1_HSI2 515 +#define IRQ_PCIE_GEN4B_1_MSI_0_HSI2 516 +#define IRQ_PCIE_GEN4B_1_MSI_1_HSI2 517 +#define IRQ_PCIE_GEN4B_1_MSI_2_HSI2 518 +#define IRQ_PCIE_GEN4B_1_MSI_3_HSI2 519 +#define IRQ_PCIE_GEN4B_1_MSI_4_HSI2 520 +#define IRQ_PCIE_IA_GEN4A_1_HSI2 521 +#define IRQ_PCIE_IA_GEN4B_1_HSI2 522 +#define IRQ_PCIE_PCS_GEN4_1_HSI2 523 +#define IRQ_PCIE_PCS_GEN4B_1_HSI2 524 +#define IRQ_PPMU_HSI2_UPPER_OR_NORMAL_HSI2 525 +#define IRQ_SSMT_HSI2_HSI2 526 +#define IRQ_SYSMMU_HSI2_S2_HSI2 527 +#define IRQ_TZINT_PCIE_GEN4A_DBI_1_HSI2 528 +#define IRQ_TZINT_PCIE_GEN4A_SLV_1_HSI2 529 +#define IRQ_TZINT_PCIE_GEN4B_DBI_1_HSI2 530 +#define IRQ_TZINT_PCIE_GEN4B_SLV_1_HSI2 531 +#define IRQ_UFS_EMBD_HSI2 532 +#define IRQ_IPP_CH0_0_IPP 533 +#define IRQ_IPP_CH0_1_IPP 534 +#define IRQ_IPP_CH1_0_IPP 535 +#define IRQ_IPP_CH1_1_IPP 536 +#define IRQ_IPP_CH2_0_IPP 537 +#define IRQ_IPP_CH2_1_IPP 538 +#define IRQ_MUTE_GTNR_ALIGN_IPP 539 +#define IRQ_MUTE_IPP0_IPP 540 +#define IRQ_MUTE_IPP1_IPP 541 +#define IRQ_MUTE_IPP2_IPP 542 +#define IRQ_PPMU_IPP_UPPER_OR_NORMAL_IPP 543 +#define IRQ_PPMU_MSA_UPPER_OR_NORMAL_IPP 544 +#define IRQ_SYSMMU_IPP_S1_NS_IPP 545 +#define IRQ_SYSMMU_IPP_S1_S_IPP 546 +#define IRQ_SYSMMU_IPP_S2_IPP 547 +#define IRQ_TNR_A_IPP 548 +#define IRQ_C2COM_MCSC_MCSC 549 +#define IRQ_C2R_MCSC_MCSC 550 +#define IRQ_ITSC_NonSecu_Mute_MCSC 551 +#define IRQ_ITSC_OTF0_MCSC 552 +#define IRQ_MCSC_NonSecu_Mute_MCSC 553 +#define IRQ_MCSC_OTF0_MCSC 554 +#define IRQ_PPMU_D0_ITSC_UPPER_OR_NORMAL_MCSC 555 +#define IRQ_PPMU_D0_MCSC_UPPER_OR_NORMAL_MCSC 556 +#define IRQ_PPMU_D1_ITSC_UPPER_OR_NORMAL_MCSC 557 +#define IRQ_PPMU_D1_MCSC_UPPER_OR_NORMAL_MCSC 558 +#define IRQ_SYSMMU_D0_MCSC_S1_NS_MCSC 559 +#define IRQ_SYSMMU_D0_MCSC_S1_S_MCSC 560 +#define IRQ_SYSMMU_D0_MCSC_S2_MCSC 561 +#define IRQ_SYSMMU_D1_MCSC_S1_NS_MCSC 562 +#define IRQ_SYSMMU_D1_MCSC_S1_S_MCSC 563 +#define IRQ_SYSMMU_D1_MCSC_S2_MCSC 564 +#define IRQ_SYSMMU_D2_MCSC_S1_NS_MCSC 565 +#define IRQ_SYSMMU_D2_MCSC_S1_S_MCSC 566 +#define IRQ_SYSMMU_D2_MCSC_S2_MCSC 567 +#define IRQ_MFC_MFC 568 +#define IRQ_PPMU_D0_MFC_interrupt_upper_or_normal_MFC 569 +#define IRQ_PPMU_D1_MFC_interrupt_upper_or_normal_MFC 570 +#define IRQ_SYSMMU_D0_MFC_interrupt_s1_ns_MFC 571 +#define IRQ_SYSMMU_D0_MFC_interrupt_s1_s_MFC 572 +#define IRQ_SYSMMU_D0_MFC_interrupt_s2_MFC 573 +#define IRQ_SYSMMU_D1_MFC_interrupt_s1_ns_MFC 574 +#define IRQ_SYSMMU_D1_MFC_interrupt_s1_s_MFC 575 +#define IRQ_SYSMMU_D1_MFC_interrupt_s2_MFC 576 +#define IRQ_DMC_APBACCESSINT_MIF0 577 +#define IRQ_DMC_ECC_CORERR_MIF0 578 +#define IRQ_DMC_ECC_UNCORERR_MIF0 579 +#define IRQ_DMC_PPMPINT_MIF0 580 +#define IRQ_DMC_SWZQ0_MIF0 581 +#define IRQ_DMC_SWZQ1_MIF0 582 +#define IRQ_DMC_TEMPERR_MIF0 583 +#define IRQ_DMC_TEMPHOT_MIF0 584 +#define IRQ_DMC_TZCINT_MIF0 585 +#define IRQ_DMC_APBACCESSINT_MIF1 586 +#define IRQ_DMC_ECC_CORERR_MIF1 587 +#define IRQ_DMC_ECC_UNCORERR_MIF1 588 +#define IRQ_DMC_PPMPINT_MIF1 589 +#define IRQ_DMC_SWZQ0_MIF1 590 +#define IRQ_DMC_SWZQ1_MIF1 591 +#define IRQ_DMC_TEMPERR_MIF1 592 +#define IRQ_DMC_TEMPHOT_MIF1 593 +#define IRQ_DMC_TZCINT_MIF1 594 +#define IRQ_DMC_APBACCESSINT_MIF2 595 +#define IRQ_DMC_ECC_CORERR_MIF2 596 +#define IRQ_DMC_ECC_UNCORERR_MIF2 597 +#define IRQ_DMC_PPMPINT_MIF2 598 +#define IRQ_DMC_SWZQ0_MIF2 599 +#define IRQ_DMC_SWZQ1_MIF2 600 +#define IRQ_DMC_TEMPERR_MIF2 601 +#define IRQ_DMC_TEMPHOT_MIF2 602 +#define IRQ_DMC_TZCINT_MIF2 603 +#define IRQ_DMC_APBACCESSINT_MIF3 604 +#define IRQ_DMC_ECC_CORERR_MIF3 605 +#define IRQ_DMC_ECC_UNCORERR_MIF3 606 +#define IRQ_DMC_PPMPINT_MIF3 607 +#define IRQ_DMC_SWZQ0_MIF3 608 +#define IRQ_DMC_SWZQ1_MIF3 609 +#define IRQ_DMC_TEMPERR_MIF3 610 +#define IRQ_DMC_TEMPHOT_MIF3 611 +#define IRQ_DMC_TZCINT_MIF3 612 +#define IRQ_PDP_MUTE0_PDP 613 +#define IRQ_PDP_MUTE1_PDP 614 +#define IRQ_PDP_MUTE2_PDP 615 +#define IRQ_PDP_TOP0_PDP 616 +#define IRQ_PDP_TOP1_PDP 617 +#define IRQ_PDP_TOP2_PDP 618 +#define IRQ_PDP_TOP3_PDP 619 +#define IRQ_PDP_TOP4_PDP 620 +#define IRQ_PDP_TOP5_PDP 621 +#define IRQ_PPMU_VRA_UPPER_OR_NORMAL_PDP 622 +#define IRQ_SSMT_VRA_PDP 623 +#define IRQ_VRA_PDP 624 +#define IRQ_GPIO_PERIC0_PERIC0 625 +#define IRQ_I3C1_PERIC0 626 +#define IRQ_I3C2_PERIC0 627 +#define IRQ_I3C3_PERIC0 628 +#define IRQ_I3C4_PERIC0 629 +#define IRQ_I3C5_PERIC0 630 +#define IRQ_I3C6_PERIC0 631 +#define IRQ_I3C7_PERIC0 632 +#define IRQ_I3C8_PERIC0 633 +#define IRQ_USI0_UART_PERIC0 634 +#define IRQ_USI1_USI_PERIC0 635 +#define IRQ_USI2_USI_PERIC0 636 +#define IRQ_USI3_USI_PERIC0 637 +#define IRQ_USI4_USI_PERIC0 638 +#define IRQ_USI5_USI_PERIC0 639 +#define IRQ_USI6_USI_PERIC0 640 +#define IRQ_USI7_USI_PERIC0 641 +#define IRQ_USI8_USI_PERIC0 642 +#define IRQ_USI14_USI_PERIC0 643 +#define IRQ_GPIO_PERIC1_PERIC1 644 +#define IRQ_I3C0_PERIC1 645 +#define IRQ_PWM0_PERIC1 646 +#define IRQ_PWM1_PERIC1 647 +#define IRQ_PWM2_PERIC1 648 +#define IRQ_PWM3_PERIC1 649 +#define IRQ_PWM4_PERIC1 650 +#define IRQ_USI0_USI_PERIC1 651 +#define IRQ_USI9_USI_PERIC1 652 +#define IRQ_USI10_USI_PERIC1 653 +#define IRQ_USI11_USI_PERIC1 654 +#define IRQ_USI12_USI_PERIC1 655 +#define IRQ_USI13_USI_PERIC1 656 +#define IRQ_PPMU_D0_TNR_UPPER_OR_NORMAL_TNR 657 +#define IRQ_PPMU_D1_TNR_UPPER_OR_NORMAL_TNR 658 +#define IRQ_PPMU_D2_TNR_UPPER_OR_NORMAL_TNR 659 +#define IRQ_PPMU_D3_TNR_UPPER_OR_NORMAL_TNR 660 +#define IRQ_PPMU_D4_TNR_UPPER_OR_NORMAL_TNR 661 +#define IRQ_PPMU_D5_TNR_UPPER_OR_NORMAL_TNR 662 +#define IRQ_PPMU_D6_TNR_UPPER_OR_NORMAL_TNR 663 +#define IRQ_PPMU_D7_TNR_UPPER_OR_NORMAL_TNR 664 +#define IRQ_SYSMMU_D0_TNR_S1_NS_TNR 665 +#define IRQ_SYSMMU_D0_TNR_S1_S_TNR 666 +#define IRQ_SYSMMU_D0_TNR_S2_TNR 667 +#define IRQ_SYSMMU_D1_TNR_S1_NS_TNR 668 +#define IRQ_SYSMMU_D1_TNR_S1_S_TNR 669 +#define IRQ_SYSMMU_D1_TNR_S2_TNR 670 +#define IRQ_SYSMMU_D2_TNR_S1_NS_TNR 671 +#define IRQ_SYSMMU_D2_TNR_S1_S_TNR 672 +#define IRQ_SYSMMU_D2_TNR_S2_TNR 673 +#define IRQ_SYSMMU_D3_TNR_S1_NS_TNR 674 +#define IRQ_SYSMMU_D3_TNR_S1_S_TNR 675 +#define IRQ_SYSMMU_D3_TNR_S2_TNR 676 +#define IRQ_SYSMMU_D4_TNR_S1_NS_TNR 677 +#define IRQ_SYSMMU_D4_TNR_S1_S_TNR 678 +#define IRQ_SYSMMU_D4_TNR_S2_TNR 679 +#define IRQ_TNR_TNR 680 +#define IRQ_TNR_MUTE_TNR 681 +#define IRQ_DDD_IRQ_0_TPU 682 +#define IRQ_DDD_IRQ_1_TPU 683 +#define IRQ_DDD_IRQ_2_TPU 684 +#define IRQ_DDD_IRQ_3_TPU 685 +#define IRQ_HPM_IRQ_TPU 686 +#define IRQ_NS_TPU_TPU 687 +#define IRQ_PPMU_UPPER_OR_NORMAL_TPU 688 +#define IRQ_S_TPU_TPU 689 +#define IRQ_SSMT_TPU_TPU 690 +#define IRQ_SYSMMU_S1_NS_TPU_TPU 691 +#define IRQ_SYSMMU_S1_S_TPU_TPU 692 +#define IRQ_SYSMMU_S2_TPU_TPU 693 +#define IRQ_OTP_CON_TOP_MISC 752 +#define IRQ_MCT_G0_MISC 753 +#define IRQ_MCT_G1_MISC 754 +#define IRQ_MCT_G2_MISC 755 +#define IRQ_MCT_G3_MISC 756 +#define IRQ_MCT_L0_MISC 757 +#define IRQ_MCT_L1_MISC 758 +#define IRQ_MCT_L2_MISC 759 +#define IRQ_MCT_L3_MISC 760 +#define IRQ_MCT_L4_MISC 761 +#define IRQ_MCT_L5_MISC 762 +#define IRQ_MCT_L6_MISC 763 +#define IRQ_MCT_L7_MISC 764 +#define IRQ_WDT_CLUSTER0_MISC 765 +#define IRQ_WDT_CLUSTER1_MISC 766 +#define IRQ_OTP_CON_BISR_MISC 767 +#define IRQ_OTP_CON_BIRA_MISC 768 +#define IRQ_TMU_TMU_TOP_MISC 769 +#define IRQ_TMU_TMU_SUB_MISC 770 +#define IRQ_SPDMA_MISC 771 +#define IRQ_PDMA_MISC 772 +#define IRQ_PPMU_DMA_0_MISC 773 +#define IRQ_PPMU_DMA_1_MISC 774 +#define IRQ_PPMU_DMA_2_MISC 775 +#define IRQ_PPMU_DMA_3_MISC 776 +#define IRQ_PPMU_DMA_IRQ_ABORT_MISC 777 +#define IRQ_SSS_MISC 778 +#define IRQ_SSS_NS_MB_MISC 779 +#define IRQ_SSS_S_MB_MISC 780 +#define IRQ_SSS_KM_MISC 781 +#define IRQ_SSS_DMAINT_MISC 782 +#define IRQ_SSS_SWDT1_MISC 783 +#define IRQ_SSS_SWDT2_MISC 784 +#define IRQ_PUF_SEC_MISC 785 +#define IRQ_PUF_UNCOREECT_MISC 786 +#define IRQ_RTIC_MISC 787 +#define IRQ_DIT_RxDst0_MISC 788 +#define IRQ_DIT_RxDst1_MISC 789 +#define IRQ_DIT_RxDst2_MISC 790 +#define IRQ_DIT_Tx_MISC 791 +#define IRQ_DIT_Err_MISC 792 +#define IRQ_PPMU_MISC_UPPER_OR_NORMAL_MISC 793 +#define IRQ_SYSMMU_NS_SSS_MISC 794 +#define IRQ_SYSMMU_S_SSS_MISC 795 +#define IRQ_SYSMMU_S2_MISC_MISC 796 +#define IRQ_GIC_FAULT_MISC 797 +#define IRQ_GIC_ERR_MISC 798 +#define IRQ_GIC_PMU_MISC 799 + +#endif/*_DT_BINDINGS_INTERRUPT_CONTROLLER_GS101_H*/ From patchwork Thu Oct 5 15:55:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Griffin X-Patchwork-Id: 1843982 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=jiqyH7cu; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=permerror (SPF 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[92.12.225.146]) by smtp.gmail.com with ESMTPSA id t9-20020a5d4609000000b0031f8a59dbeasm2084336wrq.62.2023.10.05.08.57.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Oct 2023 08:57:20 -0700 (PDT) From: Peter Griffin To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, conor+dt@kernel.org, sboyd@kernel.org, tomasz.figa@gmail.com, s.nawrocki@samsung.com, linus.walleij@linaro.org, wim@linux-watchdog.org, linux@roeck-us.net, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, olof@lixom.net, cw00.choi@samsung.com Cc: peter.griffin@linaro.org, tudor.ambarus@linaro.org, andre.draszik@linaro.org, semen.protsenko@linaro.org, soc@kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-watchdog@vger.kernel.org Subject: [PATCH 02/21] dt-bindings: soc: samsung: exynos-pmu: Add gs101 compatible Date: Thu, 5 Oct 2023 16:55:59 +0100 Message-ID: <20231005155618.700312-3-peter.griffin@linaro.org> X-Mailer: git-send-email 2.42.0.582.g8ccd20d70d-goog In-Reply-To: <20231005155618.700312-1-peter.griffin@linaro.org> References: <20231005155618.700312-1-peter.griffin@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Add gs101-pmu compatible to the bindings documentation. Signed-off-by: Peter Griffin --- Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml index e1d716df5dfa..e6abf7b55909 100644 --- a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml @@ -27,6 +27,7 @@ select: - samsung,exynos7-pmu - samsung,exynos850-pmu - samsung-s5pv210-pmu + - google,gs101-pmu required: - compatible @@ -47,6 +48,7 @@ properties: - samsung,exynos7-pmu - samsung,exynos850-pmu - samsung-s5pv210-pmu + - google,gs101-pmu - const: syscon - items: - enum: From patchwork Thu Oct 5 15:56:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Griffin X-Patchwork-Id: 1843983 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=dwGhxgLZ; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=permerror (SPF Permanent Error: More than 10 MX records returned) smtp.mailfrom=vger.kernel.org (client-ip=2604:1380:45e3:2400::1; helo=sv.mirrors.kernel.org; envelope-from=devicetree+bounces-6194-incoming-dt=patchwork.ozlabs.org@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org [IPv6:2604:1380:45e3:2400::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4S1bmY1h8Mz23jN for ; Fri, 6 Oct 2023 02:57:33 +1100 (AEDT) Received: from smtp.subspace.kernel.org (conduit.subspace.kernel.org [100.90.174.1]) by sv.mirrors.kernel.org (Postfix) with ESMTP id CFF37282A03 for ; Thu, 5 Oct 2023 15:57:31 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id E0EE5328A8; Thu, 5 Oct 2023 15:57:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="dwGhxgLZ" X-Original-To: devicetree@vger.kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0DBE431A8F for ; Thu, 5 Oct 2023 15:57:28 +0000 (UTC) Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7876185DB3 for ; Thu, 5 Oct 2023 08:57:25 -0700 (PDT) Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-32615eaa312so1110715f8f.2 for ; Thu, 05 Oct 2023 08:57:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1696521444; x=1697126244; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dqGxynjd2WPI1dcd+xfmUDs2mxNl3KtmyJFW0p/wctU=; b=dwGhxgLZi7YRLBQftSjLjjY7VD2il1J05qW/5YBdSnUsolZHGmnKeI/CQqpJ19sS7q +uoRAsa5BeO+gcbBkuLfV4TO1lnx8fKzXMRoiJVL3UbaVVndwAVihH2qFofkk8P7YUni 7zFDiwUc2EOsx+G1w1Jebr2A2LeF22aQgqgFDFSMDAQlqufMrnm25KgPxCYCtEs2FwKm fOJV1LIDb6CfRxL/HFOxg3PxVwDC6hX2i+CUQczl4HvPWisuIzbr6EE/KRqQt3jk2ZHj DZhY5sa7U+okVVw65pMHyiEvVt3yx/cryPc2UUBf/hTGS586Nsu2LmYXbxQRrlI/2g5E If1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696521444; x=1697126244; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dqGxynjd2WPI1dcd+xfmUDs2mxNl3KtmyJFW0p/wctU=; b=ioxX6NLVYKjtPpwbCyiiIoiTWKYzmlrxXx7bmHP2gsIL/fZ9CSl6Ma8LvccovhZG+J AAVg0cJrDx4eh2AVAc/vefT5hEvY+DKBfgH/tg8PnXDP/8GHFOEu/zIHno7KBvahiAeR hNoDSSV33jv8RPr+UNwdUvfIxXJVoXMFc9FyDrgpE6M8XOQMVIVlKKeHl1pZSp2v9vm5 F7bL7W0i5bLa1YM6UhCvG0uvxLK5GSoB8X6mbu6IO2sBalgGu6/6Wax9Ky7noXCLq/0Y dCo3eIQEMjwSeKJ5dVn0ANFCwhA5/rLsn3MeBACzbRSi+LGhcIgovCiG0TLevnDKnZRY v4DA== X-Gm-Message-State: AOJu0Yxd1oV/2UFYiaDw3bpoGBd9msYhp1iJUwHKofg1NBuQfFL+8QHL YurNAQlVqtjfgrp2RV/AVYR2Ow== X-Google-Smtp-Source: AGHT+IFVvYSS2Teb+3C+yTzocwyuLqySOLh37A4RBSXTHwdRSE57cXIgg0jBOZT62IFM/d6hCX7Abw== X-Received: by 2002:adf:e8cc:0:b0:322:da1f:60d9 with SMTP id k12-20020adfe8cc000000b00322da1f60d9mr5392415wrn.47.1696521443734; Thu, 05 Oct 2023 08:57:23 -0700 (PDT) Received: from gpeter-l.lan (host-92-12-225-146.as13285.net. [92.12.225.146]) by smtp.gmail.com with ESMTPSA id t9-20020a5d4609000000b0031f8a59dbeasm2084336wrq.62.2023.10.05.08.57.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Oct 2023 08:57:23 -0700 (PDT) From: Peter Griffin To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, conor+dt@kernel.org, sboyd@kernel.org, tomasz.figa@gmail.com, s.nawrocki@samsung.com, linus.walleij@linaro.org, wim@linux-watchdog.org, linux@roeck-us.net, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, olof@lixom.net, cw00.choi@samsung.com Cc: peter.griffin@linaro.org, tudor.ambarus@linaro.org, andre.draszik@linaro.org, semen.protsenko@linaro.org, soc@kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-watchdog@vger.kernel.org Subject: [PATCH 03/21] dt-bindings: clock: Add Google gs101 clock management unit bindings Date: Thu, 5 Oct 2023 16:56:00 +0100 Message-ID: <20231005155618.700312-4-peter.griffin@linaro.org> X-Mailer: git-send-email 2.42.0.582.g8ccd20d70d-goog In-Reply-To: <20231005155618.700312-1-peter.griffin@linaro.org> References: <20231005155618.700312-1-peter.griffin@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Provide dt-schema documentation for Google gs101 SoC clock controller. Signed-off-by: Peter Griffin --- .../bindings/clock/google,gs101-clock.yaml | 109 ++++++++++++++++++ 1 file changed, 109 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/google,gs101-clock.yaml diff --git a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml new file mode 100644 index 000000000000..a28d05d88afe --- /dev/null +++ b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml @@ -0,0 +1,109 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/google,gs101-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Google GS101 SoC clock controller + +maintainers: + - Peter Griffin + +description: | + Google GS101 clock controller is comprised of several CMU units, generating + clocks for different domains. Those CMU units are modeled as separate device + tree nodes, and might depend on each other. The root clock in that clock tree + is OSCCLK (24.576 MHz). That external clock must be defined as a fixed-rate + clock in dts. + + CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and + dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP. + + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All clocks available for usage + in clock consumer nodes are defined as preprocessor macros in + 'dt-bindings/clock/gs101.h' header. + +properties: + compatible: + enum: + - google,gs101-cmu-top + - google,gs101-cmu-apm + - google,gs101-cmu-misc + + clocks: + minItems: 1 + maxItems: 5 + + clock-names: + minItems: 1 + maxItems: 5 + + "#clock-cells": + const: 1 + + reg: + maxItems: 1 + +allOf: + - if: + properties: + compatible: + contains: + const: google,gs101-cmu-top + + then: + properties: + clocks: + items: + - description: External reference clock (24.576 MHz) + + clock-names: + items: + - const: oscclk + + - if: + properties: + compatible: + contains: + const: google,gs101-cmu-misc + + then: + properties: + clocks: + items: + - description: External reference clock (24.576 MHz) + - description: Misc bus clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_cmu_misc_bus + +required: + - compatible + - "#clock-cells" + - clocks + - clock-names + - reg + +additionalProperties: false + +examples: + # Clock controller node for CMU_TOP + - | + #include + soc { + #address-cells = <2>; + #size-cells = <1>; + + cmu_top: clock-controller@1e080000 { + compatible = "google,gs101-cmu-top"; + reg = <0x0 0x1e080000 0x8000>; + #clock-cells = <1>; + clocks = <&ext_24_5m>; + clock-names = "oscclk"; + }; + }; + +... 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[92.12.225.146]) by smtp.gmail.com with ESMTPSA id t9-20020a5d4609000000b0031f8a59dbeasm2084336wrq.62.2023.10.05.08.57.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Oct 2023 08:57:24 -0700 (PDT) From: Peter Griffin To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, conor+dt@kernel.org, sboyd@kernel.org, tomasz.figa@gmail.com, s.nawrocki@samsung.com, linus.walleij@linaro.org, wim@linux-watchdog.org, linux@roeck-us.net, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, olof@lixom.net, cw00.choi@samsung.com Cc: peter.griffin@linaro.org, tudor.ambarus@linaro.org, andre.draszik@linaro.org, semen.protsenko@linaro.org, soc@kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-watchdog@vger.kernel.org Subject: [PATCH 04/21] dt-bindings: soc: google: exynos-sysreg: add dedicated SYSREG compatibles to GS101 Date: Thu, 5 Oct 2023 16:56:01 +0100 Message-ID: <20231005155618.700312-5-peter.griffin@linaro.org> X-Mailer: git-send-email 2.42.0.582.g8ccd20d70d-goog In-Reply-To: <20231005155618.700312-1-peter.griffin@linaro.org> References: <20231005155618.700312-1-peter.griffin@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net GS101 has three different SYSREG controllers, add dedicated compatibles for them to the documentation. Signed-off-by: Peter Griffin --- .../bindings/soc/samsung/samsung,exynos-sysreg.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml index 163e912e9cad..02f580d6489b 100644 --- a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml @@ -50,6 +50,13 @@ properties: - samsung,exynosautov9-peric1-sysreg - const: samsung,exynosautov9-sysreg - const: syscon + - items: + - enum: + - google,gs101-peric0-sysreg + - google,gs101-peric1-sysreg + - google,gs101-apm-sysreg + - const: google,gs101-sysreg + - const: syscon reg: maxItems: 1 From patchwork Thu Oct 5 15:56:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Griffin X-Patchwork-Id: 1843985 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=AbQZamJf; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=permerror (SPF Permanent Error: More than 10 MX records returned) smtp.mailfrom=vger.kernel.org (client-ip=139.178.88.99; helo=sv.mirrors.kernel.org; envelope-from=devicetree+bounces-6196-incoming-dt=patchwork.ozlabs.org@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org [139.178.88.99]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4S1bmb2xXDz1yng for ; Fri, 6 Oct 2023 02:57:35 +1100 (AEDT) Received: from smtp.subspace.kernel.org (conduit.subspace.kernel.org [100.90.174.1]) by sv.mirrors.kernel.org (Postfix) with ESMTP id 28E41282A5E for ; Thu, 5 Oct 2023 15:57:34 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C611931A96; Thu, 5 Oct 2023 15:57:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="AbQZamJf" X-Original-To: devicetree@vger.kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 81D3030FB8 for ; Thu, 5 Oct 2023 15:57:31 +0000 (UTC) Received: from mail-wm1-x336.google.com (mail-wm1-x336.google.com [IPv6:2a00:1450:4864:20::336]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A7D3186811 for ; Thu, 5 Oct 2023 08:57:28 -0700 (PDT) Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-40537481094so10222105e9.0 for ; Thu, 05 Oct 2023 08:57:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1696521446; x=1697126246; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xm1Xoms6oZd6xtVAii0x+Ehd7QscBFZjC7N/3rM4L+E=; b=AbQZamJfp1IPbiUPXSmmAsLLQmEA3T1t7xh+w7asSiyjfiE0qjoH4Fs3u1UeeohUq9 Czuk9yuTlYjzysGOe1Dv2pJJDCwqk+bnkU3KxitfjpRolhLh96/upJYn0QjqTaI2UT+0 yNWNKTIeVxp+JvfjMGhxjyWY7+kXbXJmNejWwM5ScUD3Ac3fhRSW6hz4HN6C7bmIMpsa A9LaTEeTK2NEMwyD0SGk0BaVHaKFygv/QObVt5C8Ck4GObzbPCFw9fKvNtPHprgOfZ6j mmDCpjq1nQE6DpAsz4oGQ64JH9DbjDx8MBEvMw+xWQ9y6oX8d3dmsqm3d3MMKWaA7MFg uA4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696521446; x=1697126246; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xm1Xoms6oZd6xtVAii0x+Ehd7QscBFZjC7N/3rM4L+E=; b=WkhCzzP6yjtezKXLl9THRW95flHB8rpO/qlYmvDkbvYLHIb7LC9PVFr1Yy3vezrNYZ LqmFyWjEOOyFh9s/TigYIGUMjxWDmKlPCUse2e+vj4G5Kh7A6BfhxNGX3s92HVT9WExh lTYmMKFhao0U48X0ErB9pL6je4PbJ5kU7rYV+Ef+7ARGM3fQaJqTLBern6FSO3xNC8zE cSYwd7VT6FMOa8VikgsxTFmodPM5lftVKAQLyyrDsdA1wh6Pn8P49EW3Qci5qup9J8T3 0L550OXgfoj1TT1c53b1UZprSeOoPZniUPlmpqUN+u/dwfhljtnuKXvzdyKoiiRANjJF PZNQ== X-Gm-Message-State: AOJu0Yxj0o9dZzPwt5CKpGWfDpsPd0EvZD31Z4wYdvEv0R+edNJwfIgD 4+qQ4QLVkMlTtP6xGM4nTyelmw== X-Google-Smtp-Source: AGHT+IEMvnjwfd4IeLtIJsxbXTd4pMr2IsgDm+E4xxpemwktFFHqJeH+cuxPlOWDyzgeNbQFbEBaMA== X-Received: by 2002:a5d:4c4a:0:b0:322:478b:2be9 with SMTP id n10-20020a5d4c4a000000b00322478b2be9mr5294165wrt.25.1696521446692; Thu, 05 Oct 2023 08:57:26 -0700 (PDT) Received: from gpeter-l.lan (host-92-12-225-146.as13285.net. [92.12.225.146]) by smtp.gmail.com with ESMTPSA id t9-20020a5d4609000000b0031f8a59dbeasm2084336wrq.62.2023.10.05.08.57.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Oct 2023 08:57:26 -0700 (PDT) From: Peter Griffin To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, conor+dt@kernel.org, sboyd@kernel.org, tomasz.figa@gmail.com, s.nawrocki@samsung.com, linus.walleij@linaro.org, wim@linux-watchdog.org, linux@roeck-us.net, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, olof@lixom.net, cw00.choi@samsung.com Cc: peter.griffin@linaro.org, tudor.ambarus@linaro.org, andre.draszik@linaro.org, semen.protsenko@linaro.org, soc@kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-watchdog@vger.kernel.org Subject: [PATCH 05/21] dt-bindings: watchdog: Document Google gs101 & gs201 watchdog bindings Date: Thu, 5 Oct 2023 16:56:02 +0100 Message-ID: <20231005155618.700312-6-peter.griffin@linaro.org> X-Mailer: git-send-email 2.42.0.582.g8ccd20d70d-goog In-Reply-To: <20231005155618.700312-1-peter.griffin@linaro.org> References: <20231005155618.700312-1-peter.griffin@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Add the "google,gs101-wdt" and "google,gs201-wdt" compatibles to the dt-schema documentation. gs101 SoC has two CPU clusters and each cluster has its own dedicated watchdog timer (similar to exynos850 and exynosautov9 SoCs). These WDT instances are controlled using different bits in PMU registers. Signed-off-by: Peter Griffin --- .../devicetree/bindings/watchdog/samsung-wdt.yaml | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml index 8fb6656ba0c2..30f5949037fc 100644 --- a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml @@ -24,6 +24,8 @@ properties: - samsung,exynos7-wdt # for Exynos7 - samsung,exynos850-wdt # for Exynos850 - samsung,exynosautov9-wdt # for Exynosautov9 + - google,gs101-wdt # for Google gs101 + - google,gs201-wdt # for Google gs101 reg: maxItems: 1 @@ -42,13 +44,13 @@ properties: samsung,cluster-index: $ref: /schemas/types.yaml#/definitions/uint32 description: - Index of CPU cluster on which watchdog is running (in case of Exynos850) + Index of CPU cluster on which watchdog is running (in case of Exynos850 or Google gsx01) samsung,syscon-phandle: $ref: /schemas/types.yaml#/definitions/phandle description: Phandle to the PMU system controller node (in case of Exynos5250, - Exynos5420, Exynos7 and Exynos850). + Exynos5420, Exynos7, Exynos850 and gsx01). required: - compatible @@ -69,6 +71,8 @@ allOf: - samsung,exynos7-wdt - samsung,exynos850-wdt - samsung,exynosautov9-wdt + - google,gs101-wdt + - google,gs201-wdt then: required: - samsung,syscon-phandle @@ -79,6 +83,8 @@ allOf: enum: - samsung,exynos850-wdt - samsung,exynosautov9-wdt + - google,gs101-wdt + - google,gs201-wdt then: properties: clocks: From patchwork Thu Oct 5 15:56:03 2023 Content-Type: text/plain; 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[92.12.225.146]) by smtp.gmail.com with ESMTPSA id t9-20020a5d4609000000b0031f8a59dbeasm2084336wrq.62.2023.10.05.08.57.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Oct 2023 08:57:27 -0700 (PDT) From: Peter Griffin To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, conor+dt@kernel.org, sboyd@kernel.org, tomasz.figa@gmail.com, s.nawrocki@samsung.com, linus.walleij@linaro.org, wim@linux-watchdog.org, linux@roeck-us.net, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, olof@lixom.net, cw00.choi@samsung.com Cc: peter.griffin@linaro.org, tudor.ambarus@linaro.org, andre.draszik@linaro.org, semen.protsenko@linaro.org, soc@kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-watchdog@vger.kernel.org Subject: [PATCH 06/21] dt-bindings: arm: google: Add bindings for Google ARM platforms Date: Thu, 5 Oct 2023 16:56:03 +0100 Message-ID: <20231005155618.700312-7-peter.griffin@linaro.org> X-Mailer: git-send-email 2.42.0.582.g8ccd20d70d-goog In-Reply-To: <20231005155618.700312-1-peter.griffin@linaro.org> References: <20231005155618.700312-1-peter.griffin@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net This introduces bindings and dt-schema for the Google tensor SoCs. Currently just gs101 and pixel 6 are supported. Signed-off-by: Peter Griffin Reviewed-by: Rob Herring --- .../devicetree/bindings/arm/google.yaml | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/google.yaml diff --git a/Documentation/devicetree/bindings/arm/google.yaml b/Documentation/devicetree/bindings/arm/google.yaml new file mode 100644 index 000000000000..3759d423d9cb --- /dev/null +++ b/Documentation/devicetree/bindings/arm/google.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/google.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Google Tensor platforms + +maintainers: + - Peter Griffin + +description: | + ARM platforms using SoCs designed by Google branded "Tensor" + used in Pixel devices. + + Currently upstream this is devices using "gs101" SoC which + is found in Pixel 6, Pixel 6 Pro and Pixel 6a. + + Google have a few different names for the SoC. + - Marketing name ("Tensor") + - Codename ("Whitechapel") + - SoC ID ("gs101") + - Die ID ("S5P9845"); + + Likewise there are a couple of names for the actual device + - Marketing name ("Pixel 6") + - Codename ("Oriole") + + Devicetrees should use the lowercased SoC ID and lowercased + board codename. e.g. gs101 and gs101-oriole + +properties: + $nodename: + const: '/' + compatible: + oneOf: + + - description: Google Pixel 6 / Oriole + items: + - enum: + - google,gs101-oriole + - const: google,gs101 + +additionalProperties: true + +... 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[92.12.225.146]) by smtp.gmail.com with ESMTPSA id t9-20020a5d4609000000b0031f8a59dbeasm2084336wrq.62.2023.10.05.08.57.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Oct 2023 08:57:29 -0700 (PDT) From: Peter Griffin To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, conor+dt@kernel.org, sboyd@kernel.org, tomasz.figa@gmail.com, s.nawrocki@samsung.com, linus.walleij@linaro.org, wim@linux-watchdog.org, linux@roeck-us.net, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, olof@lixom.net, cw00.choi@samsung.com Cc: peter.griffin@linaro.org, tudor.ambarus@linaro.org, andre.draszik@linaro.org, semen.protsenko@linaro.org, soc@kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-watchdog@vger.kernel.org Subject: [PATCH 07/21] dt-bindings: pinctrl: samsung: add google,gs101-pinctrl compatible Date: Thu, 5 Oct 2023 16:56:04 +0100 Message-ID: <20231005155618.700312-8-peter.griffin@linaro.org> X-Mailer: git-send-email 2.42.0.582.g8ccd20d70d-goog In-Reply-To: <20231005155618.700312-1-peter.griffin@linaro.org> References: <20231005155618.700312-1-peter.griffin@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Add the "google,gs101-pinctrl" compatible to the dt-schema bindings documentation. Add maxItems of 50 for the interrupts property as gs101 can have multiple irqs. Signed-off-by: Peter Griffin --- .../devicetree/bindings/pinctrl/samsung,pinctrl.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml index 26614621774a..e0f37f8ae8e7 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml @@ -54,11 +54,13 @@ properties: - samsung,exynos850-pinctrl - samsung,exynosautov9-pinctrl - tesla,fsd-pinctrl + - google,gs101-pinctrl interrupts: description: Required for GPIO banks supporting external GPIO interrupts. - maxItems: 1 + minItems: 1 + maxItems: 50 power-domains: maxItems: 1 From patchwork Thu Oct 5 15:56:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Griffin X-Patchwork-Id: 1843989 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=KiKTGGxB; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=permerror (SPF Permanent Error: More than 10 MX records returned) smtp.mailfrom=vger.kernel.org (client-ip=2604:1380:45d1:ec00::1; helo=ny.mirrors.kernel.org; envelope-from=devicetree+bounces-6199-incoming-dt=patchwork.ozlabs.org@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org [IPv6:2604:1380:45d1:ec00::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4S1bmh6RMfz23jN for ; Fri, 6 Oct 2023 02:57:40 +1100 (AEDT) Received: from smtp.subspace.kernel.org (conduit.subspace.kernel.org [100.90.174.1]) by ny.mirrors.kernel.org (Postfix) with ESMTP id 8A0F91C20953 for ; Thu, 5 Oct 2023 15:57:37 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id A78F431A96; Thu, 5 Oct 2023 15:57:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="KiKTGGxB" X-Original-To: devicetree@vger.kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D57D0328A8 for ; Thu, 5 Oct 2023 15:57:34 +0000 (UTC) Received: from mail-wr1-x432.google.com (mail-wr1-x432.google.com [IPv6:2a00:1450:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C668386837 for ; Thu, 5 Oct 2023 08:57:32 -0700 (PDT) Received: by mail-wr1-x432.google.com with SMTP id ffacd0b85a97d-32488a22810so1039865f8f.3 for ; Thu, 05 Oct 2023 08:57:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1696521451; x=1697126251; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ylH3r2N4huNUb7il+GAvao+h0OGeqDeAdkjyqYnsGYw=; b=KiKTGGxBP6ZDFcKpuUl9/FXoOpG6W9/PCwrOD8gEpkVDDVnNjIQpMqIemF7mvLN4mi 3bdUQFYAEkMxpCCEcdvgaJCSCFw0wEcwMNBL6DShp0JfirJZIAgMsnd35mk7Xqsme7sy RJxn8gA7UtpZ1RyX/V18ofP4e3XksSjmTq/IW6CcLKrlT5MpgA2y1QuJl2+4sXI85MuI LK8t9iiM8jT0LXv3jHPD89pilNQM64ilkqUdraBLQB2iqaf7prTGe9EHhFfg9hKcCocF zqfUBjHrkMgPyMvsy+jQ5kTWJCybS0AlFloapCly/g1pJI1wi6S6p6eYC0GO+LpFObg/ m1bA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696521451; x=1697126251; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ylH3r2N4huNUb7il+GAvao+h0OGeqDeAdkjyqYnsGYw=; b=akkpIbC1/U5Cs4f1zTFI9sd0n2q0vKzSa0A0dUIq61LSdiI7aVAu98bPFSL3JxMIb1 qDNPJ5j5cNtns8W8mZh0qNzFkN+y6U5OE2I16xnVkv3FNxSwIPuHqDWPN+V7cJI0WJtm LUszUW87P2wuCSoV8IfcavwC9MXZA20RXr+F0/KCqC1i2wrFh81+S2tVMHRn2oTSNGRl qSwhD2phvxGUyCzEGQyRDZHhSP3KgcY/GA4Lys1IqFvkWVvgHa2STUGsrx71gPAK//LF 63k9rNEpjzYC2+Z7Cfo5jmR/Bt3/0nMS0dwy3ioBCvLqKflN27R1MK51GoJ253jYB+8E ac0w== X-Gm-Message-State: AOJu0Yyy7a3oIaRrzGVuWEtDrhaqJ3YH4A3MkfEJ1Bg7vtTu5JVAGJ9K OUcUyZPQNFCOpVQ2DaZhRdNriw== X-Google-Smtp-Source: AGHT+IEPYyyM2IMYe/RJ0phQWyT/Pm8leTRtBdwsfcRau9xe1hKp1zxU0tWr3ekNb0EMRyzrKcPhlA== X-Received: by 2002:a5d:4d12:0:b0:323:16c0:9531 with SMTP id z18-20020a5d4d12000000b0032316c09531mr5128395wrt.13.1696521451269; Thu, 05 Oct 2023 08:57:31 -0700 (PDT) Received: from gpeter-l.lan (host-92-12-225-146.as13285.net. [92.12.225.146]) by smtp.gmail.com with ESMTPSA id t9-20020a5d4609000000b0031f8a59dbeasm2084336wrq.62.2023.10.05.08.57.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Oct 2023 08:57:30 -0700 (PDT) From: Peter Griffin To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, conor+dt@kernel.org, sboyd@kernel.org, tomasz.figa@gmail.com, s.nawrocki@samsung.com, linus.walleij@linaro.org, wim@linux-watchdog.org, linux@roeck-us.net, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, olof@lixom.net, cw00.choi@samsung.com Cc: peter.griffin@linaro.org, tudor.ambarus@linaro.org, andre.draszik@linaro.org, semen.protsenko@linaro.org, soc@kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-watchdog@vger.kernel.org Subject: [PATCH 08/21] dt-bindings: pinctrl: samsung: add gs101-wakeup-eint compatible Date: Thu, 5 Oct 2023 16:56:05 +0100 Message-ID: <20231005155618.700312-9-peter.griffin@linaro.org> X-Mailer: git-send-email 2.42.0.582.g8ccd20d70d-goog In-Reply-To: <20231005155618.700312-1-peter.griffin@linaro.org> References: <20231005155618.700312-1-peter.griffin@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net gs101 is similar to newer Exynos SoCs like Exynos850 and ExynosAutov9 where more than one pin controller can do external wake-up interrupt. So add a dedicated compatible for it. Signed-off-by: Peter Griffin --- .../bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml index 1de91a51234d..668fd903d06f 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml @@ -37,6 +37,7 @@ properties: - samsung,exynos7-wakeup-eint - samsung,exynos850-wakeup-eint - samsung,exynosautov9-wakeup-eint + - google,gs101-wakeup-eint interrupts: description: @@ -99,6 +100,7 @@ allOf: enum: - samsung,exynos850-wakeup-eint - samsung,exynosautov9-wakeup-eint + - google,gs101-wakeup-eint then: properties: interrupts: false From patchwork Thu Oct 5 15:56:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Griffin X-Patchwork-Id: 1843990 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=bolZ88a0; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=permerror (SPF Permanent Error: More than 10 MX records returned) smtp.mailfrom=vger.kernel.org (client-ip=147.75.48.161; helo=sy.mirrors.kernel.org; envelope-from=devicetree+bounces-6200-incoming-dt=patchwork.ozlabs.org@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org [147.75.48.161]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4S1bmj2dTyz26jT for ; Fri, 6 Oct 2023 02:57:41 +1100 (AEDT) Received: from smtp.subspace.kernel.org (conduit.subspace.kernel.org [100.90.174.1]) by sy.mirrors.kernel.org (Postfix) with ESMTP id 6C0A0B2098D for ; Thu, 5 Oct 2023 15:57:40 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 6361031A9F; Thu, 5 Oct 2023 15:57:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="bolZ88a0" X-Original-To: devicetree@vger.kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4A09C328A8 for ; Thu, 5 Oct 2023 15:57:37 +0000 (UTC) Received: from mail-wr1-x432.google.com (mail-wr1-x432.google.com [IPv6:2a00:1450:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3FC9286811 for ; Thu, 5 Oct 2023 08:57:34 -0700 (PDT) Received: by mail-wr1-x432.google.com with SMTP id ffacd0b85a97d-3214cdb4b27so1141820f8f.1 for ; Thu, 05 Oct 2023 08:57:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1696521452; x=1697126252; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=d11cqKfS+fdxtmrtzzZxvBU5OTmGMgE/XCozhQBkInQ=; b=bolZ88a0qh+aaO+SvY1rYXgLvMveRT0hAU94nU6iInNhb2Jeya1jffxpvoB6en3bFU ccOCAx+kzaq6JNgSBHJ3GKIS68hRhSGeDWNZzUqn+qs8x6KwvPzgeLi4j+vk5S3k+2Nr EZivjsGOVAfSQeBn2Uos2x7rcWu3w4h3LzUDHDIcjoQ1/Upfk3HyY61cPTA/pbSV2gDt 2PYvOFpqicIaTIAgaPx0tJrFyLxB2hty1zEQHHVIorFoqcJ6sZ7l8/RNpTYg4Z2oy4UC krqa7Ql2hboQmnOmWNd6jGysl/OS7PAW7JnECNJICLKT0PXVqj6f0Sbjc5OgXyzBi32N ZIaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696521452; x=1697126252; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=d11cqKfS+fdxtmrtzzZxvBU5OTmGMgE/XCozhQBkInQ=; b=hG3+m6pqN9Ao0Ayq/cck2TQXmpTKq58CBe+dLwzNNXmxpMM4YBSocUXbwBm/zAuW9Z 7arxUu3tmFSo/u5hvmg5ta3ySIx1dSxbGSeBAWR1rVHNZnc0V1eMhINFNTT7kAQFDA6g 5ESsTAL/n7fOmiDjP8gRoNnkC5PH8x07pp166heSwXQsid6BmZaUhS+8XaFuOTiKHTEu v1+a/iLsTDYWns6tteOGEnrXHMn0ZvHIKc2UITjpVeO1FEHtwvLu7QzeFeyI6EgwVkE+ xjJUToUY0/mUrGbLzALYOBjPds6RlyCBaaYV7d0QAyqptd6MLD+KJdz4wVVxEMDyMP9r 1+3w== X-Gm-Message-State: AOJu0Ywh5IL5exxZsZkczbcSz4k8EP5hAF7iKWI8qjfCXjZHTy31qWzd 45UdRyrwVQQilINqVRhV8yRGWw== X-Google-Smtp-Source: AGHT+IF5JxaO9+rCy97IxTy5wUsRkgWUCcXCf+iMUE0xXftzVtEU+uJrHfiP+TqDv55krBbjdkA52Q== X-Received: by 2002:adf:ec52:0:b0:321:6de5:68b4 with SMTP id w18-20020adfec52000000b003216de568b4mr5417975wrn.52.1696521452740; Thu, 05 Oct 2023 08:57:32 -0700 (PDT) Received: from gpeter-l.lan (host-92-12-225-146.as13285.net. [92.12.225.146]) by smtp.gmail.com with ESMTPSA id t9-20020a5d4609000000b0031f8a59dbeasm2084336wrq.62.2023.10.05.08.57.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Oct 2023 08:57:32 -0700 (PDT) From: Peter Griffin To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, conor+dt@kernel.org, sboyd@kernel.org, tomasz.figa@gmail.com, s.nawrocki@samsung.com, linus.walleij@linaro.org, wim@linux-watchdog.org, linux@roeck-us.net, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, olof@lixom.net, cw00.choi@samsung.com Cc: peter.griffin@linaro.org, tudor.ambarus@linaro.org, andre.draszik@linaro.org, semen.protsenko@linaro.org, soc@kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-watchdog@vger.kernel.org Subject: [PATCH 09/21] dt-bindings: clock: gs101: Add cmu_top clock indices Date: Thu, 5 Oct 2023 16:56:06 +0100 Message-ID: <20231005155618.700312-10-peter.griffin@linaro.org> X-Mailer: git-send-email 2.42.0.582.g8ccd20d70d-goog In-Reply-To: <20231005155618.700312-1-peter.griffin@linaro.org> References: <20231005155618.700312-1-peter.griffin@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,UPPERCASE_50_75,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net CMU_TOP geneerates clocks for all the other CMU units. Add clock indices for those PLLs, muxes, dividers and gates. Signed-off-by: Peter Griffin --- include/dt-bindings/clock/gs101.h | 204 ++++++++++++++++++++++++++++++ 1 file changed, 204 insertions(+) create mode 100644 include/dt-bindings/clock/gs101.h diff --git a/include/dt-bindings/clock/gs101.h b/include/dt-bindings/clock/gs101.h new file mode 100644 index 000000000000..d1e216a33aeb --- /dev/null +++ b/include/dt-bindings/clock/gs101.h @@ -0,0 +1,204 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2023 Linaro Ltd. + * Author: Peter Griffin + * + * Device Tree binding constants for Google gs101 clock controller. + */ + +#ifndef _DT_BINDINGS_CLOCK_GOOGLE_GS101_H +#define _DT_BINDINGS_CLOCK_GOOGLE_GS101_H + +/* CMU_TOP PLL*/ +#define CLK_FOUT_SHARED0_PLL 1 +#define CLK_FOUT_SHARED1_PLL 2 +#define CLK_FOUT_SHARED2_PLL 3 +#define CLK_FOUT_SHARED3_PLL 4 +#define CLK_FOUT_SPARE_PLL 5 + +/* CMU_TOP MUX*/ +#define CLK_MOUT_SHARED0_PLL 6 +#define CLK_MOUT_SHARED1_PLL 7 +#define CLK_MOUT_SHARED2_PLL 8 +#define CLK_MOUT_SHARED3_PLL 9 +#define CLK_MOUT_SPARE_PLL 10 +#define CLK_MOUT_BUS0_BUS 11 +#define CLK_MOUT_CMU_BOOST 12 +#define CLK_MOUT_BUS1_BUS 13 +#define CLK_MOUT_BUS2_BUS 14 +#define CLK_MOUT_CORE_BUS 15 +#define CLK_MOUT_EH_BUS 16 +#define CLK_MOUT_CPUCL2_SWITCH 17 +#define CLK_MOUT_CPUCL1_SWITCH 18 +#define CLK_MOUT_CPUCL0_SWITCH 19 +#define CLK_MOUT_CPUCL0_DBG 20 +#define CLK_MOUT_CMU_HPM 21 +#define CLK_MOUT_G3D_SWITCH 22 +#define CLK_MOUT_G3D_GLB 23 +#define CLK_MOUT_DPU_BUS 24 +#define CLK_MOUT_DISP_BUS 25 +#define CLK_MOUT_G2D_G2D 26 +#define CLK_MOUT_G2D_MSCL 27 +#define CLK_MOUT_HSI0_USB31DRD 28 +#define CLK_MOUT_HSI0_BUS 29 +#define CLK_MOUT_HSI0_DPGTC 30 +#define CLK_MOUT_HSI0_USBDPDGB 31 +#define CLK_MOUT_HSI1_BUS 32 +#define CLK_MOUT_HSI1_PCIE 33 +#define CLK_MOUT_HSI2_BUS 34 +#define CLK_MOUT_HSI2_PCIE 35 +#define CLK_MOUT_HSI2_UFS_EMBD 36 +#define CLK_MOUT_HSI2_MMC_CARD 37 +#define CLK_MOUT_CSIS 38 +#define CLK_MOUT_PDP_BUS 39 +#define CLK_MOUT_PDP_VRA 40 +#define CLK_MOUT_IPP_BUS 41 +#define CLK_MOUT_G3AA 42 +#define CLK_MOUT_ITP 43 +#define CLK_MOUT_DNS_BUS 44 +#define CLK_MOUT_TNR_BUS 45 +#define CLK_MOUT_MCSC_ITSC 46 +#define CLK_MOUT_MCSC_MCSC 47 +#define CLK_MOUT_GDC_SCSC 48 +#define CLK_MOUT_GDC_GDC0 49 +#define CLK_MOUT_GDC_GDC1 50 +#define CLK_MOUT_MFC_MFC 51 +#define CLK_MOUT_MIF_SWITCH 52 +#define CLK_MOUT_MIF_BUS 53 +#define CLK_MOUT_MISC_BUS 54 +#define CLK_MOUT_MISC_SSS 55 +#define CLK_MOUT_PERIC0_IP 56 +#define CLK_MOUT_PERIC0_BUS 57 +#define CLK_MOUT_PERIC1_IP 58 +#define CLK_MOUT_PERIC1_BUS 59 +#define CLK_MOUT_TPU_TPU 60 +#define CLK_MOUT_TPU_TPUCTL 61 +#define CLK_MOUT_TPU_BUS 62 +#define CLK_MOUT_TPU_UART 63 +#define CLK_MOUT_TPU_HPM 64 +#define CLK_MOUT_BO_BUS 65 +#define CLK_MOUT_G3D_BUSD 66 + +/* CMU_TOP Dividers*/ +#define CLK_DOUT_SHARED0_DIV3 67 +#define CLK_DOUT_SHARED0_DIV2 68 +#define CLK_DOUT_SHARED0_DIV4 69 +#define CLK_DOUT_SHARED0_DIV5 70 +#define CLK_DOUT_SHARED1_DIV3 71 +#define CLK_DOUT_SHARED1_DIV2 72 +#define CLK_DOUT_SHARED1_DIV4 73 +#define CLK_DOUT_SHARED2_DIV2 74 +#define CLK_DOUT_SHARED3_DIV2 75 +#define CLK_DOUT_BUS0_BUS 76 +#define CLK_DOUT_CMU_BOOST 77 +#define CLK_DOUT_BUS1_BUS 78 +#define CLK_DOUT_BUS2_BUS 79 +#define CLK_DOUT_CORE_BUS 80 +#define CLK_DOUT_EH_BUS 81 +#define CLK_DOUT_CPUCL2_SWITCH 82 +#define CLK_DOUT_CPUCL1_SWITCH 83 +#define CLK_DOUT_CPUCL0_SWITCH 84 +#define CLK_DOUT_CPUCL0_DBG 85 +#define CLK_DOUT_CMU_HPM 86 +#define CLK_DOUT_G3D_SWITCH 87 +#define CLK_DOUT_G3D_GLB 88 +#define CLK_DOUT_DPU_BUS 89 +#define CLK_DOUT_DISP_BUS 90 +#define CLK_DOUT_G2D_G2D 91 +#define CLK_DOUT_G2D_MSCL 92 +#define CLK_DOUT_HSI0_USB31DRD 93 +#define CLK_DOUT_HSI0_BUS 94 +#define CLK_DOUT_HSI0_DPGTC 95 +#define CLK_DOUT_HSI0_USBDPDGB 96 +#define CLK_DOUT_HSI1_BUS 97 +#define CLK_DOUT_HSI1_PCIE 98 +#define CLK_DOUT_HSI2_BUS 100 +#define CLK_DOUT_HSI2_PCIE 101 +#define CLK_DOUT_HSI2_UFS_EMBD 102 +#define CLK_DOUT_HSI2_MMC_CARD 103 +#define CLK_DOUT_CSIS 104 +#define CLK_DOUT_PDP_BUS 105 +#define CLK_DOUT_PDP_VRA 106 +#define CLK_DOUT_IPP_BUS 107 +#define CLK_DOUT_G3AA 108 +#define CLK_DOUT_ITP 109 +#define CLK_DOUT_DNS_BUS 110 +#define CLK_DOUT_TNR_BUS 111 +#define CLK_DOUT_MCSC_ITSC 112 +#define CLK_DOUT_MCSC_MCSC 113 +#define CLK_DOUT_GDC_SCSC 114 +#define CLK_DOUT_GDC_GDC0 115 +#define CLK_DOUT_GDC_GDC1 116 +#define CLK_DOUT_MFC_MFC 117 +#define CLK_DOUT_MIF_BUS 118 +#define CLK_DOUT_MISC_BUS 119 +#define CLK_DOUT_MISC_SSS 120 +#define CLK_DOUT_PERIC0_BUS 121 +#define CLK_DOUT_PERIC0_IP 122 +#define CLK_DOUT_PERIC1_BUS 123 +#define CLK_DOUT_PERIC1_IP 124 +#define CLK_DOUT_TPU_TPU 125 +#define CLK_DOUT_TPU_TPUCTL 126 +#define CLK_DOUT_TPU_BUS 127 +#define CLK_DOUT_TPU_UART 128 +#define CLK_DOUT_TPU_HPM 129 +#define CLK_DOUT_BO_BUS 130 + +/* CMU_TOP Gates*/ +#define CLK_GOUT_BUS0_BUS 131 +#define CLK_GOUT_BUS1_BUS 132 +#define CLK_GOUT_BUS2_BUS 133 +#define CLK_GOUT_CORE_BUS 134 +#define CLK_GOUT_EH_BUS 135 +#define CLK_GOUT_CPUCL2_SWITCH 136 +#define CLK_GOUT_CPUCL1_SWITCH 137 +#define CLK_GOUT_CPUCL0_SWITCH 138 +#define CLK_GOUT_CPUCL0_DBG 139 +#define CLK_GOUT_CMU_HPM 140 +#define CLK_GOUT_G3D_SWITCH 141 +#define CLK_GOUT_G3D_GLB 142 +#define CLK_GOUT_DPU_BUS 143 +#define CLK_GOUT_DISP_BUS 144 +#define CLK_GOUT_G2D_G2D 145 +#define CLK_GOUT_G2D_MSCL 146 +#define CLK_GOUT_HSI0_USB31DRD 147 +#define CLK_GOUT_HSI0_BUS 148 +#define CLK_GOUT_HSI0_DPGTC 149 +#define CLK_GOUT_HSI0_USBDPDGB 150 +#define CLK_GOUT_HSI1_BUS 151 +#define CLK_GOUT_HSI1_PCIE 152 +#define CLK_GOUT_HSI2_BUS 153 +#define CLK_GOUT_HSI2_PCIE 154 +#define CLK_GOUT_HSI2_UFS_EMBD 155 +#define CLK_GOUT_HSI2_MMC_CARD 156 +#define CLK_GOUT_CSIS 157 +#define CLK_GOUT_PDP_BUS 158 +#define CLK_GOUT_PDP_VRA 159 +#define CLK_GOUT_IPP_BUS 160 +#define CLK_GOUT_G3AA 161 +#define CLK_GOUT_ITP 162 +#define CLK_GOUT_DNS_BUS 163 +#define CLK_GOUT_TNR_BUS 164 +#define CLK_GOUT_MCSC_ITSC 165 +#define CLK_GOUT_MCSC_MCSC 166 +#define CLK_GOUT_GDC_SCSC 167 +#define CLK_GOUT_GDC_GDC0 168 +#define CLK_GOUT_GDC_GDC1 169 +#define CLK_GOUT_MFC_MFC 170 +#define CLK_GOUT_MIF_SWITCH 171 +#define CLK_GOUT_MIF_BUS 172 +#define CLK_GOUT_MISC_BUS 173 +#define CLK_GOUT_MISC_SSS 174 +#define CLK_GOUT_PERIC0_BUS 175 +#define CLK_GOUT_PERIC0_IP 176 +#define CLK_GOUT_PERIC1_BUS 177 +#define CLK_GOUT_PERIC1_IP 178 +#define CLK_GOUT_TPU_TPU 179 +#define CLK_GOUT_TPU_TPUCTL 180 +#define CLK_GOUT_TPU_BUS 181 +#define CLK_GOUT_TPU_UART 182 +#define CLK_GOUT_TPU_HPM 183 +#define CLK_GOUT_BO_BUS 184 +#define CLK_GOUT_CMU_BOOST 185 + +#endif /* _DT_BINDINGS_CLOCK_GOOGLE_GS101_H */ From patchwork Thu Oct 5 15:56:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Griffin X-Patchwork-Id: 1843992 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) 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[92.12.225.146]) by smtp.gmail.com with ESMTPSA id t9-20020a5d4609000000b0031f8a59dbeasm2084336wrq.62.2023.10.05.08.57.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Oct 2023 08:57:33 -0700 (PDT) From: Peter Griffin To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, conor+dt@kernel.org, sboyd@kernel.org, tomasz.figa@gmail.com, s.nawrocki@samsung.com, linus.walleij@linaro.org, wim@linux-watchdog.org, linux@roeck-us.net, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, olof@lixom.net, cw00.choi@samsung.com Cc: peter.griffin@linaro.org, tudor.ambarus@linaro.org, andre.draszik@linaro.org, semen.protsenko@linaro.org, soc@kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-watchdog@vger.kernel.org Subject: [PATCH 10/21] dt-bindings: clock: gs101: Add cmu_apm clock indices Date: Thu, 5 Oct 2023 16:56:07 +0100 Message-ID: <20231005155618.700312-11-peter.griffin@linaro.org> X-Mailer: git-send-email 2.42.0.582.g8ccd20d70d-goog In-Reply-To: <20231005155618.700312-1-peter.griffin@linaro.org> References: <20231005155618.700312-1-peter.griffin@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net CMU_APM generates clocks for the Active Power Management controller. Add clock indices for those muxs, dividers and gates. Signed-off-by: Peter Griffin --- include/dt-bindings/clock/gs101.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/include/dt-bindings/clock/gs101.h b/include/dt-bindings/clock/gs101.h index d1e216a33aeb..d9b8299fcc0b 100644 --- a/include/dt-bindings/clock/gs101.h +++ b/include/dt-bindings/clock/gs101.h @@ -201,4 +201,21 @@ #define CLK_GOUT_BO_BUS 184 #define CLK_GOUT_CMU_BOOST 185 +/* CMU_APM */ + +#define CLK_MOUT_APM_FUNC 1 +#define CLK_MOUT_APM_FUNCSRC 2 +#define CLK_DOUT_APM_BOOST 3 +#define CLK_DOUT_APM_USI0_UART 4 +#define CLK_DOUT_APM_USI0_USI 5 +#define CLK_DOUT_APM_USI1_UART 6 +#define CLK_GOUT_APM_FUNC 7 +#define CLK_GOUT_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK 8 +#define CLK_GOUT_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK 9 +#define CLK_GOUT_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK 10 +#define CLK_GOUT_APM_UID_SYSREG_APM_IPCLKPORT_PCLK 11 +#define CLK_APM_PLL_DIV2_APM 12 +#define CLK_APM_PLL_DIV4_APM 13 +#define CLK_APM_PLL_DIV16_APM 14 + #endif /* _DT_BINDINGS_CLOCK_GOOGLE_GS101_H */ From patchwork Thu Oct 5 15:56:08 2023 Content-Type: text/plain; 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[92.12.225.146]) by smtp.gmail.com with ESMTPSA id t9-20020a5d4609000000b0031f8a59dbeasm2084336wrq.62.2023.10.05.08.57.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Oct 2023 08:57:35 -0700 (PDT) From: Peter Griffin To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, conor+dt@kernel.org, sboyd@kernel.org, tomasz.figa@gmail.com, s.nawrocki@samsung.com, linus.walleij@linaro.org, wim@linux-watchdog.org, linux@roeck-us.net, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, olof@lixom.net, cw00.choi@samsung.com Cc: peter.griffin@linaro.org, tudor.ambarus@linaro.org, andre.draszik@linaro.org, semen.protsenko@linaro.org, soc@kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-watchdog@vger.kernel.org Subject: [PATCH 11/21] dt-bindings: clock: gs101: Add cmu_misc clock indices Date: Thu, 5 Oct 2023 16:56:08 +0100 Message-ID: <20231005155618.700312-12-peter.griffin@linaro.org> X-Mailer: git-send-email 2.42.0.582.g8ccd20d70d-goog In-Reply-To: <20231005155618.700312-1-peter.griffin@linaro.org> References: <20231005155618.700312-1-peter.griffin@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net CMU_MISC generates clocks for IPs such as Watchdog. Add clock indices for the PLLs, Muxes, dividers and gates in this clock management unit. Signed-off-by: Peter Griffin --- include/dt-bindings/clock/gs101.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/include/dt-bindings/clock/gs101.h b/include/dt-bindings/clock/gs101.h index d9b8299fcc0b..7765ba68f734 100644 --- a/include/dt-bindings/clock/gs101.h +++ b/include/dt-bindings/clock/gs101.h @@ -218,4 +218,15 @@ #define CLK_APM_PLL_DIV4_APM 13 #define CLK_APM_PLL_DIV16_APM 14 +/* CMU_MISC */ + +#define CLK_MOUT_MISC_BUS_USER 1 +#define CLK_MOUT_MISC_SSS_USER 2 +#define CLK_DOUT_MISC_BUSP 3 +#define CLK_DOUT_MISC_GIC 4 +#define CLK_GOUT_MISC_PCLK 5 +#define CLK_GOUT_MISC_SYSREG_PCLK 6 +#define CLK_GOUT_MISC_WDT_CLUSTER0 7 +#define CLK_GOUT_MISC_WDT_CLUSTER1 8 + #endif /* _DT_BINDINGS_CLOCK_GOOGLE_GS101_H */ From patchwork Thu Oct 5 15:56:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Griffin X-Patchwork-Id: 1843994 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=xqUf3uiv; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=permerror (SPF Permanent Error: More than 10 MX records returned) smtp.mailfrom=vger.kernel.org (client-ip=2604:1380:45e3:2400::1; helo=sv.mirrors.kernel.org; envelope-from=devicetree+bounces-6212-incoming-dt=patchwork.ozlabs.org@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org [IPv6:2604:1380:45e3:2400::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4S1bn950DTz1yng for ; Fri, 6 Oct 2023 02:58:05 +1100 (AEDT) Received: from smtp.subspace.kernel.org (conduit.subspace.kernel.org [100.90.174.1]) by sv.mirrors.kernel.org (Postfix) with ESMTP id 412EF282D01 for ; Thu, 5 Oct 2023 15:58:04 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id A9F8B33987; Thu, 5 Oct 2023 15:58:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="xqUf3uiv" X-Original-To: devicetree@vger.kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 80C32328D2 for ; Thu, 5 Oct 2023 15:57:59 +0000 (UTC) Received: from mail-wr1-x436.google.com (mail-wr1-x436.google.com [IPv6:2a00:1450:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C5C8959D5 for ; Thu, 5 Oct 2023 08:57:48 -0700 (PDT) Received: by mail-wr1-x436.google.com with SMTP id ffacd0b85a97d-325e9cd483eso1137047f8f.2 for ; Thu, 05 Oct 2023 08:57:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1696521467; x=1697126267; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Lym2EwtDrKeJJGvLKxCwm6sp2Mh1Q2fV1S+IW1hcq/c=; b=xqUf3uivX0t8CZt9vSF+qT0p0nT425jU37bYPUyuhJ2xvTlrPcE5ZqSfD+Egxwun8V BjxxzfZt18HUNKw64gSGPqEtVLPw/FPTmKmOhd0W4bAWCeKkBSdCvP/96CuKJiODU6ov Yel/SN2PU+wdiqFGye+Oqt2VTMDGJP+/0//cEjaOs4O90uTVyd9QyZZcC3PlO2oza6ZO T2z92FJe4Tl8TpwxVGwD2iy8KXPUkm455kIB5BEBFN6CSQItOuVWEQmj4GjWJ7p6r6zm DoNrn0416B7/p9jSEF3KUt1NCzBCJ/1neXGsIWlloBxaQr74EGI77y7A3KoTh75JgaqW Qpuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696521467; x=1697126267; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Lym2EwtDrKeJJGvLKxCwm6sp2Mh1Q2fV1S+IW1hcq/c=; b=Ei8oOHGNcuMMyC4YFSkSuoMFspvu7SEIQs8TTfn39nzcWa9OM3PaFw/ynBQMqdZm8y 3mep5Fq6CMLZa9nYWbkHzJNFz/KyvaYEBxP8JwxOsQdwHLxt0u47+IOIvQGdkC5MUlSA iq5/ROJ5nQ2K3xOs+5xTF9HWtJL98eBcm8N56P0c+2JnPsuoOOk8zZwtfc/r8k6F6lDM QFlLEXLfWjmKRTrwd6+qFZnQ3xYFLhNHYh+oIo2v+7i8ETOLqM20qb2Rc/QUSAp0xaoZ NNJIfuj8eBsvTOVniFcW+RFYZNlHS5yQB6fqULCWh190YKM1mq+78LF/huFZQHeXLwgz FDWQ== X-Gm-Message-State: AOJu0YzVNLDbxLFQcMCUSHijXX+mhIfX8ygQ3Z0VhfUwd33TzO91Na39 iiyHBuPRhTKX1UYXgUyBLRNjUA== X-Google-Smtp-Source: AGHT+IHjNGqv8KQPY2t+wEWDVvWP0MC2mIwicf7m+bRjT6v9j543ZdU02SxoePNAdoSlUs9QdQxalw== X-Received: by 2002:a5d:4a05:0:b0:31f:a277:4cde with SMTP id m5-20020a5d4a05000000b0031fa2774cdemr5589425wrq.43.1696521466987; Thu, 05 Oct 2023 08:57:46 -0700 (PDT) Received: from gpeter-l.lan (host-92-12-225-146.as13285.net. [92.12.225.146]) by smtp.gmail.com with ESMTPSA id t9-20020a5d4609000000b0031f8a59dbeasm2084336wrq.62.2023.10.05.08.57.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Oct 2023 08:57:46 -0700 (PDT) From: Peter Griffin To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, conor+dt@kernel.org, sboyd@kernel.org, tomasz.figa@gmail.com, s.nawrocki@samsung.com, linus.walleij@linaro.org, wim@linux-watchdog.org, linux@roeck-us.net, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, olof@lixom.net, cw00.choi@samsung.com Cc: peter.griffin@linaro.org, tudor.ambarus@linaro.org, andre.draszik@linaro.org, semen.protsenko@linaro.org, soc@kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-watchdog@vger.kernel.org Subject: [PATCH 18/21] arm64: dts: google: Add initial Google gs101 SoC support Date: Thu, 5 Oct 2023 16:56:15 +0100 Message-ID: <20231005155618.700312-19-peter.griffin@linaro.org> X-Mailer: git-send-email 2.42.0.582.g8ccd20d70d-goog In-Reply-To: <20231005155618.700312-1-peter.griffin@linaro.org> References: <20231005155618.700312-1-peter.griffin@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Google gs101 SoC is ARMv8 mobile SoC found in the Pixel 6, (oriole) Pixel 6a (bluejay) and Pixel 6 pro (raven) mobile phones. It features: * 4xA55 little cluster * 2xA76 Mid cluster * 2xX1 Big cluster This commit adds the basic device tree for gs101 (SoC) and oriole (pixel 6). Further platform support will be added over time. It has been tested with a minimal busybox initramfs and boots to a shell. Signed-off-by: Peter Griffin --- arch/arm64/Kconfig.platforms | 6 + arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/google/Makefile | 6 + arch/arm64/boot/dts/google/gs101-oriole.dts | 68 + arch/arm64/boot/dts/google/gs101-pinctrl.dtsi | 1134 +++++++++++++++++ arch/arm64/boot/dts/google/gs101-pinctrl.h | 17 + arch/arm64/boot/dts/google/gs101.dtsi | 501 ++++++++ 7 files changed, 1733 insertions(+) create mode 100644 arch/arm64/boot/dts/google/Makefile create mode 100644 arch/arm64/boot/dts/google/gs101-oriole.dts create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.h create mode 100644 arch/arm64/boot/dts/google/gs101.dtsi diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 6069120199bb..a5ed1b719488 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -107,6 +107,12 @@ config ARCH_EXYNOS help This enables support for ARMv8 based Samsung Exynos SoC family. +config ARCH_GOOGLE_TENSOR + bool "Google Tensor SoC fmaily" + depends on ARCH_EXYNOS + help + Support for ARMv8 based Google Tensor platforms. + config ARCH_SPARX5 bool "Microchip Sparx5 SoC family" select PINCTRL diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index 30dd6347a929..a4ee7b628114 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -13,6 +13,7 @@ subdir-y += broadcom subdir-y += cavium subdir-y += exynos subdir-y += freescale +subdir-y += google subdir-y += hisilicon subdir-y += intel subdir-y += lg diff --git a/arch/arm64/boot/dts/google/Makefile b/arch/arm64/boot/dts/google/Makefile new file mode 100644 index 000000000000..6d2026a767d4 --- /dev/null +++ b/arch/arm64/boot/dts/google/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0 + +dtb-$(CONFIG_ARCH_GOOGLE_TENSOR) += \ + gs101-oriole.dtb \ + + diff --git a/arch/arm64/boot/dts/google/gs101-oriole.dts b/arch/arm64/boot/dts/google/gs101-oriole.dts new file mode 100644 index 000000000000..e531a39a76a4 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs101-oriole.dts @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Oriole DVT Device Tree + * + * Copyright 2021-2023 Google,LLC + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include "gs101-pinctrl.h" +#include "gs101.dtsi" + +/ { + model = "Oriole DVT"; + compatible = "google,gs101-oriole", "google,gs101"; +}; + +&pinctrl_1 { + key_voldown: key-voldown-pins { + samsung,pins = "gpa7-3"; + samsung,pin-function = <0xf>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + key_volup: key-volup-pins { + samsung,pins = "gpa8-1"; + samsung,pin-function = <0xf>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; +}; + +&pinctrl_0 { + key_power: key-power-pins { + samsung,pins = "gpa10-1"; + samsung,pin-function = <0xf>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; +}; + +&gpio_keys { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&key_voldown &key_volup &key_power>; + button-vol-down { + label = "KEY_VOLUMEDOWN"; + linux,code = <114>; + gpios = <&gpa7 3 0xf>; + wakeup-source; + }; + button-vol-up { + label = "KEY_VOLUMEUP"; + linux,code = <115>; + gpios = <&gpa8 1 0xf>; + wakeup-source; + }; + button-power { + label = "KEY_POWER"; + linux,code = <116>; + gpios = <&gpa10 1 0xf>; + wakeup-source; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs101-pinctrl.dtsi b/arch/arm64/boot/dts/google/gs101-pinctrl.dtsi new file mode 100644 index 000000000000..24825205ede8 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs101-pinctrl.dtsi @@ -0,0 +1,1134 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * GS101 SoC pin-mux and pin-config device tree source + * + * Copyright 2019-2023 Google LLC + * + */ + +#include +#include +#include "gs101-pinctrl.h" + +/ { + /* GPIO_ALIVE */ + pinctrl@174d0000 { + gpa0: gpa0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + }; + gpa1: gpa1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + ; + }; + gpa2: gpa2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + ; + }; + gpa3: gpa3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + gpa4: gpa4-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + gpa5: gpa5-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = , + , + , + , + , + , + ; + }; + gpa9: gpa9-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = , + , + , + , + , + , + , + ; + }; + gpa10: gpa10-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = , + ; + }; + + uart15_bus: uart15-bus-pins { + samsung,pins = "gpa2-3", "gpa2-4"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + }; + + uart16_bus: uart16-bus-pins { + samsung,pins = "gpa3-0", "gpa3-1", "gpa3-2", "gpa3-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + uart16_bus_rts: uart1-bus-rts-pins { + samsung,pins = "gpa3-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-val = <1>; + }; + + uart16_bus_tx_dat: uart1-bus-tx-dat-pins { + samsung,pins = "gpa3-1"; + samsung,pin-val = <1>; + }; + + uart16_bus_tx_con: uart1-bus-tx-con-pins { + samsung,pins = "gpa3-1"; + samsung,pin-function = <1>; + }; + + uart17_bus: uart17-bus-pins { + samsung,pins = "gpa4-0", "gpa4-1", "gpa4-2", "gpa4-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + }; + + spi15_bus: spi15-bus-pins { + samsung,pins = "gpa4-0", "gpa4-1", "gpa4-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + spi15_cs: spi15-cs-pins { + samsung,pins = "gpa4-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + }; + /* GPIO_FAR_ALIVE */ + pinctrl@174e0000 { + gpa6: gpa6-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + }; + gpa7: gpa7-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + gpa8: gpa8-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + }; + gpa11: gpa11-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = , + ; + }; + + }; + /* GPIO_GSACORE */ + pinctrl@17a80000 { + gps0: gps0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + gps1: gps1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + gps2: gps2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + /* GPIO_GSACTRL */ + pinctrl@17940000 { + gps3: gps3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + /* GPIO_HSI1 */ + pinctrl@11840000 { + gph0: gph0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + gph1: gph1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + pcie0_clkreq: pcie0-clkreq-pins{ + samsung,pins = "gph0-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = ; + samsung,pin-con-pdn = <3>; + samsung,pin-pud-pdn = <3>; + }; + pcie0_perst: pcie0-perst-pins { + samsung,pins = "gph0-0"; + samsung,pin-function = <1>; + samsung,pin-drv = ; + samsung,pin-con-pdn = <3>; + }; + }; + /* GPIO_HSI2 */ + pinctrl@14440000 { + gph2: gph2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + gph3: gph3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + gph4: gph4-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + sd2_clk: sd2-clk-pins { + samsung,pins = "gph4-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + sd2_cmd: sd2-cmd-pins { + samsung,pins = "gph4-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = ; + }; + + sd2_bus1: sd2-bus-width1-pins { + samsung,pins = "gph4-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = ; + }; + + sd2_bus4: sd2-bus-width4-pins { + samsung,pins = "gph4-3", "gph4-4", "gph4-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = ; + }; + + sd2_clk_fast_slew_rate_1x: sd2-clk-fast-slew-rate-1x-pins { + samsung,pins = "gph4-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + sd2_clk_fast_slew_rate_2x: sd2-clk-fast-slew-rate-2x-pins { + samsung,pins = "gph4-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + sd2_clk_fast_slew_rate_3x: sd2-clk-fast-slew-rate-3x-pins { + samsung,pins = "gph4-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + sd2_clk_fast_slew_rate_4x: sd2-clk-fast-slew-rate-4x-pins { + samsung,pins = "gph4-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + ufs_rst_n: ufs-rst-n-pins { + samsung,pins = "gph3-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-con-pdn = <3>; + samsung,pin-pud-pdn = <0>; + }; + + ufs_refclk_out: ufs-refclk-out-pins { + samsung,pins = "gph3-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-con-pdn = <3>; + samsung,pin-pud-pdn = <0>; + }; + pcie1_clkreq: pcie1-clkreq-pins { + samsung,pins = "gph2-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = ; + samsung,pin-con-pdn = <3>; + samsung,pin-pud-pdn = <3>; + }; + pcie1_perst: pcie1-perst-pins { + samsung,pins = "gph2-0"; + samsung,pin-function = <1>; + samsung,pin-drv = ; + samsung,pin-con-pdn = <3>; + }; + }; + /* GPIO_PERIC0 */ + pinctrl@10840000 { + gpp0: gpp0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + gpp1: gpp1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + gpp2: gpp2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + gpp3: gpp3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + gpp4: gpp4-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + gpp5: gpp5-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + gpp6: gpp6-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + gpp7: gpp7-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + gpp8: gpp8-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + gpp9: gpp9-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + gpp10: gpp10-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + gpp11: gpp11-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + gpp12: gpp12-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + gpp13: gpp13-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + gpp14: gpp14-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + gpp15: gpp15-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + gpp16: gpp16-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + gpp17: gpp17-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + gpp18: gpp18-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + gpp19: gpp19-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + /* USI_PERIC0_UART_DBG */ + uart0_bus: uart0-bus-pins { + samsung,pins = "gpp1-2", "gpp1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + }; + + disp_te_pri_on: disp-te-pri-on-pins { + samsung,pins = "gpp0-3"; + samsung,pin-function = <0xf>; + }; + + disp_te_pri_off: disp-te-pri-off-pins { + samsung,pins = "gpp0-3"; + samsung,pin-function = <0>; + }; + + disp_te_sec_on: disp-te-sec-on-pins { + samsung,pins = "gpp0-4"; + samsung,pin-function = <0xf>; + }; + + disp_te_sec_off: disp-te-sec-off-pins { + samsung,pins = "gpp0-4"; + samsung,pin-function = <0>; + }; + + sensor_mclk1_out: sensor-mclk1-out-pins { + samsung,pins = "gpp3-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + sensor_mclk1_fn: sensor-mclk1-fn-pins { + samsung,pins = "gpp3-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + sensor_mclk2_out: sensor-mclk2-out-pins { + samsung,pins = "gpp5-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + sensor_mclk2_fn: sensor-mclk2-fn-pins { + samsung,pins = "gpp5-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + sensor_mclk3_out: sensor-mclk3-out-pins { + samsung,pins = "gpp7-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + sensor_mclk3_fn: sensor-mclk3-fn-pins { + samsung,pins = "gpp7-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + sensor_mclk4_out: sensor-mclk4-out-pins { + samsung,pins = "gpp9-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + sensor_mclk4_fn: sensor-mclk4-fn-pins { + samsung,pins = "gpp9-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + sensor_mclk5_out: sensor-mclk5-out-pins { + samsung,pins = "gpp11-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + sensor_mclk5_fn: sensor-mclk5-fn-pins { + samsung,pins = "gpp11-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + sensor_mclk6_out: sensor-mclk6-out-pins { + samsung,pins = "gpp13-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + sensor_mclk6_fn: sensor-mclk6-fn-pins { + samsung,pins = "gpp13-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + sensor_mclk7_out: sensor-mclk7-out-pins { + samsung,pins = "gpp15-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + sensor_mclk7_fn: sensor-mclk7-fn-pins { + samsung,pins = "gpp15-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + sensor_mclk8_out: sensor-mclk8-out-pins { + samsung,pins = "gpp17-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + sensor_mclk8_fn: sensor-mclk8-fn-pins { + samsung,pins = "gpp17-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + hsi2c14_bus: hsi2c14-bus-pins { + samsung,pins = "gpp18-0", "gpp18-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + uart14_bus_single: uart14-bus-pins { + samsung,pins = "gpp18-0", "gpp18-1", + "gpp18-2", "gpp18-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + }; + spi14_bus: spi14-bus-pins { + samsung,pins = "gpp18-0", "gpp18-1", "gpp18-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + spi14_cs: spi14-cs-pins { + samsung,pins = "gpp18-3"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + spi14_cs_func: spi14-cs-func-pins { + samsung,pins = "gpp18-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + hsi2c8_bus: hsi2c8-bus-pins { + samsung,pins = "gpp16-0", "gpp16-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + samsung,pin-pud-pdn = ; + }; + uart8_bus_single: uart8-bus-pins { + samsung,pins = "gpp16-0", "gpp16-1", "gpp16-2", + "gpp16-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + }; + spi8_bus: spi8-bus-pins { + samsung,pins = "gpp16-0", "gpp16-1", "gpp16-2"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + spi8_cs: spi8-cs-pins { + samsung,pins = "gpp16-3"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + spi8_cs_func: spi8-cs-func-pins { + samsung,pins = "gpp16-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + hsi2c7_bus: hsi2c7-bus-pins { + samsung,pins = "gpp14-0", "gpp14-1"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + uart7_bus_single: uart7-bus-pins { + samsung,pins = "gpp14-0", "gpp14-1", + "gpp14-2", "gpp14-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + }; + spi7_bus: spi7-bus-pins { + samsung,pins = "gpp14-0", "gpp14-1", "gpp14-2"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + spi7_cs: spi7-cs-pins { + samsung,pins = "gpp14-3"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + spi7_cs_func: spi7-cs-func-pins { + samsung,pins = "gpp14-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + hsi2c6_bus: hsi2c6-bus-pins { + samsung,pins = "gpp12-0", "gpp12-1"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + uart6_bus_single: uart6-bus-pins { + samsung,pins = "gpp12-0", "gpp12-1", + "gpp12-2", "gpp12-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + }; + spi6_bus: spi6-bus-pins { + samsung,pins = "gpp12-0", "gpp12-1", "gpp12-2"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + spi6_cs: spi6-cs-pins { + samsung,pins = "gpp12-3"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + spi6_cs_func: spi6-cs-func-pins { + samsung,pins = "gpp12-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + hsi2c5_bus: hsi2c5-bus-pins { + samsung,pins = "gpp10-0", "gpp10-1"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + uart5_bus_single: uart5-bus-pins { + samsung,pins = "gpp10-0", "gpp10-1", + "gpp10-2", "gpp10-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + }; + spi5_bus: spi5-bus-pins { + samsung,pins = "gpp10-0", "gpp10-1", "gpp10-2"; + samsung,pin-drv = ; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; + spi5_cs_func: spi5-cs-func-pins { + samsung,pins = "gpp10-3"; + samsung,pin-drv = ; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; + hsi2c4_bus: hsi2c4-bus-pins { + samsung,pins = "gpp8-0", "gpp8-1"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + uart4_bus_single: uart4-bus-pins { + samsung,pins = "gpp8-0", "gpp8-1", + "gpp8-2", "gpp8-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + }; + spi4_bus: spi4-bus-pins { + samsung,pins = "gpp8-0", "gpp8-1", "gpp8-2"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + spi4_cs: spi4-cs-pins { + samsung,pins = "gpp8-3"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + spi4_cs_func: spi4-cs-func-pins { + samsung,pins = "gpp8-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + hsi2c3_bus: hsi2c3-bus-pins { + samsung,pins = "gpp6-0", "gpp6-1"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + uart3_bus_single: uart3-bus-pins { + samsung,pins = "gpp6-0", "gpp6-1", + "gpp6-2", "gpp6-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + }; + spi3_bus: spi3-bus-pins { + samsung,pins = "gpp6-0", "gpp6-1", "gpp6-2"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + spi3_cs: spi3-cs-pins { + samsung,pins = "gpp6-3"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + spi3_cs_func: spi3-cs-func-pins { + samsung,pins = "gpp6-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + hsi2c2_bus: hsi2c2-bus-pins { + samsung,pins = "gpp4-0", "gpp4-1"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + uart2_bus_single: uart2-bus-pins { + samsung,pins = "gpp4-0", "gpp4-1", + "gpp4-2", "gpp4-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + }; + spi2_bus: spi2-bus-pins { + samsung,pins = "gpp4-0", "gpp4-1", "gpp4-2"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + spi2_cs: spi2-cs-pins { + samsung,pins = "gpp4-3"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + spi2_cs_func: spi2-cs-func-pins { + samsung,pins = "gpp4-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + hsi2c1_bus: hsi2c1-bus-pins { + samsung,pins = "gpp2-0", "gpp2-1"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + uart1_bus_single: uart1-bus-pins { + samsung,pins = "gpp2-0", "gpp2-1", + "gpp2-2", "gpp2-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + }; + spi1_bus: spi1-bus-pins { + samsung,pins = "gpp2-0", "gpp2-1", "gpp2-2"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + spi1_cs: spi1-cs-pins { + samsung,pins = "gpp2-3"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + spi1_cs_func: spi1-cs-func-pins { + samsung,pins = "gpp2-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + }; + /* GPIO_PERIC1 */ + pinctrl@10c40000 { + gpp20: gpp20-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + gpp21: gpp21-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + gpp22: gpp22-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + gpp23: gpp23-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + gpp24: gpp24-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + gpp25: gpp25-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + gpp26: gpp26-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + gpp27: gpp27-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + hsi2c13_bus: hsi2c13-bus-pins { + samsung,pins = "gpp25-0", "gpp25-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + uart13_bus_single: uart13-bus-pins { + samsung,pins = "gpp25-0", "gpp25-1", + "gpp25-2", "gpp25-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + }; + spi13_bus: spi13-bus-pins { + samsung,pins = "gpp25-0", "gpp25-1", "gpp25-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + spi13_cs: spi13-cs-pins { + samsung,pins = "gpp25-3"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + spi13_cs_func: spi13-cs-func-pins { + samsung,pins = "gpp25-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + hsi2c12_bus: hsi2c12-bus-pins { + samsung,pins = "gpp23-4", "gpp23-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + uart12_bus_single: uart12-bus-pins { + samsung,pins = "gpp23-4", "gpp23-5", + "gpp23-6", "gpp23-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + }; + spi12_bus: spi12-bus-pins { + samsung,pins = "gpp23-4", "gpp23-5", "gpp23-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + spi14_cs2: spi14-cs2-pins { + samsung,pins = "gpp23-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + spi12_cs: spi12-cs-pins { + samsung,pins = "gpp23-7"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + spi12_cs_func: spi12-cs-func-pins { + samsung,pins = "gpp23-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + hsi2c11_bus: hsi2c11-bus-pins { + samsung,pins = "gpp23-0", "gpp23-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + uart11_bus_single: uart11-bus-pins { + samsung,pins = "gpp23-0", "gpp23-1", + "gpp23-2", "gpp23-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + }; + spi11_bus: spi11-bus-pins { + samsung,pins = "gpp23-0", "gpp23-1", "gpp23-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + spi11_cs: spi11-cs-pins { + samsung,pins = "gpp23-3"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + spi11_cs_func: spi11-cs-func-pins { + samsung,pins = "gpp23-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + hsi2c10_bus: hsi2c10-bus-pins { + samsung,pins = "gpp21-0", "gpp21-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + uart10_bus_single: uart10-bus-pins { + samsung,pins = "gpp21-0", "gpp21-1", + "gpp21-2", "gpp21-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + }; + spi10_bus: spi10-bus-pins { + samsung,pins = "gpp21-0", "gpp21-1", "gpp21-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + spi10_cs: spi10-cs-pins { + samsung,pins = "gpp21-3"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + spi10_cs_func: spi10-cs-func-pins { + samsung,pins = "gpp21-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + hsi2c9_bus: hsi2c9-bus-pins { + samsung,pins = "gpp20-4", "gpp20-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + uart9_bus_single: uart9-bus-pins { + samsung,pins = "gpp20-4", "gpp20-5", + "gpp20-6", "gpp20-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + }; + spi9_bus: spi9-bus-pins { + samsung,pins = "gpp20-4", "gpp20-5", "gpp20-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + spi9_cs: spi9-cs-pins { + samsung,pins = "gpp20-7"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + spi9_cs_func: spi9-cs-func-pins { + samsung,pins = "gpp20-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + hsi2c0_bus: hsi2c0-bus-pins { + samsung,pins = "gpp20-0", "gpp20-1"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + uart0_bus_single: uart0-bus-pins { + samsung,pins = "gpp20-0", "gpp20-1", + "gpp20-2", "gpp20-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + }; + spi0_bus: spi0-bus-pins { + samsung,pins = "gpp20-0", "gpp20-1", "gpp20-2"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + spi0_cs: spi0-cs-pins { + samsung,pins = "gpp20-3"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + spi0_cs_func: spi0-cs-func-pins { + samsung,pins = "gpp20-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs101-pinctrl.h b/arch/arm64/boot/dts/google/gs101-pinctrl.h new file mode 100644 index 000000000000..acc77c684f0d --- /dev/null +++ b/arch/arm64/boot/dts/google/gs101-pinctrl.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Pinctrl binding constants for GS101 + * + * Copyright (c) 2020-2023 Google, LLC. + */ + +#ifndef __DT_BINDINGS_PINCTRL_GS101_H__ +#define __DT_BINDINGS_PINCTRL_GS101_H__ + +/* GS101 drive strengths */ +#define GS101_PIN_DRV_2_5_MA 0 +#define GS101_PIN_DRV_5_MA 1 +#define GS101_PIN_DRV_7_5_MA 2 +#define GS101_PIN_DRV_10_MA 3 + +#endif /* __DT_BINDINGS_PINCTRL_GS101_H__ */ diff --git a/arch/arm64/boot/dts/google/gs101.dtsi b/arch/arm64/boot/dts/google/gs101.dtsi new file mode 100644 index 000000000000..0bd43745f6fa --- /dev/null +++ b/arch/arm64/boot/dts/google/gs101.dtsi @@ -0,0 +1,501 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * GS101 SoC + * + * Copyright 2019-2023 Google LLC + * + */ + +#include +#include +#include +#include + +#include "gs101-pinctrl.dtsi" + +/ { + compatible = "google,gs101"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <1>; + + aliases { + pinctrl0 = &pinctrl_0; + pinctrl1 = &pinctrl_1; + pinctrl2 = &pinctrl_2; + pinctrl3 = &pinctrl_3; + pinctrl4 = &pinctrl_4; + pinctrl5 = &pinctrl_5; + pinctrl6 = &pinctrl_6; + pinctrl7 = &pinctrl_7; + + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + }; + cluster1 { + core0 { + cpu = <&cpu4>; + }; + core1 { + cpu = <&cpu5>; + }; + }; + cluster2 { + core0 { + cpu = <&cpu6>; + }; + core1 { + cpu = <&cpu7>; + }; + }; + }; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0000>; + enable-method = "psci"; + cpu-idle-states = <&ANANKE_CPU_SLEEP>; + capacity-dmips-mhz = <250>; + dynamic-power-coefficient = <70>; + }; + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0100>; + enable-method = "psci"; + cpu-idle-states = <&ANANKE_CPU_SLEEP>; + capacity-dmips-mhz = <250>; + dynamic-power-coefficient = <70>; + }; + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0200>; + enable-method = "psci"; + cpu-idle-states = <&ANANKE_CPU_SLEEP>; + capacity-dmips-mhz = <250>; + dynamic-power-coefficient = <70>; + }; + cpu3: cpu@300 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0300>; + enable-method = "psci"; + cpu-idle-states = <&ANANKE_CPU_SLEEP>; + capacity-dmips-mhz = <250>; + dynamic-power-coefficient = <70>; + }; + cpu4: cpu@400 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0400>; + enable-method = "psci"; + cpu-idle-states = <&ENYO_CPU_SLEEP>; + capacity-dmips-mhz = <620>; + dynamic-power-coefficient = <284>; + }; + cpu5: cpu@500 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0500>; + enable-method = "psci"; + cpu-idle-states = <&ENYO_CPU_SLEEP>; + capacity-dmips-mhz = <620>; + dynamic-power-coefficient = <284>; + }; + cpu6: cpu@600 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0600>; + enable-method = "psci"; + cpu-idle-states = <&HERA_CPU_SLEEP>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <650>; + }; + cpu7: cpu@700 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0700>; + enable-method = "psci"; + cpu-idle-states = <&HERA_CPU_SLEEP>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <650>; + }; + + idle-states { + entry-method = "psci"; + + ANANKE_CPU_SLEEP: cpu-ananke-sleep { + idle-state-name = "c2"; + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <70>; + exit-latency-us = <160>; + min-residency-us = <2000>; + status = "okay"; + }; + + ENYO_CPU_SLEEP: cpu-enyo-sleep { + idle-state-name = "c2"; + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <150>; + exit-latency-us = <190>; + min-residency-us = <2500>; + status = "okay"; + }; + + HERA_CPU_SLEEP: cpu-hera-sleep { + idle-state-name = "c2"; + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <235>; + exit-latency-us = <220>; + min-residency-us = <3500>; + status = "okay"; + }; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <1>; + ranges; + + tpu_fw_reserved: tpu_fw@93000000 { + reg = <0x0 0x93000000 0x1000000>; + no-map; + }; + + gsa_reserved_protected: gsa@90200000 { + reg = <0x0 0x90200000 0x400000>; + no-map; + }; + + aoc_reserve: aoc@94000000 { + reg = <0x0 0x94000000 0x03000000>; + no-map; + }; + + abl_reserved: abl@f8800000 { + reg = <0x0 0xf8800000 0x02000000>; + no-map; + }; + + dss_log_reserved: dss_log_reserved@fd3f0000 { + reg = <0 0xfd3f0000 0x0000e000>; + no-map; + }; + + debug_kinfo_reserved: debug_kinfo_reserved@fd3fe000 { + reg = <0 0xfd3fe000 0x00001000>; + no-map; + }; + + bldr_log_reserved: bldr_log_reserved@fd800000 { + reg = <0 0xfd800000 0x00100000>; + no-map; + }; + + bldr_log_hist_reserved: bldr_log_hist_reserved@fd900000 { + reg = <0 0xfd900000 0x00002000>; + no-map; + }; + }; + + /* bootloader requires ect node */ + ect { + parameter_address = <0x90000000>; + parameter_size = <0x53000>; + }; + + chosen { + bootargs = "earlycon=exynos4210,mmio32,0x10A00000 clk_ignore_unused"; + }; + + gic: interrupt-controller@10400000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x10400000 0x10000>, /* GICD */ + <0x0 0x10440000 0x100000>; /* GICR * 8 */ + interrupts = ; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + clock-frequency = <24576000>; + }; + + ext_24_5m: ext_24_5m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + clock-output-names = "oscclk"; + }; + + ext_200m: ext_200m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + clock-output-names = "ext-200m"; + }; + + /* GPIO_ALIVE */ + pinctrl_0: pinctrl@174d0000 { + compatible = "google,gs101-pinctrl"; + reg = <0x00000000 0x174d0000 0x00001000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + wakeup-interrupt-controller { + compatible = "google,gs101-wakeup-eint"; + }; + }; + + /* GPIO_FAR_ALIVE */ + pinctrl_1: pinctrl@174e0000 { + compatible = "google,gs101-pinctrl"; + reg = <0x00000000 0x174e0000 0x00001000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + wakeup-interrupt-controller { + compatible = "google,gs101-wakeup-eint"; + }; + }; + + /* GPIO_GSACORE */ + pinctrl_2: pinctrl@17a80000 { + compatible = "google,gs101-pinctrl"; + reg = <0x00000000 0x17a80000 0x00001000>; + }; + /* GPIO_GSACTRL */ + pinctrl_3: pinctrl@17940000 { + compatible = "google,gs101-pinctrl"; + reg = <0x00000000 0x17940000 0x00001000>; + }; + /* GPIO_PERIC0 */ + pinctrl_4: pinctrl@10840000 { + compatible = "google,gs101-pinctrl"; + reg = <0x00000000 0x10840000 0x00001000>; + interrupts = ; + }; + /* GPIO_PERIC1 */ + pinctrl_5: pinctrl@10c40000 { + compatible = "google,gs101-pinctrl"; + reg = <0x00000000 0x10C40000 0x00001000>; + interrupts = ; + }; + /* GPIO_HSI1 */ + pinctrl_6: pinctrl@11840000 { + compatible = "google,gs101-pinctrl"; + reg = <0x00000000 0x11840000 0x00001000>; + interrupts = ; + }; + /* GPIO_HSI2 */ + pinctrl_7: pinctrl@14440000 { + compatible = "google,gs101-pinctrl"; + reg = <0x00000000 0x14440000 0x00001000>; + interrupts = ; + }; + + arm-pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + sysreg_apm: syscon@174204e0 { + compatible = "google,gs101-apm-sysreg", + "google,gs101-sysreg", "syscon"; + reg = <0x0 0x174204e0 0x1000>; + }; + + sysreg_peric0: syscon@10821000 { + compatible = "google,gs101-peric0-sysreg", + "google,gs101-sysreg", "syscon"; + reg = <0x0 0x10821000 0x40000>; + }; + + sysreg_peric1: syscon@10c21000 { + compatible = "google,gs101-peric1-sysreg", + "google,gs101-sysreg", "syscon"; + reg = <0x0 0x10C21000 0x40000>; + }; + + /* TODO replace with CCF clock */ + dummy_clk: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12345>; + clock-output-names = "pclk"; + }; + + serial_0: serial@10a00000 { + compatible = "samsung,exynos850-uart"; + reg = <0x0 0x10a00000 0xc0>; + reg-io-width = <4>; + samsung,uart-fifosize = <256>; + interrupts = ; + clocks = <&dummy_clk 0>, <&dummy_clk 0>; + clock-names = "uart", "clk_uart_baud0"; + status = "okay"; + }; + + pmu_system_controller: system-controller@17460000 { + compatible = "google,gs101-pmu", "syscon"; + reg = <0x0 0x17460000 0x10000>; + }; + + watchdog_cl0: watchdog@10060000 { + compatible = "google,gs101-wdt"; + reg = <0x0 0x10060000 0x100>; + interrupts = ; + clocks = <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER0>, <&ext_24_5m>; + clock-names = "watchdog", "watchdog_src"; + timeout-sec = <30>; + samsung,syscon-phandle = <&pmu_system_controller>; + samsung,cluster-index = <0>; + }; + + watchdog_cl1: watchdog@10070000 { + compatible = "google,gs101-wdt"; + reg = <0x0 0x10070000 0x100>; + interrupts = ; + clocks = <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER1>, <&ext_24_5m>; + clock-names = "watchdog", "watchdog_src"; + timeout-sec = <30>; + samsung,syscon-phandle = <&pmu_system_controller>; + samsung,cluster-index = <1>; + status = "disabled"; + }; + + cmu_top: clock-controller@1e080000 { + compatible = "google,gs101-cmu-top"; + reg = <0x0 0x1e080000 0x8000>; + #clock-cells = <1>; + + clocks = <&ext_24_5m>; + clock-names = "oscclk"; + }; + + cmu_apm: clock-controller@17400000 { + compatible = "google,gs101-cmu-apm"; + reg = <0x0 0x17400000 0x8000>; + #clock-cells = <1>; + + clocks = <&ext_24_5m>; + clock-names = "oscclk"; + }; + + cmu_misc: clock-controller@10010000 { + compatible = "google,gs101-cmu-misc"; + reg = <0x0 0x10010000 0x8000>; + #clock-cells = <1>; + + clocks = <&ext_24_5m>, <&cmu_top CLK_DOUT_MISC_BUS>; + clock-names = "oscclk", "dout_cmu_misc_bus"; + }; + + dsu-pmu-0 { + compatible = "arm,dsu-pmu"; + interrupts = ; + cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; + }; + + gpio_keys: gpio_keys { + compatible = "gpio-keys"; + }; + +};