From patchwork Wed Oct 4 07:49:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Xianmiao Qu X-Patchwork-Id: 1843007 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4S0n002xlmz1yng for ; Wed, 4 Oct 2023 18:49:36 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 5D75C385771C for ; Wed, 4 Oct 2023 07:49:34 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from out30-112.freemail.mail.aliyun.com (out30-112.freemail.mail.aliyun.com [115.124.30.112]) by sourceware.org (Postfix) with ESMTPS id 68BB53858402 for ; Wed, 4 Oct 2023 07:49:21 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 68BB53858402 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.alibaba.com X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R211e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=ay29a033018045176; MF=cooper.qu@linux.alibaba.com; NM=1; PH=DS; RN=5; SR=0; TI=SMTPD_---0VtMWgvO_1696405754; Received: from localhost(mailfrom:cooper.qu@linux.alibaba.com fp:SMTPD_---0VtMWgvO_1696405754) by smtp.aliyun-inc.com; Wed, 04 Oct 2023 15:49:14 +0800 From: Xianmiao Qu To: gcc-patches@gcc.gnu.org, christoph.muellner@vrull.eu, jeffreyalaw@gmail.com, kito.cheng@sifive.com Cc: quxm Subject: [PATCH] RISC-V: THead: Fix missing CFI directives for th.sdd in prologue. Date: Wed, 4 Oct 2023 15:49:06 +0800 Message-Id: <20231004074906.15805-1-cooper.qu@linux.alibaba.com> X-Mailer: git-send-email 2.32.1 (Apple Git-133) MIME-Version: 1.0 X-Spam-Status: No, score=-19.7 required=5.0 tests=BAYES_00, ENV_AND_HDR_SPF_MATCH, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, LIKELY_SPAM_BODY, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, UNPARSEABLE_RELAY, USER_IN_DEF_SPF_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org From: quxm When generating CFI directives for the store-pair instruction, if we add two parallel REG_FRAME_RELATED_EXPR expr_lists like (expr_list:REG_FRAME_RELATED_EXPR (set (mem/c:DI (plus:DI (reg/f:DI 2 sp) (const_int 8 [0x8])) [1 S8 A64]) (reg:DI 1 ra)) (expr_list:REG_FRAME_RELATED_EXPR (set (mem/c:DI (reg/f:DI 2 sp) [1 S8 A64]) (reg:DI 8 s0)) only the first expr_list will be recognized by dwarf2out_frame_debug funciton. So, here we generate a SEQUENCE expression of REG_FRAME_RELATED_EXPR, which includes two sub-expressions of RTX_FRAME_RELATED_P. Then the dwarf2out_frame_debug_expr function will iterate through all the sub-expressions and generate the corresponding CFI directives. gcc/ * config/riscv/thead.cc (th_mempair_save_regs): Fix missing CFI directives for store-pair instruction. gcc/testsuite/ * gcc.target/riscv/xtheadmempair-4.c: New test. Reviewed-by: Christoph Müllner Tested-by: Christoph Müllner --- gcc/config/riscv/thead.cc | 11 +++---- .../gcc.target/riscv/xtheadmempair-4.c | 29 +++++++++++++++++++ 2 files changed, 35 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmempair-4.c diff --git a/gcc/config/riscv/thead.cc b/gcc/config/riscv/thead.cc index 507c912bc39..be0cd7c1276 100644 --- a/gcc/config/riscv/thead.cc +++ b/gcc/config/riscv/thead.cc @@ -366,14 +366,15 @@ th_mempair_save_regs (rtx operands[4]) { rtx set1 = gen_rtx_SET (operands[0], operands[1]); rtx set2 = gen_rtx_SET (operands[2], operands[3]); + rtx dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (2)); rtx insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set1, set2))); RTX_FRAME_RELATED_P (insn) = 1; - REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR, - copy_rtx (set1), REG_NOTES (insn)); - - REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR, - copy_rtx (set2), REG_NOTES (insn)); + XVECEXP (dwarf, 0, 0) = copy_rtx (set1); + XVECEXP (dwarf, 0, 1) = copy_rtx (set2); + RTX_FRAME_RELATED_P (XVECEXP (dwarf, 0, 0)) = 1; + RTX_FRAME_RELATED_P (XVECEXP (dwarf, 0, 1)) = 1; + add_reg_note (insn, REG_FRAME_RELATED_EXPR, dwarf); } /* Similar like riscv_restore_reg, but restores two registers from memory diff --git a/gcc/testsuite/gcc.target/riscv/xtheadmempair-4.c b/gcc/testsuite/gcc.target/riscv/xtheadmempair-4.c new file mode 100644 index 00000000000..9aef4e15f8d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadmempair-4.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-g" "-Oz" "-Os" "-flto" } } */ +/* { dg-options "-march=rv64gc_xtheadmempair -mtune=thead-c906 -funwind-tables" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_xtheadmempair -mtune=thead-c906 -funwind-tables" { target { rv32 } } } */ + +extern void bar (void); + +void foo (void) +{ + asm volatile (";my clobber list" + : : : "s0"); + bar (); + asm volatile (";my clobber list" + : : : "s0"); +} + +/* { dg-final { scan-assembler-times "th.sdd\t" 1 { target { rv64 } } } } */ +/* { dg-final { scan-assembler ".cfi_offset 8, -16" { target { rv64 } } } } */ +/* { dg-final { scan-assembler ".cfi_offset 1, -8" { target { rv64 } } } } */ + +/* { dg-final { scan-assembler-times "th.swd\t" 1 { target { rv32 } } } } */ +/* { dg-final { scan-assembler ".cfi_offset 8, -8" { target { rv32 } } } } */ +/* { dg-final { scan-assembler ".cfi_offset 1, -4" { target { rv32 } } } } */ + +/* { dg-final { scan-assembler ".cfi_restore 1" } } */ +/* { dg-final { scan-assembler ".cfi_restore 8" } } */ + +/* { dg-final { scan-assembler-times "th.ldd\t" 1 { target { rv64 } } } } */ +/* { dg-final { scan-assembler-times "th.lwd\t" 1 { target { rv32 } } } } */