From patchwork Tue Oct 3 02:27:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kito Cheng X-Patchwork-Id: 1842343 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256 header.s=google header.b=JBLpe1vJ; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4S01v94hP9z1yqM for ; Tue, 3 Oct 2023 13:27:48 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 30E7E385828D for ; Tue, 3 Oct 2023 02:27:46 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pl1-x630.google.com (mail-pl1-x630.google.com [IPv6:2607:f8b0:4864:20::630]) by sourceware.org (Postfix) with ESMTPS id 2B5103858D33 for ; Tue, 3 Oct 2023 02:27:32 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 2B5103858D33 Authentication-Results: sourceware.org; dmarc=pass (p=reject dis=none) header.from=sifive.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=sifive.com Received: by mail-pl1-x630.google.com with SMTP id d9443c01a7336-1c3bd829b86so3369005ad.0 for ; Mon, 02 Oct 2023 19:27:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1696300051; x=1696904851; darn=gcc.gnu.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=VSnzLyTABCcPPh3VhIaIlOJ8weK9dLOSzIVrtFJ0+Pw=; b=JBLpe1vJRCZAMPiBlXgwSKkDs4yc4CYDB631tpKvwkb/Qtptkz0ZQUrkqHATlP+UVh 2Z4T4NwIY4nxjWIFGHdVhS+iev/8LMQ6fdPWWWmKmhIgzWLNRwozjCEQ/l6m0zWexUQe AaLBEozDdP1uA7MK82RWtDw2IinTKRPtVfseYon261ito344u/wPvGc2cDa0urX9JQy0 4hLk9mdTIo3pBQsO4soAmOjvxdDZkbboAxR2dPhaKjZVF4sCpIell95O3GzwjreXsMhp 3TZpPK+pqLVCLFB7oknjAM9Et9/n7advTR6UFl7RcFuB1yU3dWZvYYbWFqm0B+DTFuTp JzbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696300051; x=1696904851; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=VSnzLyTABCcPPh3VhIaIlOJ8weK9dLOSzIVrtFJ0+Pw=; b=QqHMI6fUUVwHOlGlp3/sGpmMDbsh5p+augeA5KwhDW22OhzRbz7wQP1KOk3Y5GUZY3 1laBqwVg9+Aq1ZhUEIuxxeY/9yHVcgMb14Of/RiHu/1VZ+TKPWUsqcCvsFCW2GWR+VSC 5rMWmTSCcQM8y9XoEtvsV7bV0DcqkzBpBtWiGCbngxaCzihOx6QK2zcWUcO9qjMzImmy 9zoGOvBaA6/ZIU3sNJDYIck+dzixmM3pRhsjS1AlKR/hE0bDvgDsGGEE7HC4B94Dl8+8 2a8scWLevj8rxKlA1SKHqG1qSvoErXjkdyCD0/XEBUuuNmyLCqGty8sVtWQvqB4Z2HYb ArMQ== X-Gm-Message-State: AOJu0YymH1CAs2WUQAuYQL0UjsYomYpqjSY2Dil6cQaa63cupYOAPfR6 Y97LAffCg7ucP9u0ARUy+RzVln7yLaNCFUau+n1pOlfej7erCFxLkT2HuHMWOcwg1t25Wq7dqtY a5noLLbnXF+mNe/qXQ8l4HpG0OFBtvrd/pyLB4KEVKOYR+8Qw7X0cpGnwUacgbNOsOt+mIeg3aZ UgHEU= X-Google-Smtp-Source: AGHT+IHwK/etzsV7MhvZfZ2bQN2XxYbhD4SyvIxS0yTVAYC7nWd5n1RpE4vziRuBBzyAEk41+5Wsew== X-Received: by 2002:a17:902:c40d:b0:1c0:a5c9:e072 with SMTP id k13-20020a170902c40d00b001c0a5c9e072mr13365711plk.11.1696300050553; Mon, 02 Oct 2023 19:27:30 -0700 (PDT) Received: from hsinchu02.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id b19-20020a170902ed1300b001c0ce518e98sm156533pld.224.2023.10.02.19.27.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Oct 2023 19:27:30 -0700 (PDT) From: Kito Cheng To: gcc-patches@gcc.gnu.org, kito.cheng@gmail.com, palmer@dabbelt.com, jeffreyalaw@gmail.com, rdapp@ventanamicro.com, juzhe.zhong@rivai.ai Cc: Kito Cheng Subject: [PATCH] RISC-V: Fix the riscv_legitimize_poly_move issue on targets where the minimal VLEN exceeds 512. Date: Tue, 3 Oct 2023 10:27:24 +0800 Message-Id: <20231003022724.2875-1-kito.cheng@sifive.com> X-Mailer: git-send-email 2.40.1 MIME-Version: 1.0 X-Spam-Status: No, score=-12.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org riscv_legitimize_poly_move was expected to ensure the poly value is at most 32 times smaller than the minimal VLEN (32 being derived from '4096 / 128'). This assumption held when our mode modeling was not so precisely defined. However, now that we have modeled the mode size according to the correct minimal VLEN info, the size difference between different RVV modes can be up to 64 times. For instance, comparing RVVMF64BI and RVVMF1BI, the sizes are [1, 1] versus [64, 64] respectively. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_legitimize_poly_move): Bump max_power to 64. gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/autovec/bug-01.C: New. * g++.target/riscv/rvv/rvv.exp: Add autovec folder. --- gcc/config/riscv/riscv.cc | 7 ++-- .../g++.target/riscv/rvv/autovec/bug-01.C | 33 +++++++++++++++++++ gcc/testsuite/g++.target/riscv/rvv/rvv.exp | 3 ++ 3 files changed, 40 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/g++.target/riscv/rvv/autovec/bug-01.C diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index d5446b63dbf..6468702e3a3 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -2386,9 +2386,10 @@ riscv_legitimize_poly_move (machine_mode mode, rtx dest, rtx tmp, rtx src) } else { - /* FIXME: We currently DON'T support TARGET_MIN_VLEN > 4096. */ - int max_power = exact_log2 (4096 / 128); - for (int i = 0; i < max_power; i++) + /* The size difference between different RVV modes can be up to 64 times. + e.g. RVVMF64BI vs RVVMF1BI on zvl512b, which is [1, 1] vs [64, 64]. */ + int max_power = exact_log2 (64); + for (int i = 0; i <= max_power; i++) { int possible_div_factor = 1 << i; if (factor % (vlenb / possible_div_factor) == 0) diff --git a/gcc/testsuite/g++.target/riscv/rvv/autovec/bug-01.C b/gcc/testsuite/g++.target/riscv/rvv/autovec/bug-01.C new file mode 100644 index 00000000000..fd10009ddbe --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/autovec/bug-01.C @@ -0,0 +1,33 @@ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -O3" } */ + +class c { +public: + int e(); + void j(); +}; +float *d; +class k { + int f; + +public: + k(int m) : f(m) {} + float g; + float h; + void n(int m) { + for (int i; i < m; i++) { + d[0] = d[1] = d[2] = g; + d[3] = h; + d += f; + } + } +}; +c l; +void o() { + int b = l.e(); + k a(b); + for (;;) + if (b == 4) { + l.j(); + a.n(2); + } +} diff --git a/gcc/testsuite/g++.target/riscv/rvv/rvv.exp b/gcc/testsuite/g++.target/riscv/rvv/rvv.exp index 249530580d7..c30d6e93144 100644 --- a/gcc/testsuite/g++.target/riscv/rvv/rvv.exp +++ b/gcc/testsuite/g++.target/riscv/rvv/rvv.exp @@ -40,5 +40,8 @@ set CFLAGS "-march=$gcc_march -O3" dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/base/*.C]] \ "" $CFLAGS +dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/*.\[C\]]] \ + "" $CFLAGS + # All done. dg-finish