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Mon, 25 Sep 2023 02:05:43 +0000 (GMT) Message-ID: <77605bb5-c8c9-275d-f180-7c9bf13cf34e@linux.ibm.com> Date: Mon, 25 Sep 2023 10:05:43 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Content-Language: en-US To: gcc-patches Cc: Segher Boessenkool , David , "Kewen.Lin" , Peter Bergner From: HAO CHEN GUI Subject: [PATCH-2v3, rs6000] Implement 32bit inline lrint [PR88558] X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: mQcEK6q2MIaa4ogHgXM5-D7pNpAZ4R3b X-Proofpoint-GUID: n6oZD_acWQ7uMmkpuxmRwZEAQsw4r8qR X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-09-24_21,2023-09-21_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 bulkscore=0 impostorscore=0 clxscore=1015 mlxscore=0 lowpriorityscore=0 mlxlogscore=847 malwarescore=0 adultscore=0 priorityscore=1501 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2309180000 definitions=main-2309250010 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Hi, This patch implements 32bit inline lrint by "fctiw". It depends on the patch1 to do SImode move from FP registers on P7. Compared to last version, the main change is to add some test cases. https://gcc.gnu.org/pipermail/gcc-patches/2023-September/629187.html Bootstrapped and tested on powerpc64-linux BE and LE with no regressions. Thanks Gui Haochen ChangeLog rs6000: support 32bit inline lrint gcc/ PR target/88558 * config/rs6000/rs6000.md (lrintdi2): Remove TARGET_FPRND from insn condition. (lrintsi2): New insn pattern for 32bit lrint. gcc/testsuite/ PR target/106769 * gcc.target/powerpc/pr88558.h: New. * gcc.target/powerpc/pr88558-p7.c: New. * gcc.target/powerpc/pr88558-p8.c: New. patch.diff diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index ac5d29a2cf8..a41898e0e08 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -6655,10 +6655,18 @@ (define_insn "lrintdi2" [(set (match_operand:DI 0 "gpc_reg_operand" "=d") (unspec:DI [(match_operand:SFDF 1 "gpc_reg_operand" "")] UNSPEC_FCTID))] - "TARGET_HARD_FLOAT && TARGET_FPRND" + "TARGET_HARD_FLOAT" "fctid %0,%1" [(set_attr "type" "fp")]) +(define_insn "lrintsi2" + [(set (match_operand:SI 0 "gpc_reg_operand" "=d") + (unspec:SI [(match_operand:SFDF 1 "gpc_reg_operand" "")] + UNSPEC_FCTIW))] + "TARGET_HARD_FLOAT && TARGET_POPCNTD" + "fctiw %0,%1" + [(set_attr "type" "fp")]) + (define_insn "btrunc2" [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa") (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")] diff --git a/gcc/testsuite/gcc.target/powerpc/pr88558-p7.c b/gcc/testsuite/gcc.target/powerpc/pr88558-p7.c new file mode 100644 index 00000000000..3932656c5fd --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr88558-p7.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fno-math-errno -mdejagnu-cpu=power7" } */ + +/* -fno-math-errno is required to make {i,l,ll}rint{,f} inlined */ + +#include "pr88558.h" + +/* { dg-final { scan-assembler-times {\mfctid\M} 4 { target lp64 } } } */ +/* { dg-final { scan-assembler-times {\mfctid\M} 2 { target ilp32 } } } */ +/* { dg-final { scan-assembler-times {\mfctiw\M} 2 { target lp64 } } } */ +/* { dg-final { scan-assembler-times {\mfctiw\M} 4 { target ilp32 } } } */ +/* { dg-final { scan-assembler-times {\mstfiwx\M} 2 { target lp64 } } } */ +/* { dg-final { scan-assembler-times {\mstfiwx\M} 4 { target ilp32 } } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr88558-p8.c b/gcc/testsuite/gcc.target/powerpc/pr88558-p8.c new file mode 100644 index 00000000000..1afc8fd4f0d --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr88558-p8.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-O2 -fno-math-errno -mdejagnu-cpu=power8" } */ + +/* -fno-math-errno is required to make {i,l,ll}rint{,f} inlined */ + +#include "pr88558.h" + +/* { dg-final { scan-assembler-times {\mfctid\M} 4 { target lp64 } } } */ +/* { dg-final { scan-assembler-times {\mfctid\M} 2 { target ilp32 } } } */ +/* { dg-final { scan-assembler-times {\mfctiw\M} 2 { target lp64 } } } */ +/* { dg-final { scan-assembler-times {\mfctiw\M} 4 { target ilp32 } } } */ +/* { dg-final { scan-assembler-times {\mmfvsrwz\M} 2 { target lp64 } } } */ +/* { dg-final { scan-assembler-times {\mmfvsrwz\M} 4 { target ilp32 } } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr88558.h b/gcc/testsuite/gcc.target/powerpc/pr88558.h new file mode 100644 index 00000000000..9c604faadd1 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr88558.h @@ -0,0 +1,29 @@ +long int test1 (double a) +{ + return __builtin_lrint (a); +} + +long long test2 (double a) +{ + return __builtin_llrint (a); +} + +int test3 (double a) +{ + return __builtin_irint (a); +} + +long int test4 (float a) +{ + return __builtin_lrintf (a); +} + +long long test5 (float a) +{ + return __builtin_llrintf (a); +} + +int test6 (float a) +{ + return __builtin_irintf (a); +}