From patchwork Fri Sep 22 06:07:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 1837924 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=gEv9gZKG; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4RsMJT0Mghz1ynt for ; Fri, 22 Sep 2023 16:08:09 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231180AbjIVGIL (ORCPT ); Fri, 22 Sep 2023 02:08:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58368 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231239AbjIVGIJ (ORCPT ); Fri, 22 Sep 2023 02:08:09 -0400 Received: from mail-lj1-x233.google.com (mail-lj1-x233.google.com [IPv6:2a00:1450:4864:20::233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F3F22197 for ; Thu, 21 Sep 2023 23:08:02 -0700 (PDT) Received: by mail-lj1-x233.google.com with SMTP id 38308e7fff4ca-2c137f74b23so12300861fa.3 for ; Thu, 21 Sep 2023 23:08:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1695362881; x=1695967681; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=+/S5F/94lzE+JzXRkckvi7oOP9RR2RmQ+CAb+mf1D9Y=; b=gEv9gZKGOqMDxliZreFetzCoAe7ewePqsldWF2XoGUEBuKHUgLjY788ekFCbgjCWGm zHv5qCfnl7cBD2eIJmYMuu3Q/+0J+KNnGB5QQUCJgs+hx8E1ign+ikGCCRnfXs63M9Nv bIr8BP3z0iDKRFu6E3JHh/osFbGvSJg0ohFJmC1akbwSHVmdy5kMNGH6dhUzOkM6f82I LjdbUXUOXY5wZj8uslqOPy/Dv+KTfeZUwwJpQ2AaL5gK7LKANvTrnTlwGpt26kiY8PYh mrezOgsFLqCbQP5PkP4x6YViJa0Tf80QfjPeI8roQ6nYJS/vlnhKYC+yLPQ5sD3yT2JP Slcg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695362881; x=1695967681; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+/S5F/94lzE+JzXRkckvi7oOP9RR2RmQ+CAb+mf1D9Y=; b=cERhBFknuVLS1FJE1kgBrG2HGA/27DGnBMpvvOQk1Z9ZHbFbuY2ncuV8JkHt3V3jrJ RPO8YqfpU2lnTkOVyVq/vZ8Yc8U8p0tPB/Q1n9t5kXwCiaUBK9PZUvE4bdbBR3Xp0yWl D6vBbTc7igxkXK4KLtVMwNvW5KWTVPVKmcW4qe4iCZ12VCl1DnF9w8ZEE8erzuZHB3Gp RBILpgXLD3lqL5BB+A7TkT3hYwZfLIktzXljzfvrNPGdHwAsRuUaURsrgDJdiZAMs+3k kjNz7AE7UJQt0tpBL5+7xQS1W7l8so1c1kc4JLNaZxpa7jEc9mRUQBiMc+NtPGmb4awQ SgHw== X-Gm-Message-State: AOJu0Yzh9fA7ddSLTZowOaeBHCKHjFLebwIz+FW+JF32XXHa5Hm58NUs FswirA7AUOMv3c/Jr9ksANMDcQ== X-Google-Smtp-Source: AGHT+IHBp89OIbC4TGiKcIUQi24CkXikre13ErfJbelFpRJ1wSI42Wf8MoUBJiXAd/vbx7JP0ZYcRQ== X-Received: by 2002:a2e:8941:0:b0:2c0:7d6:570a with SMTP id b1-20020a2e8941000000b002c007d6570amr6912060ljk.33.1695362881301; Thu, 21 Sep 2023 23:08:01 -0700 (PDT) Received: from [192.168.1.2] (c-05d8225c.014-348-6c756e10.bbcust.telenor.se. [92.34.216.5]) by smtp.gmail.com with ESMTPSA id w22-20020a05651c103600b002b9f4841913sm754329ljm.1.2023.09.21.23.08.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Sep 2023 23:08:00 -0700 (PDT) From: Linus Walleij Date: Fri, 22 Sep 2023 08:07:56 +0200 Subject: [PATCH v2 1/2] gpio: Rewrite IXP4xx GPIO bindings in schema MIME-Version: 1.0 Message-Id: <20230922-ixp4xx-gpio-clocks-v2-1-0215ee10976d@linaro.org> References: <20230922-ixp4xx-gpio-clocks-v2-0-0215ee10976d@linaro.org> In-Reply-To: <20230922-ixp4xx-gpio-clocks-v2-0-0215ee10976d@linaro.org> To: Linus Walleij , Imre Kaloz , Krzysztof Halasa , Bartosz Golaszewski , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, Linus Walleij , Rob Herring X-Mailer: b4 0.12.3 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This rewrites the IXP4xx GPIO bindings to use YAML schema, and adds two new properties to enable fixed clock output on pins 14 and 15. Reviewed-by: Rob Herring Signed-off-by: Linus Walleij --- .../devicetree/bindings/gpio/intel,ixp4xx-gpio.txt | 38 ----------- .../bindings/gpio/intel,ixp4xx-gpio.yaml | 73 ++++++++++++++++++++++ MAINTAINERS | 2 +- 3 files changed, 74 insertions(+), 39 deletions(-) diff --git a/Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.txt b/Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.txt deleted file mode 100644 index 8dc41ed99685..000000000000 --- a/Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.txt +++ /dev/null @@ -1,38 +0,0 @@ -Intel IXP4xx XScale Networking Processors GPIO - -This GPIO controller is found in the Intel IXP4xx processors. -It supports 16 GPIO lines. - -The interrupt portions of the GPIO controller is hierarchical: -the synchronous edge detector is part of the GPIO block, but the -actual enabling/disabling of the interrupt line is done in the -main IXP4xx interrupt controller which has a 1:1 mapping for -the first 12 GPIO lines to 12 system interrupts. - -The remaining 4 GPIO lines can not be used for receiving -interrupts. - -The interrupt parent of this GPIO controller must be the -IXP4xx interrupt controller. - -Required properties: - -- compatible : Should be - "intel,ixp4xx-gpio" -- reg : Should contain registers location and length -- gpio-controller : marks this as a GPIO controller -- #gpio-cells : Should be 2, see gpio/gpio.txt -- interrupt-controller : marks this as an interrupt controller -- #interrupt-cells : a standard two-cell interrupt, see - interrupt-controller/interrupts.txt - -Example: - -gpio0: gpio@c8004000 { - compatible = "intel,ixp4xx-gpio"; - reg = <0xc8004000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; -}; diff --git a/Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.yaml b/Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.yaml new file mode 100644 index 000000000000..bfcb1f364c3a --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/intel,ixp4xx-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel IXP4xx XScale Networking Processors GPIO Controller + +description: | + This GPIO controller is found in the Intel IXP4xx + processors. It supports 16 GPIO lines. + The interrupt portions of the GPIO controller is hierarchical. + The synchronous edge detector is part of the GPIO block, but the + actual enabling/disabling of the interrupt line is done in the + main IXP4xx interrupt controller which has a 1-to-1 mapping for + the first 12 GPIO lines to 12 system interrupts. + The remaining 4 GPIO lines can not be used for receiving + interrupts. + The interrupt parent of this GPIO controller must be the + IXP4xx interrupt controller. + GPIO 14 and 15 can be used as clock outputs rather than GPIO, + and this can be enabled by a special flag. + +maintainers: + - Linus Walleij + +properties: + compatible: + const: intel,ixp4xx-gpio + + reg: + maxItems: 1 + + gpio-controller: true + + "#gpio-cells": + const: 2 + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + intel,ixp4xx-gpio14-clkout: + description: If defined, enables clock output on GPIO 14 + instead of GPIO. + type: boolean + + intel,ixp4xx-gpio15-clkout: + description: If defined, enables clock output on GPIO 15 + instead of GPIO. + type: boolean + +required: + - compatible + - reg + - "#gpio-cells" + - interrupt-controller + - "#interrupt-cells" + +additionalProperties: false + +examples: + - | + #include + gpio@c8004000 { + compatible = "intel,ixp4xx-gpio"; + reg = <0xc8004000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 90f13281d297..4e216887eb76 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2215,7 +2215,7 @@ M: Krzysztof Halasa L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml -F: Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.txt +F: Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.yaml F: Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml F: Documentation/devicetree/bindings/memory-controllers/intel,ixp4xx-expansion* F: Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.yaml From patchwork Fri Sep 22 06:07:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 1837925 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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[92.34.216.5]) by smtp.gmail.com with ESMTPSA id w22-20020a05651c103600b002b9f4841913sm754329ljm.1.2023.09.21.23.08.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Sep 2023 23:08:01 -0700 (PDT) From: Linus Walleij Date: Fri, 22 Sep 2023 08:07:57 +0200 Subject: [PATCH v2 2/2] gpio: ixp4xx: Handle clock output on pin 14 and 15 MIME-Version: 1.0 Message-Id: <20230922-ixp4xx-gpio-clocks-v2-2-0215ee10976d@linaro.org> References: <20230922-ixp4xx-gpio-clocks-v2-0-0215ee10976d@linaro.org> In-Reply-To: <20230922-ixp4xx-gpio-clocks-v2-0-0215ee10976d@linaro.org> To: Linus Walleij , Imre Kaloz , Krzysztof Halasa , Bartosz Golaszewski , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, Linus Walleij X-Mailer: b4 0.12.3 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This makes it possible to provide basic clock output on pins 14 and 15. The clocks are typically used by random electronics, not modeled in the device tree, so they just need to be provided on request. Signed-off-by: Linus Walleij --- drivers/gpio/gpio-ixp4xx.c | 40 ++++++++++++++++++++++++++++++++++++++-- 1 file changed, 38 insertions(+), 2 deletions(-) diff --git a/drivers/gpio/gpio-ixp4xx.c b/drivers/gpio/gpio-ixp4xx.c index dde6cf3a5779..d69954d19144 100644 --- a/drivers/gpio/gpio-ixp4xx.c +++ b/drivers/gpio/gpio-ixp4xx.c @@ -38,6 +38,18 @@ #define IXP4XX_GPIO_STYLE_MASK GENMASK(2, 0) #define IXP4XX_GPIO_STYLE_SIZE 3 +/* + * Clock output control register defines. + */ +#define IXP4XX_GPCLK_CLK0DC_SHIFT 0 +#define IXP4XX_GPCLK_CLK0TC_SHIFT 4 +#define IXP4XX_GPCLK_CLK0_MASK GENMASK(7, 0) +#define IXP4XX_GPCLK_MUX14 BIT(8) +#define IXP4XX_GPCLK_CLK1DC_SHIFT 16 +#define IXP4XX_GPCLK_CLK1TC_SHIFT 20 +#define IXP4XX_GPCLK_CLK1_MASK GENMASK(23, 16) +#define IXP4XX_GPCLK_MUX15 BIT(24) + /** * struct ixp4xx_gpio - IXP4 GPIO state container * @dev: containing device for this instance @@ -202,6 +214,7 @@ static int ixp4xx_gpio_probe(struct platform_device *pdev) struct ixp4xx_gpio *g; struct gpio_irq_chip *girq; struct device_node *irq_parent; + u32 val; int ret; g = devm_kzalloc(dev, sizeof(*g), GFP_KERNEL); @@ -227,11 +240,34 @@ static int ixp4xx_gpio_probe(struct platform_device *pdev) /* * Make sure GPIO 14 and 15 are NOT used as clocks but GPIO on - * specific machines. + * specific machines. For others, use the boot defaults as + * starting point. */ if (of_machine_is_compatible("dlink,dsm-g600-a") || of_machine_is_compatible("iom,nas-100d")) - __raw_writel(0x0, g->base + IXP4XX_REG_GPCLK); + val = 0; + else + val = __raw_readl(g->base + IXP4XX_REG_GPCLK); + + /* + * Enable clock outputs with default timings of requested clock. + * If you need control over TC and DC, add these to the device + * tree bindings and use them here. + */ + if (of_property_read_bool(np, "intel,ixp4xx-gpio14-clkout")) { + val &= ~IXP4XX_GPCLK_CLK0_MASK; + val |= (0 << IXP4XX_GPCLK_CLK0DC_SHIFT); + val |= (1 << IXP4XX_GPCLK_CLK0TC_SHIFT); + val |= IXP4XX_GPCLK_MUX14; + } + + if (of_property_read_bool(np, "intel,ixp4xx-gpio15-clkout")) { + val &= ~IXP4XX_GPCLK_CLK1_MASK; + val |= (0 << IXP4XX_GPCLK_CLK1DC_SHIFT); + val |= (1 << IXP4XX_GPCLK_CLK1TC_SHIFT); + val |= IXP4XX_GPCLK_MUX15; + } + __raw_writel(val, g->base + IXP4XX_REG_GPCLK); /* * This is a very special big-endian ARM issue: when the IXP4xx is